Re: [Qemu-devel] [PATCH V1 3/4] target-arm: Add support for PMU register PMINTENSET_EL1

[Peter Maydell]

On 12 January 2017 at 07:04, Wei Huang  wrote:
> This patch adds access support for PMINTENSET_EL1.
>
> Signed-off-by: Wei Huang 
> ---
>  target/arm/helper.c | 8 
>  1 file changed, 8 insertions(+)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 9044a33..22c66e3 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -1261,9 +1261,17 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
>.writefn = pmuserenr_write, .raw_writefn = raw_write },
>  { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 
> = 1,
>.access = PL1_RW, .accessfn = access_tpm,
> +  .type = ARM_CP_ALIAS,
>.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
>.resetvalue = 0,
>.writefn = pmintenset_write, .raw_writefn = raw_write },
> +{ .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64,
> +  .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1,
> +  .access = PL1_RW, .accessfn = access_tpm,
> +  .type = ARM_CP_IO,
> +  .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
> +  .writefn = pmintenset_write, .raw_writefn = raw_write,
> +  .resetvalue = 0x0 },
>  { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 
> = 2,
>.access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
>.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
> --

c9_pminten needs to become 64 bits.

We should add PMINTENCLR_EL1 too -- it's a bit weird to provide the
SET function but not its parter CLR operation.

thanks
-- PMM

[Qemu-devel] [PATCH V1 3/4] target-arm: Add support for PMU register PMINTENSET_EL1

[Wei Huang]

This patch adds access support for PMINTENSET_EL1.

Signed-off-by: Wei Huang 
---
 target/arm/helper.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 9044a33..22c66e3 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1261,9 +1261,17 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
   .writefn = pmuserenr_write, .raw_writefn = raw_write },
 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 
1,
   .access = PL1_RW, .accessfn = access_tpm,
+  .type = ARM_CP_ALIAS,
   .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
   .resetvalue = 0,
   .writefn = pmintenset_write, .raw_writefn = raw_write },
+{ .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64,
+  .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1,
+  .access = PL1_RW, .accessfn = access_tpm,
+  .type = ARM_CP_IO,
+  .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
+  .writefn = pmintenset_write, .raw_writefn = raw_write,
+  .resetvalue = 0x0 },
 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 
2,
   .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
   .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
-- 
1.8.3.1