Re: [Qemu-devel] [PATCH microblaze v1 1/1] net: xilinx_axienet.c: Add phy soft reset bit clearing
On Tue, Apr 08, 2014 at 06:52:39PM -0700, Peter Crosthwaite wrote: > From: Nathan Rossi > > Clear the BMCR Reset when writing to registers. > > Signed-off-by: Nathan Rossi > [ PC: > * Trivial style fixes to commit message > ] > Signed-off-by: Peter Crosthwaite > --- > > hw/net/xilinx_axienet.c | 3 +++ > 1 file changed, 3 insertions(+) Thanks, applied to my net tree: https://github.com/stefanha/qemu/commits/net Stefan
Re: [Qemu-devel] [PATCH microblaze v1 1/1] net: xilinx_axienet.c: Add phy soft reset bit clearing
On Thu, Apr 24, 2014 at 02:03:45PM +0200, Stefan Hajnoczi wrote: > On Tue, Apr 08, 2014 at 06:52:39PM -0700, Peter Crosthwaite wrote: > > From: Nathan Rossi > > > > Clear the BMCR Reset when writing to registers. > > > > Signed-off-by: Nathan Rossi > > [ PC: > > * Trivial style fixes to commit message > > ] > > Signed-off-by: Peter Crosthwaite > > --- > > > > hw/net/xilinx_axienet.c | 3 +++ > > 1 file changed, 3 insertions(+) > > Will this patch go through Edgar's MicroBlaze tree? Just wanted to > check I'm not holding it up :). > Hi Stefan, Feel free to take it via your tree. Reviewed-by: Edgar E. Iglesias Thanks, Edgar
Re: [Qemu-devel] [PATCH microblaze v1 1/1] net: xilinx_axienet.c: Add phy soft reset bit clearing
On Tue, Apr 08, 2014 at 06:52:39PM -0700, Peter Crosthwaite wrote: > From: Nathan Rossi > > Clear the BMCR Reset when writing to registers. > > Signed-off-by: Nathan Rossi > [ PC: > * Trivial style fixes to commit message > ] > Signed-off-by: Peter Crosthwaite > --- > > hw/net/xilinx_axienet.c | 3 +++ > 1 file changed, 3 insertions(+) Will this patch go through Edgar's MicroBlaze tree? Just wanted to check I'm not holding it up :). Stefan
Re: [Qemu-devel] [PATCH microblaze v1 1/1] net: xilinx_axienet.c: Add phy soft reset bit clearing
On Tue, Apr 08, 2014 at 06:52:39PM -0700, Peter Crosthwaite wrote: > From: Nathan Rossi > > Clear the BMCR Reset when writing to registers. > > Signed-off-by: Nathan Rossi > [ PC: > * Trivial style fixes to commit message > ] > Signed-off-by: Peter Crosthwaite > --- > > hw/net/xilinx_axienet.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c > index 839d97c..0f485a0 100644 > --- a/hw/net/xilinx_axienet.c > +++ b/hw/net/xilinx_axienet.c > @@ -142,6 +142,9 @@ tdk_write(struct PHY *phy, unsigned int req, unsigned int > data) > phy->regs[regnum] = data; > break; > } > + > +/* Unconditionally clear regs[BMCR][BMCR_RESET] */ > +phy->regs[0] &= ~0x8000; > } > > static void > -- Reviewed-by: Beniamino Galvani Ideally we should also restore default values of registers after a reset, but probably it is not required for the guest to operate properly. Beniamino
[Qemu-devel] [PATCH microblaze v1 1/1] net: xilinx_axienet.c: Add phy soft reset bit clearing
From: Nathan Rossi Clear the BMCR Reset when writing to registers. Signed-off-by: Nathan Rossi [ PC: * Trivial style fixes to commit message ] Signed-off-by: Peter Crosthwaite --- hw/net/xilinx_axienet.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c index 839d97c..0f485a0 100644 --- a/hw/net/xilinx_axienet.c +++ b/hw/net/xilinx_axienet.c @@ -142,6 +142,9 @@ tdk_write(struct PHY *phy, unsigned int req, unsigned int data) phy->regs[regnum] = data; break; } + +/* Unconditionally clear regs[BMCR][BMCR_RESET] */ +phy->regs[0] &= ~0x8000; } static void -- 1.9.1.1.gbb9f595
