Re: [Qemu-devel] [PATCH v1 03/28] target/riscv: Add the force HS exception mode
On Fri, 23 Aug 2019 16:37:57 PDT (-0700), Alistair Francis wrote: Signed-off-by: Alistair Francis There's really no description of what this does, either in the commit message or as a comment. --- target/riscv/cpu.h| 2 ++ target/riscv/cpu_bits.h | 6 ++ target/riscv/cpu_helper.c | 23 +++ 3 files changed, 31 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0ef1ecb0e0..3a95c41428 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -261,6 +261,8 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); bool riscv_cpu_fp_enabled(CPURISCVState *env); bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); +bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); +void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 1fbde516be..204d9d9a79 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -428,6 +428,12 @@ #define VIRT_MODE_SHIFT 0 #define VIRT_MODE_MASK (1 << VIRT_MODE_SHIFT) +/* HS-level exception modes */ +#define CLEAR_HS_EXCEP0 +#define FORCE_HS_EXCEP1 +#define FORCE_HS_EXCEP_SHIFT 1 +#define FORCE_HS_EXCEP_MASK (1 << FORCE_HS_EXCEP_SHIFT) + /* RV32 satp CSR field masks */ #define SATP32_MODE 0x8000 #define SATP32_ASID 0x7fc0 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 7b0bb14c01..5bcfc2e090 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -104,6 +104,29 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) env->virt |= enable << VIRT_MODE_SHIFT; } +bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env) +{ +bool tmp; + +if (!riscv_has_ext(env, RVH)) { +return false; +} + +tmp = (env->virt & FORCE_HS_EXCEP_MASK) >> FORCE_HS_EXCEP_SHIFT; + +return tmp == FORCE_HS_EXCEP; +} + +void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable) +{ +if (!riscv_has_ext(env, RVH)) { +return; +} + +env->virt &= ~FORCE_HS_EXCEP_MASK; +env->virt |= enable << FORCE_HS_EXCEP_SHIFT; +} + int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) { CPURISCVState *env = &cpu->env;
Re: [Qemu-devel] [PATCH v1 03/28] target/riscv: Add the force HS exception mode
On Sat, Aug 24, 2019 at 7:50 AM Alistair Francis wrote: > Signed-off-by: Alistair Francis > --- > target/riscv/cpu.h| 2 ++ > target/riscv/cpu_bits.h | 6 ++ > target/riscv/cpu_helper.c | 23 +++ > 3 files changed, 31 insertions(+) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 0ef1ecb0e0..3a95c41428 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -261,6 +261,8 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int > interrupt_request); > bool riscv_cpu_fp_enabled(CPURISCVState *env); > bool riscv_cpu_virt_enabled(CPURISCVState *env); > void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); > +bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); > +void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); > int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); > hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); > void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 1fbde516be..204d9d9a79 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -428,6 +428,12 @@ > #define VIRT_MODE_SHIFT 0 > #define VIRT_MODE_MASK (1 << VIRT_MODE_SHIFT) > > +/* HS-level exception modes */ > +#define CLEAR_HS_EXCEP0 > +#define FORCE_HS_EXCEP1 > +#define FORCE_HS_EXCEP_SHIFT 1 > +#define FORCE_HS_EXCEP_MASK (1 << FORCE_HS_EXCEP_SHIFT) > + > /* RV32 satp CSR field masks */ > #define SATP32_MODE 0x8000 > #define SATP32_ASID 0x7fc0 > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 7b0bb14c01..5bcfc2e090 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -104,6 +104,29 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, > bool enable) > env->virt |= enable << VIRT_MODE_SHIFT; > } > > +bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env) > +{ > +bool tmp; > + > +if (!riscv_has_ext(env, RVH)) { > +return false; > +} > + > +tmp = (env->virt & FORCE_HS_EXCEP_MASK) >> FORCE_HS_EXCEP_SHIFT; > + > +return tmp == FORCE_HS_EXCEP; > +} > + > +void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable) > +{ > +if (!riscv_has_ext(env, RVH)) { > +return; > +} > + > +env->virt &= ~FORCE_HS_EXCEP_MASK; > +env->virt |= enable << FORCE_HS_EXCEP_SHIFT; > +} > + > int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) > { > CPURISCVState *env = &cpu->env; > -- > 2.22.0 > > > I have the same option as [PATCH 2/28]. Why not to use get_field and set_field ? chihmin
[Qemu-devel] [PATCH v1 03/28] target/riscv: Add the force HS exception mode
Signed-off-by: Alistair Francis --- target/riscv/cpu.h| 2 ++ target/riscv/cpu_bits.h | 6 ++ target/riscv/cpu_helper.c | 23 +++ 3 files changed, 31 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0ef1ecb0e0..3a95c41428 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -261,6 +261,8 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); bool riscv_cpu_fp_enabled(CPURISCVState *env); bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); +bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); +void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 1fbde516be..204d9d9a79 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -428,6 +428,12 @@ #define VIRT_MODE_SHIFT 0 #define VIRT_MODE_MASK (1 << VIRT_MODE_SHIFT) +/* HS-level exception modes */ +#define CLEAR_HS_EXCEP0 +#define FORCE_HS_EXCEP1 +#define FORCE_HS_EXCEP_SHIFT 1 +#define FORCE_HS_EXCEP_MASK (1 << FORCE_HS_EXCEP_SHIFT) + /* RV32 satp CSR field masks */ #define SATP32_MODE 0x8000 #define SATP32_ASID 0x7fc0 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 7b0bb14c01..5bcfc2e090 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -104,6 +104,29 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) env->virt |= enable << VIRT_MODE_SHIFT; } +bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env) +{ +bool tmp; + +if (!riscv_has_ext(env, RVH)) { +return false; +} + +tmp = (env->virt & FORCE_HS_EXCEP_MASK) >> FORCE_HS_EXCEP_SHIFT; + +return tmp == FORCE_HS_EXCEP; +} + +void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable) +{ +if (!riscv_has_ext(env, RVH)) { +return; +} + +env->virt &= ~FORCE_HS_EXCEP_MASK; +env->virt |= enable << FORCE_HS_EXCEP_SHIFT; +} + int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) { CPURISCVState *env = &cpu->env; -- 2.22.0