Re: [Qemu-devel] [PATCH v1 1/2] target-ppc: Add xvtstdc[sp, dp] instructions

[Nikunj A Dadhania]

Richard Henderson  writes:

> On 01/12/2017 07:54 PM, Nikunj A Dadhania wrote:
>> +uint32_t match = 0; \
>> +\
>> +getVSR(xbn, , env);  \
>> +memset(, 0, sizeof(xt)); \
>> +dcmx = DCMX_XV(opcode); \
>> +\
>> +for (i = 0; i < nels; i++) {\
>> +sign = tp##_is_neg(xb.fld); \
>> +if (tp##_is_any_nan(xb.fld)) {  \
>> +match = extract32(dcmx, 6, 1);  \
>
> Failing to clear match for each elt.

Oops, will send an update :(

Regards,
Nikunj

Re: [Qemu-devel] [PATCH v1 1/2] target-ppc: Add xvtstdc[sp, dp] instructions

[Richard Henderson]

On 01/12/2017 07:54 PM, Nikunj A Dadhania wrote:

+uint32_t match = 0; \
+\
+getVSR(xbn, , env);  \
+memset(, 0, sizeof(xt)); \
+dcmx = DCMX_XV(opcode); \
+\
+for (i = 0; i < nels; i++) {\
+sign = tp##_is_neg(xb.fld); \
+if (tp##_is_any_nan(xb.fld)) {  \
+match = extract32(dcmx, 6, 1);  \


Failing to clear match for each elt.


r~

[Qemu-devel] [PATCH v1 1/2] target-ppc: Add xvtstdc[sp, dp] instructions

[Nikunj A Dadhania]

xvtstdcsp: VSX Vector Test Data Class Single-Precision
xvtstdcdp: VSX Vector Test Data Class Double-Precision

Signed-off-by: Nikunj A Dadhania 
---
 target/ppc/fpu_helper.c | 39 +
 target/ppc/helper.h |  2 ++
 target/ppc/internal.h   |  5 +++--
 target/ppc/translate/vsx-impl.inc.c |  2 ++
 target/ppc/translate/vsx-ops.inc.c  |  8 
 5 files changed, 54 insertions(+), 2 deletions(-)

diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index ffcf9ca..75c70e4 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -3187,3 +3187,42 @@ void helper_xvxsigsp(CPUPPCState *env, uint32_t opcode)
 }
 putVSR(xT(opcode), , env);
 }
+
+/* VSX_TEST_DC - VSX floating point test data class
+ *   op- instruction mnemonic
+ *   nels  - number of elements (1, 2 or 4)
+ *   xbn   - VSR register number
+ *   tp- type (float32 or float64)
+ *   fld   - vsr_t field (VsrD(*) or VsrW(*))
+ *   tfld   - target vsr_t field (VsrD(*) or VsrW(*))
+ *   fld_max - target field max
+ */
+#define VSX_TEST_DC(op, nels, xbn, tp, fld, tfld, fld_max)  \
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{   \
+ppc_vsr_t xt, xb;   \
+uint32_t i, sign, dcmx; \
+uint32_t match = 0; \
+\
+getVSR(xbn, , env);  \
+memset(, 0, sizeof(xt)); \
+dcmx = DCMX_XV(opcode); \
+\
+for (i = 0; i < nels; i++) {\
+sign = tp##_is_neg(xb.fld); \
+if (tp##_is_any_nan(xb.fld)) {  \
+match = extract32(dcmx, 6, 1);  \
+} else if (tp##_is_infinity(xb.fld)) {  \
+match = extract32(dcmx, 4 + !sign, 1);  \
+} else if (tp##_is_zero(xb.fld)) {  \
+match = extract32(dcmx, 2 + !sign, 1);  \
+} else if (tp##_is_zero_or_denormal(xb.fld)) {  \
+match = extract32(dcmx, 0 + !sign, 1);  \
+}   \
+xt.tfld = match ? fld_max : 0;  \
+}   \
+putVSR(xT(opcode), , env);   \
+}
+
+VSX_TEST_DC(xvtstdcdp, 2, xB(opcode), float64, VsrD(i), VsrD(i), UINT64_MAX)
+VSX_TEST_DC(xvtstdcsp, 4, xB(opcode), float32, VsrW(i), VsrW(i), UINT32_MAX)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 9d4ed08..165e4a5 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -546,6 +546,8 @@ DEF_HELPER_2(xvcvsxdsp, void, env, i32)
 DEF_HELPER_2(xvcvuxdsp, void, env, i32)
 DEF_HELPER_2(xvcvsxwsp, void, env, i32)
 DEF_HELPER_2(xvcvuxwsp, void, env, i32)
+DEF_HELPER_2(xvtstdcsp, void, env, i32)
+DEF_HELPER_2(xvtstdcdp, void, env, i32)
 DEF_HELPER_2(xvrspi, void, env, i32)
 DEF_HELPER_2(xvrspic, void, env, i32)
 DEF_HELPER_2(xvrspim, void, env, i32)
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index c22d74e..4c3811a 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -68,7 +68,7 @@ static inline uint32_t name(uint32_t opcode)  
\
 ((opcode >> (shift2)) & ((1 << (nb2)) - 1));  \
 }
 
-#define EXTRACT_HELPER_DXFORM(name,   \
+#define EXTRACT_HELPER_SPLIT_3(name,  \
   d0_bits, shift_op_d0, shift_d0, \
   d1_bits, shift_op_d1, shift_d1, \
   d2_bits, shift_op_d2, shift_d2) \
@@ -156,7 +156,7 @@ EXTRACT_HELPER(FPFLM, 17, 8);
 EXTRACT_HELPER(FPW, 16, 1);
 
 /* addpcis */
-EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
+EXTRACT_HELPER_SPLIT_3(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
 #if defined(TARGET_PPC64)
 /* darn */
 EXTRACT_HELPER(L, 16, 2);
@@ -198,6 +198,7 @@ EXTRACT_HELPER(UIM, 16, 2);
 EXTRACT_HELPER(SHW, 8, 2);
 EXTRACT_HELPER(SP, 19, 2);
 EXTRACT_HELPER(IMM8, 11, 8);
+EXTRACT_HELPER_SPLIT_3(DCMX_XV, 5, 16, 0, 1, 2, 5, 1, 6, 6);
 
 typedef union _ppc_vsr_t {
 uint8_t u8[16];
diff --git a/target/ppc/translate/vsx-impl.inc.c 
b/target/ppc/translate/vsx-impl.inc.c
index 9bcc5af..adb6fc7 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -928,6 +928,8 @@ GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)