subject:"\[Qemu\-devel\] \[PATCH v2\] x86\: Intel AVX512

Re: [Qemu-devel] [PATCH v2] x86: Intel AVX512_BF16 feature enabling

2019-08-19 Thread Paolo Bonzini

On 25/07/19 08:14, Jing Liu wrote:
> Intel CooperLake cpu adds AVX512_BF16 instruction, defining as
> CPUID.(EAX=7,ECX=1):EAX[bit 05].
> 
> The patch adds a property for setting the subleaf of CPUID leaf 7 in
> case that people would like to specify it.
> 
> The release spec link as follows,
> https://software.intel.com/sites/default/files/managed/c5/15/\
> architecture-instruction-set-extensions-programming-reference.pdf
> 
> Signed-off-by: Jing Liu 
> ---
>  target/i386/cpu.c | 39 ++-
>  target/i386/cpu.h |  7 +++
>  target/i386/kvm.c |  3 ++-
>  3 files changed, 47 insertions(+), 2 deletions(-)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 805ce95..517dedb 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -770,6 +770,7 @@ static void x86_cpu_vendor_words2str(char *dst, uint32_t 
> vendor1,
>/* CPUID_7_0_ECX_OSPKE is dynamic */ \
>CPUID_7_0_ECX_LA57)
>  #define TCG_7_0_EDX_FEATURES 0
> +#define TCG_7_1_EAX_FEATURES 0
>  #define TCG_APM_FEATURES 0
>  #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
>  #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
> @@ -1095,6 +1096,25 @@ static FeatureWordInfo 
> feature_word_info[FEATURE_WORDS] = {
>  },
>  .tcg_features = TCG_7_0_EDX_FEATURES,
>  },
> +[FEAT_7_1_EAX] = {
> +.type = CPUID_FEATURE_WORD,
> +.feat_names = {
> +NULL, NULL, NULL, NULL,
> +NULL, "avx512-bf16", NULL, NULL,
> +NULL, NULL, NULL, NULL,
> +NULL, NULL, NULL, NULL,
> +NULL, NULL, NULL, NULL,
> +NULL, NULL, NULL, NULL,
> +NULL, NULL, NULL, NULL,
> +NULL, NULL, NULL, NULL,
> +},
> +.cpuid = {
> +.eax = 7,
> +.needs_ecx = true, .ecx = 1,
> +.reg = R_EAX,
> +},
> +.tcg_features = TCG_7_1_EAX_FEATURES,
> +},
>  [FEAT_8000_0007_EDX] = {
>  .type = CPUID_FEATURE_WORD,
>  .feat_names = {
> @@ -4293,13 +4313,19 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, 
> uint32_t count,
>  case 7:
>  /* Structured Extended Feature Flags Enumeration Leaf */
>  if (count == 0) {
> -*eax = 0; /* Maximum ECX value for sub-leaves */
> +/* Maximum ECX value for sub-leaves */
> +*eax = env->cpuid_level_func7;
>  *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
>  *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
>  if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
>  *ecx |= CPUID_7_0_ECX_OSPKE;
>  }
>  *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
> +} else if (count == 1) {
> +*eax = env->features[FEAT_7_1_EAX];
> +*ebx = 0;
> +*ecx = 0;
> +*edx = 0;
>  } else {
>  *eax = 0;
>  *ebx = 0;
> @@ -4949,6 +4975,11 @@ static void x86_cpu_adjust_feat_level(X86CPU *cpu, 
> FeatureWord w)
>  x86_cpu_adjust_level(cpu, >cpuid_min_xlevel2, eax);
>  break;
>  }
> +
> +if (eax == 7) {
> +x86_cpu_adjust_level(cpu, >cpuid_min_level_func7,
> + fi->cpuid.ecx);
> +}
>  }
>  
>  /* Calculate XSAVE components based on the configured CPU feature flags */
> @@ -5067,6 +5098,7 @@ static void x86_cpu_expand_features(X86CPU *cpu, Error 
> **errp)
>  x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
>  x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
>  x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
> +x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
>  x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
>  x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
>  x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
> @@ -5098,6 +5130,9 @@ static void x86_cpu_expand_features(X86CPU *cpu, Error 
> **errp)
>  }
>  
>  /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
> +if (env->cpuid_level_func7 == UINT32_MAX) {
> +env->cpuid_level_func7 = env->cpuid_min_level_func7;
> +}
>  if (env->cpuid_level == UINT32_MAX) {
>  env->cpuid_level = env->cpuid_min_level;
>  }
> @@ -5869,6 +5904,8 @@ static Property x86_cpu_properties[] = {
>  DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
>  DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 
> 0),
>  DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
> +DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7,
> +   UINT32_MAX),
>  DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
>  DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
>  DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
> diff --git

Re: [Qemu-devel] [PATCH v2] x86: Intel AVX512_BF16 feature enabling

2019-08-19 Thread Jing Liu


Ping~ :)

Thanks,
Jing

On 7/25/2019 2:14 PM, Jing Liu wrote:

Intel CooperLake cpu adds AVX512_BF16 instruction, defining as
CPUID.(EAX=7,ECX=1):EAX[bit 05].

The patch adds a property for setting the subleaf of CPUID leaf 7 in
case that people would like to specify it.

The release spec link as follows,
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf

Signed-off-by: Jing Liu 
---
  target/i386/cpu.c | 39 ++-
  target/i386/cpu.h |  7 +++
  target/i386/kvm.c |  3 ++-
  3 files changed, 47 insertions(+), 2 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 805ce95..517dedb 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -770,6 +770,7 @@ static void x86_cpu_vendor_words2str(char *dst, uint32_t 
vendor1,
/* CPUID_7_0_ECX_OSPKE is dynamic */ \
CPUID_7_0_ECX_LA57)
  #define TCG_7_0_EDX_FEATURES 0
+#define TCG_7_1_EAX_FEATURES 0
  #define TCG_APM_FEATURES 0
  #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
  #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
@@ -1095,6 +1096,25 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] 
= {
  },
  .tcg_features = TCG_7_0_EDX_FEATURES,
  },
+[FEAT_7_1_EAX] = {
+.type = CPUID_FEATURE_WORD,
+.feat_names = {
+NULL, NULL, NULL, NULL,
+NULL, "avx512-bf16", NULL, NULL,
+NULL, NULL, NULL, NULL,
+NULL, NULL, NULL, NULL,
+NULL, NULL, NULL, NULL,
+NULL, NULL, NULL, NULL,
+NULL, NULL, NULL, NULL,
+NULL, NULL, NULL, NULL,
+},
+.cpuid = {
+.eax = 7,
+.needs_ecx = true, .ecx = 1,
+.reg = R_EAX,
+},
+.tcg_features = TCG_7_1_EAX_FEATURES,
+},
  [FEAT_8000_0007_EDX] = {
  .type = CPUID_FEATURE_WORD,
  .feat_names = {
@@ -4293,13 +4313,19 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, 
uint32_t count,
  case 7:
  /* Structured Extended Feature Flags Enumeration Leaf */
  if (count == 0) {
-*eax = 0; /* Maximum ECX value for sub-leaves */
+/* Maximum ECX value for sub-leaves */
+*eax = env->cpuid_level_func7;
  *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
  *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
  if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
  *ecx |= CPUID_7_0_ECX_OSPKE;
  }
  *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
+} else if (count == 1) {
+*eax = env->features[FEAT_7_1_EAX];
+*ebx = 0;
+*ecx = 0;
+*edx = 0;
  } else {
  *eax = 0;
  *ebx = 0;
@@ -4949,6 +4975,11 @@ static void x86_cpu_adjust_feat_level(X86CPU *cpu, 
FeatureWord w)
  x86_cpu_adjust_level(cpu, >cpuid_min_xlevel2, eax);
  break;
  }
+
+if (eax == 7) {
+x86_cpu_adjust_level(cpu, >cpuid_min_level_func7,
+ fi->cpuid.ecx);
+}
  }
  
  /* Calculate XSAVE components based on the configured CPU feature flags */

@@ -5067,6 +5098,7 @@ static void x86_cpu_expand_features(X86CPU *cpu, Error 
**errp)
  x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
  x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
  x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
+x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
  x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
  x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
  x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
@@ -5098,6 +5130,9 @@ static void x86_cpu_expand_features(X86CPU *cpu, Error 
**errp)
  }
  
  /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */

+if (env->cpuid_level_func7 == UINT32_MAX) {
+env->cpuid_level_func7 = env->cpuid_min_level_func7;
+}
  if (env->cpuid_level == UINT32_MAX) {
  env->cpuid_level = env->cpuid_min_level;
  }
@@ -5869,6 +5904,8 @@ static Property x86_cpu_properties[] = {
  DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
  DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 
0),
  DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
+DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7,
+   UINT32_MAX),
  DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
  DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
  DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 05393cf..df9106f 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -479,6 +479,7 @@ typedef enum FeatureWord {

Re: [Qemu-devel] [PATCH v2] x86: Intel AVX512_BF16 feature enabling

2019-07-31 Thread Jing Liu


Hi,

Looking forward to your comments. :)

Thanks!
Jing

On 7/25/2019 2:14 PM, Jing Liu wrote:

Intel CooperLake cpu adds AVX512_BF16 instruction, defining as
CPUID.(EAX=7,ECX=1):EAX[bit 05].

The patch adds a property for setting the subleaf of CPUID leaf 7 in
case that people would like to specify it.

The release spec link as follows,
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf

Signed-off-by: Jing Liu 
---
  target/i386/cpu.c | 39 ++-
  target/i386/cpu.h |  7 +++
  target/i386/kvm.c |  3 ++-
  3 files changed, 47 insertions(+), 2 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 805ce95..517dedb 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -770,6 +770,7 @@ static void x86_cpu_vendor_words2str(char *dst, uint32_t 
vendor1,
/* CPUID_7_0_ECX_OSPKE is dynamic */ \
CPUID_7_0_ECX_LA57)
  #define TCG_7_0_EDX_FEATURES 0
+#define TCG_7_1_EAX_FEATURES 0
  #define TCG_APM_FEATURES 0
  #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
  #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
@@ -1095,6 +1096,25 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] 
= {
  },
  .tcg_features = TCG_7_0_EDX_FEATURES,
  },
+[FEAT_7_1_EAX] = {
+.type = CPUID_FEATURE_WORD,
+.feat_names = {
+NULL, NULL, NULL, NULL,
+NULL, "avx512-bf16", NULL, NULL,
+NULL, NULL, NULL, NULL,
+NULL, NULL, NULL, NULL,
+NULL, NULL, NULL, NULL,
+NULL, NULL, NULL, NULL,
+NULL, NULL, NULL, NULL,
+NULL, NULL, NULL, NULL,
+},
+.cpuid = {
+.eax = 7,
+.needs_ecx = true, .ecx = 1,
+.reg = R_EAX,
+},
+.tcg_features = TCG_7_1_EAX_FEATURES,
+},
  [FEAT_8000_0007_EDX] = {
  .type = CPUID_FEATURE_WORD,
  .feat_names = {
@@ -4293,13 +4313,19 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, 
uint32_t count,
  case 7:
  /* Structured Extended Feature Flags Enumeration Leaf */
  if (count == 0) {
-*eax = 0; /* Maximum ECX value for sub-leaves */
+/* Maximum ECX value for sub-leaves */
+*eax = env->cpuid_level_func7;
  *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
  *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
  if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
  *ecx |= CPUID_7_0_ECX_OSPKE;
  }
  *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
+} else if (count == 1) {
+*eax = env->features[FEAT_7_1_EAX];
+*ebx = 0;
+*ecx = 0;
+*edx = 0;
  } else {
  *eax = 0;
  *ebx = 0;
@@ -4949,6 +4975,11 @@ static void x86_cpu_adjust_feat_level(X86CPU *cpu, 
FeatureWord w)
  x86_cpu_adjust_level(cpu, >cpuid_min_xlevel2, eax);
  break;
  }
+
+if (eax == 7) {
+x86_cpu_adjust_level(cpu, >cpuid_min_level_func7,
+ fi->cpuid.ecx);
+}
  }
  
  /* Calculate XSAVE components based on the configured CPU feature flags */

@@ -5067,6 +5098,7 @@ static void x86_cpu_expand_features(X86CPU *cpu, Error 
**errp)
  x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
  x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
  x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
+x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
  x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
  x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
  x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
@@ -5098,6 +5130,9 @@ static void x86_cpu_expand_features(X86CPU *cpu, Error 
**errp)
  }
  
  /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */

+if (env->cpuid_level_func7 == UINT32_MAX) {
+env->cpuid_level_func7 = env->cpuid_min_level_func7;
+}
  if (env->cpuid_level == UINT32_MAX) {
  env->cpuid_level = env->cpuid_min_level;
  }
@@ -5869,6 +5904,8 @@ static Property x86_cpu_properties[] = {
  DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
  DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 
0),
  DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
+DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7,
+   UINT32_MAX),
  DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
  DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
  DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 05393cf..df9106f 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -479,6

[Qemu-devel] [PATCH v2] x86: Intel AVX512_BF16 feature enabling

2019-07-25 Thread Jing Liu

Intel CooperLake cpu adds AVX512_BF16 instruction, defining as
CPUID.(EAX=7,ECX=1):EAX[bit 05].

The patch adds a property for setting the subleaf of CPUID leaf 7 in
case that people would like to specify it.

The release spec link as follows,
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf

Signed-off-by: Jing Liu 
---
 target/i386/cpu.c | 39 ++-
 target/i386/cpu.h |  7 +++
 target/i386/kvm.c |  3 ++-
 3 files changed, 47 insertions(+), 2 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 805ce95..517dedb 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -770,6 +770,7 @@ static void x86_cpu_vendor_words2str(char *dst, uint32_t 
vendor1,
   /* CPUID_7_0_ECX_OSPKE is dynamic */ \
   CPUID_7_0_ECX_LA57)
 #define TCG_7_0_EDX_FEATURES 0
+#define TCG_7_1_EAX_FEATURES 0
 #define TCG_APM_FEATURES 0
 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
@@ -1095,6 +1096,25 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] 
= {
 },
 .tcg_features = TCG_7_0_EDX_FEATURES,
 },
+[FEAT_7_1_EAX] = {
+.type = CPUID_FEATURE_WORD,
+.feat_names = {
+NULL, NULL, NULL, NULL,
+NULL, "avx512-bf16", NULL, NULL,
+NULL, NULL, NULL, NULL,
+NULL, NULL, NULL, NULL,
+NULL, NULL, NULL, NULL,
+NULL, NULL, NULL, NULL,
+NULL, NULL, NULL, NULL,
+NULL, NULL, NULL, NULL,
+},
+.cpuid = {
+.eax = 7,
+.needs_ecx = true, .ecx = 1,
+.reg = R_EAX,
+},
+.tcg_features = TCG_7_1_EAX_FEATURES,
+},
 [FEAT_8000_0007_EDX] = {
 .type = CPUID_FEATURE_WORD,
 .feat_names = {
@@ -4293,13 +4313,19 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, 
uint32_t count,
 case 7:
 /* Structured Extended Feature Flags Enumeration Leaf */
 if (count == 0) {
-*eax = 0; /* Maximum ECX value for sub-leaves */
+/* Maximum ECX value for sub-leaves */
+*eax = env->cpuid_level_func7;
 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
 *ecx |= CPUID_7_0_ECX_OSPKE;
 }
 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
+} else if (count == 1) {
+*eax = env->features[FEAT_7_1_EAX];
+*ebx = 0;
+*ecx = 0;
+*edx = 0;
 } else {
 *eax = 0;
 *ebx = 0;
@@ -4949,6 +4975,11 @@ static void x86_cpu_adjust_feat_level(X86CPU *cpu, 
FeatureWord w)
 x86_cpu_adjust_level(cpu, >cpuid_min_xlevel2, eax);
 break;
 }
+
+if (eax == 7) {
+x86_cpu_adjust_level(cpu, >cpuid_min_level_func7,
+ fi->cpuid.ecx);
+}
 }
 
 /* Calculate XSAVE components based on the configured CPU feature flags */
@@ -5067,6 +5098,7 @@ static void x86_cpu_expand_features(X86CPU *cpu, Error 
**errp)
 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
+x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
@@ -5098,6 +5130,9 @@ static void x86_cpu_expand_features(X86CPU *cpu, Error 
**errp)
 }
 
 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
+if (env->cpuid_level_func7 == UINT32_MAX) {
+env->cpuid_level_func7 = env->cpuid_min_level_func7;
+}
 if (env->cpuid_level == UINT32_MAX) {
 env->cpuid_level = env->cpuid_min_level;
 }
@@ -5869,6 +5904,8 @@ static Property x86_cpu_properties[] = {
 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
+DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7,
+   UINT32_MAX),
 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 05393cf..df9106f 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -479,6 +479,7 @@ typedef enum FeatureWord {
 FEAT_7_0_EBX,   /* CPUID[EAX=7,ECX=0].EBX */
 FEAT_7_0_ECX,   /* CPUID[EAX=7,ECX=0].ECX */

Re: [Qemu-devel] [PATCH v2] x86: Intel AVX512_BF16 feature enabling

Re: [Qemu-devel] [PATCH v2] x86: Intel AVX512_BF16 feature enabling

Re: [Qemu-devel] [PATCH v2] x86: Intel AVX512_BF16 feature enabling

[Qemu-devel] [PATCH v2] x86: Intel AVX512_BF16 feature enabling

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