Re: [Qemu-devel] [PATCH v2 01/17] Openrisc: add target stubs

2012-05-29 Thread Jia Liu 
Hi Andreas,

On Sun, May 27, 2012 at 8:44 PM, Andreas Färber afaer...@suse.de wrote:
 Am 27.05.2012 07:32, schrieb Jia Liu:
 add openrisc target stubs.

 Signed-off-by: Jia Liu pro...@gmail.com

 Minor nitpick: I'd recommend to stick to the typographic conventions
 outlined here:
 https://live.gnome.org/Git/CommitMessages

 In particular please start the sentence with a capital A. GNOME
 recommend a lowercase topic (we usually use the file/directory mainly
 affected) and uppercase beginning of the actual description, e.g.

 target-or32: Add target stubs

 Add OpenRISC target stubs.


Thanks, I'll fix all of them.

 Signed-off-by: ...

 Writing it that way is not mandatory but when you're reposting and
 fixing the English grammar you can just as well make it perfect. ;)


I'm trying, all the time...

 As Stefan pointed out, www.opencores.org writes it as OpenRISC, not
 Openrisc. I saw no prominent notice whether OpenRISC may be a trademark
 but better to respect their naming, seeing all the misspellings of QEMU.


Thanks, I'll fix all of them.

 [...]
 diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
 new file mode 100644
 index 000..ef3ffb1
 --- /dev/null
 +++ b/target-openrisc/cpu.c
 @@ -0,0 +1,24 @@
 +/*
 + *  QEMU Openrisc CPU
 + *
 + *  Copyright (c) 2012 Jia Liu pro...@gmail.com
 + *
 + * This library is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU Lesser General Public
 + * License as published by the Free Software Foundation; either
 + * version 2 of the License, or (at your option) any later version.
 + *
 + * This library is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 + * Lesser General Public License for more details.
 + *
 + * You should have received a copy of the GNU Lesser General Public
 + * License along with this library; if not, see 
 http://www.gnu.org/licenses/.
 + */
 +
 +#include cpu.h
 +#include qemu-common.h
 +#if !defined(CONFIG_USER_ONLY)
 +#include hw/loader.h
 +#endif

 Missing TypeInfo, missing class_init, missing initfn (where you might
 want to move the openrisc_translate_init() call btw, following Igor's
 example), missing reset function. This cannot all be deferred to a later
 patch.


I'm trying fix this, is target-i386 a good example of QOM? If so, I'll
rewrite the code fellow target-i386.

 diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
 new file mode 100644
 index 000..80018df
 --- /dev/null
 +++ b/target-openrisc/cpu.h
 @@ -0,0 +1,184 @@
 +/*
 + *  Openrisc virtual CPU header.
 + *
 + *  Copyright (c) 2011-2012 Jia Liu pro...@gmail.com
 + *
 + * This library is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU Lesser General Public
 + * License as published by the Free Software Foundation; either
 + * version 2 of the License, or (at your option) any later version.
 + *
 + * This library is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 + * Lesser General Public License for more details.
 + *
 + * You should have received a copy of the GNU Lesser General Public
 + * License along with this library; if not, see 
 http://www.gnu.org/licenses/.
 + */
 +
 +#ifndef CPU_OPENRISC_H
 +#define CPU_OPENRISC_H
 +
 +#define TARGET_HAS_ICE 1
 +
 +#define ELF_MACHINE EM_OPENRISC
 +
 +#define CPUArchState struct CPUOpenriscState
 +
 +#define TARGET_LONG_BITS 32
 +
 +#include config.h
 +#include qemu-common.h
 +#include cpu-defs.h
 +#include softfloat.h
 +#include qemu/cpu.h
 +
 +struct CPUOpenriscState;
 +
 +#define NB_MMU_MODES 3
 +#define MMU_NOMMU_IDX   0
 +#define MMU_SUPERVISOR_IDX  1
 +#define MMU_USER_IDX    2

 Maybe make these three an enum?


Thanks, I'll make a enum for them.

 +
 +#define TARGET_PAGE_BITS 13
 +
 +#define TARGET_PHYS_ADDR_SPACE_BITS 32
 +#define TARGET_VIRT_ADDR_SPACE_BITS 32
 +
 +/* Verison Register */
 +#define SPR_VR       0x1201
 +#define SPR_CPUCFGR  0x1201
 +
 +/* Registers */
 +enum {
 +    R0 = 0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10,
 +    R11, R12, R13, R14, R15, R16, R17, R18, R19, R20,
 +    R21, R22, R23, R24, R25, R26, R27, R28, R29, R30,
 +    R31
 +};
 +
 +/* Register aliases */
 +enum {
 +    R_ZERO = R0,
 +    R_SP = R1,
 +    R_FP = R2,
 +    R_LR = R9,
 +    R_RV = R11,
 +    R_RVH = R12
 +};
 +
 +typedef struct CPUOpenriscState CPUOpenriscState;
 +struct CPUOpenriscState {
 +    target_ulong gpr[32];   /* General registers */
 +
 +    CPU_COMMON
 +
 +    target_ulong pc;        /* Program counter */
 +    target_ulong npc;       /* Next PC */
 +    target_ulong ppc;       /* Prev PC */
 +    target_ulong jmp_pc;    /* Jump PC */
 +    uint32_t flags;
 +    /* Branch. */
 +    uint32_t btaken;        /* the SR_F bit */
 +};

 Why are

Re: [Qemu-devel] [PATCH v2 01/17] Openrisc: add target stubs

2012-05-27 Thread Andreas Färber 
Am 27.05.2012 07:32, schrieb Jia Liu:
 add openrisc target stubs.
 
 Signed-off-by: Jia Liu pro...@gmail.com

Minor nitpick: I'd recommend to stick to the typographic conventions
outlined here:
https://live.gnome.org/Git/CommitMessages

In particular please start the sentence with a capital A. GNOME
recommend a lowercase topic (we usually use the file/directory mainly
affected) and uppercase beginning of the actual description, e.g.

target-or32: Add target stubs

Add OpenRISC target stubs.

Signed-off-by: ...

Writing it that way is not mandatory but when you're reposting and
fixing the English grammar you can just as well make it perfect. ;)

As Stefan pointed out, www.opencores.org writes it as OpenRISC, not
Openrisc. I saw no prominent notice whether OpenRISC may be a trademark
but better to respect their naming, seeing all the misspellings of QEMU.

[...]
 diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
 new file mode 100644
 index 000..ef3ffb1
 --- /dev/null
 +++ b/target-openrisc/cpu.c
 @@ -0,0 +1,24 @@
 +/*
 + *  QEMU Openrisc CPU
 + *
 + *  Copyright (c) 2012 Jia Liu pro...@gmail.com
 + *
 + * This library is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU Lesser General Public
 + * License as published by the Free Software Foundation; either
 + * version 2 of the License, or (at your option) any later version.
 + *
 + * This library is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 + * Lesser General Public License for more details.
 + *
 + * You should have received a copy of the GNU Lesser General Public
 + * License along with this library; if not, see 
 http://www.gnu.org/licenses/.
 + */
 +
 +#include cpu.h
 +#include qemu-common.h
 +#if !defined(CONFIG_USER_ONLY)
 +#include hw/loader.h
 +#endif

Missing TypeInfo, missing class_init, missing initfn (where you might
want to move the openrisc_translate_init() call btw, following Igor's
example), missing reset function. This cannot all be deferred to a later
patch.

 diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
 new file mode 100644
 index 000..80018df
 --- /dev/null
 +++ b/target-openrisc/cpu.h
 @@ -0,0 +1,184 @@
 +/*
 + *  Openrisc virtual CPU header.
 + *
 + *  Copyright (c) 2011-2012 Jia Liu pro...@gmail.com
 + *
 + * This library is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU Lesser General Public
 + * License as published by the Free Software Foundation; either
 + * version 2 of the License, or (at your option) any later version.
 + *
 + * This library is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 + * Lesser General Public License for more details.
 + *
 + * You should have received a copy of the GNU Lesser General Public
 + * License along with this library; if not, see 
 http://www.gnu.org/licenses/.
 + */
 +
 +#ifndef CPU_OPENRISC_H
 +#define CPU_OPENRISC_H
 +
 +#define TARGET_HAS_ICE 1
 +
 +#define ELF_MACHINE EM_OPENRISC
 +
 +#define CPUArchState struct CPUOpenriscState
 +
 +#define TARGET_LONG_BITS 32
 +
 +#include config.h
 +#include qemu-common.h
 +#include cpu-defs.h
 +#include softfloat.h
 +#include qemu/cpu.h
 +
 +struct CPUOpenriscState;
 +
 +#define NB_MMU_MODES 3
 +#define MMU_NOMMU_IDX   0
 +#define MMU_SUPERVISOR_IDX  1
 +#define MMU_USER_IDX2

Maybe make these three an enum?

 +
 +#define TARGET_PAGE_BITS 13
 +
 +#define TARGET_PHYS_ADDR_SPACE_BITS 32
 +#define TARGET_VIRT_ADDR_SPACE_BITS 32
 +
 +/* Verison Register */
 +#define SPR_VR   0x1201
 +#define SPR_CPUCFGR  0x1201
 +
 +/* Registers */
 +enum {
 +R0 = 0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10,
 +R11, R12, R13, R14, R15, R16, R17, R18, R19, R20,
 +R21, R22, R23, R24, R25, R26, R27, R28, R29, R30,
 +R31
 +};
 +
 +/* Register aliases */
 +enum {
 +R_ZERO = R0,
 +R_SP = R1,
 +R_FP = R2,
 +R_LR = R9,
 +R_RV = R11,
 +R_RVH = R12
 +};
 +
 +typedef struct CPUOpenriscState CPUOpenriscState;
 +struct CPUOpenriscState {
 +target_ulong gpr[32];   /* General registers */
 +
 +CPU_COMMON
 +
 +target_ulong pc;/* Program counter */
 +target_ulong npc;   /* Next PC */
 +target_ulong ppc;   /* Prev PC */
 +target_ulong jmp_pc;/* Jump PC */
 +uint32_t flags;
 +/* Branch. */
 +uint32_t btaken;/* the SR_F bit */
 +};

Why are pc, etc. placed after CPU_COMMON? Are they not supposed to be reset?

 +
 +#define TYPE_OPENRISC_CPU or32-cpu
 +
 +#define OPENRISC_CPU_CLASS(klass) \
 +OBJECT_CLASS_CHECK(OpenriscCPUClass, (klass), TYPE_OPENRISC_CPU)
 +#define OPENRISC_CPU(obj) \
 +OBJECT_CHECK(OpenriscCPU, (obj), TYPE_OPENRISC_CPU)
 +#define OPENRISC_CPU_GET_CLASS(obj) \

[Qemu-devel] [PATCH v2 01/17] Openrisc: add target stubs

2012-05-26 Thread Jia Liu 
add openrisc target stubs.

Signed-off-by: Jia Liu pro...@gmail.com
---
 Makefile.target  |3 +
 arch_init.c  |2 +
 arch_init.h  |1 +
 configure|   10 ++-
 cpu-exec.c   |2 +
 default-configs/or32-softmmu.mak |6 ++
 elf.h|2 +
 poison.h |1 +
 target-openrisc/cpu.c|   24 +
 target-openrisc/cpu.h|  184 ++
 target-openrisc/helper.c |   60 +
 target-openrisc/intrpt.c |   30 +++
 target-openrisc/machine.c|   31 +++
 target-openrisc/mmu.c|   35 
 target-openrisc/mmu_helper.c |   43 +
 target-openrisc/translate.c  |   61 +
 16 files changed, 493 insertions(+), 2 deletions(-)
 create mode 100644 default-configs/or32-softmmu.mak
 create mode 100644 target-openrisc/cpu.c
 create mode 100644 target-openrisc/cpu.h
 create mode 100644 target-openrisc/helper.c
 create mode 100644 target-openrisc/intrpt.c
 create mode 100644 target-openrisc/machine.c
 create mode 100644 target-openrisc/mmu.c
 create mode 100644 target-openrisc/mmu_helper.c
 create mode 100644 target-openrisc/translate.c

diff --git a/Makefile.target b/Makefile.target
index 1582904..0415db8 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -83,9 +83,11 @@ libobj-$(CONFIG_TCG_INTERPRETER) += tci.o
 libobj-y += fpu/softfloat.o
 ifneq ($(TARGET_BASE_ARCH), sparc)
 ifneq ($(TARGET_BASE_ARCH), alpha)
+ifneq ($(TARGET_BASE_ARCH), openrisc)
 libobj-y += op_helper.o
 endif
 endif
+endif
 libobj-y += helper.o
 ifneq ($(TARGET_BASE_ARCH), ppc)
 libobj-y += cpu.o
@@ -99,6 +101,7 @@ endif
 libobj-$(TARGET_SPARC) += int32_helper.o
 libobj-$(TARGET_SPARC64) += int64_helper.o
 libobj-$(TARGET_ALPHA) += int_helper.o fpu_helper.o sys_helper.o mem_helper.o
+libobj-$(TARGET_OPENRISC) += intrpt.o mmu.o mmu_helper.o
 
 libobj-y += disas.o
 libobj-$(CONFIG_TCI_DIS) += tci-dis.o
diff --git a/arch_init.c b/arch_init.c
index 988adca..55b608d 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -71,6 +71,8 @@ int graphic_depth = 15;
 #define QEMU_ARCH QEMU_ARCH_MICROBLAZE
 #elif defined(TARGET_MIPS)
 #define QEMU_ARCH QEMU_ARCH_MIPS
+#elif defined(TARGET_OPENRISC)
+#define QEMU_ARCH QEMU_ARCH_OPENRISC
 #elif defined(TARGET_PPC)
 #define QEMU_ARCH QEMU_ARCH_PPC
 #elif defined(TARGET_S390X)
diff --git a/arch_init.h b/arch_init.h
index c7cb94a..3dfea3b 100644
--- a/arch_init.h
+++ b/arch_init.h
@@ -16,6 +16,7 @@ enum {
 QEMU_ARCH_SH4 = 1024,
 QEMU_ARCH_SPARC = 2048,
 QEMU_ARCH_XTENSA = 4096,
+QEMU_ARCH_OPENRISC = 8192,
 };
 
 extern const uint32_t arch_type;
diff --git a/configure b/configure
index b55a792..bcfe00f 100755
--- a/configure
+++ b/configure
@@ -924,6 +924,7 @@ mips-softmmu \
 mipsel-softmmu \
 mips64-softmmu \
 mips64el-softmmu \
+or32-softmmu \
 ppc-softmmu \
 ppcemb-softmmu \
 ppc64-softmmu \
@@ -3460,7 +3461,7 @@ target_arch2=`echo $target | cut -d '-' -f 1`
 target_bigendian=no
 
 case $target_arch2 in
-  
armeb|lm32|m68k|microblaze|mips|mipsn32|mips64|ppc|ppcemb|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)
+  
armeb|lm32|m68k|microblaze|mips|mipsn32|mips64|or32|ppc|ppcemb|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)
   target_bigendian=yes
   ;;
 esac
@@ -3588,6 +3589,11 @@ case $target_arch2 in
 target_phys_bits=64
 target_long_alignment=8
   ;;
+  or32)
+TARGET_ARCH=openrisc
+TARGET_BASE_ARCH=openrisc
+target_phys_bits=32
+  ;;
   ppc)
 gdb_xml_files=power-core.xml power-fpu.xml power-altivec.xml 
power-spe.xml
 target_phys_bits=64
@@ -3659,7 +3665,7 @@ case $target_arch2 in
 esac
 
 case $target_arch2 in
-  alpha | sparc*)
+  alpha | or32 | sparc*)
 echo CONFIG_TCG_PASS_AREG0=y  $config_target_mak
   ;;
 esac
diff --git a/cpu-exec.c b/cpu-exec.c
index 0344cd5..ba10db1 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -222,6 +222,7 @@ int cpu_exec(CPUArchState *env)
 #elif defined(TARGET_LM32)
 #elif defined(TARGET_MICROBLAZE)
 #elif defined(TARGET_MIPS)
+#elif defined(TARGET_OPENRISC)
 #elif defined(TARGET_SH4)
 #elif defined(TARGET_CRIS)
 #elif defined(TARGET_S390X)
@@ -620,6 +621,7 @@ int cpu_exec(CPUArchState *env)
   | env-cc_dest | (env-cc_x  4);
 #elif defined(TARGET_MICROBLAZE)
 #elif defined(TARGET_MIPS)
+#elif defined(TARGET_OPENRISC)
 #elif defined(TARGET_SH4)
 #elif defined(TARGET_ALPHA)
 #elif defined(TARGET_CRIS)
diff --git a/default-configs/or32-softmmu.mak b/default-configs/or32-softmmu.mak
new file mode 100644
index 000..7590eed
--- /dev/null
+++ b/default-configs/or32-softmmu.mak
@@ -0,0 +1,6 @@
+# Default configuration for or32-softmmu
+
+include pci.mak
+CONFIG_SERIAL=y
+CONFIG_NE2000_ISA=y
+CONFIG_I8259=y
diff --git a/elf.h b/elf.h
index e1422b8..e65f4b9 100644
--- a/elf.h
+++ b/elf.h
@@ -106,6 +106,8 @@ typedef int64_t