Move the MVFR* VFP feature register values to ARMCPU,
so they are set up by the implementation-specific instance
init functions rather than in cpu_reset_model_id().
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/cpu-qom.h |2 ++
target-arm/cpu.c | 14 ++
target-arm/helper.c | 14 ++
3 files changed, 18 insertions(+), 12 deletions(-)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 7cc4cd5..c51eb84 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -71,6 +71,8 @@ typedef struct ARMCPU {
*/
uint32_t midr;
uint32_t reset_fpsid;
+uint32_t mvfr0;
+uint32_t mvfr1;
} ARMCPU;
static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 9d23a1a..8e2d8c2 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -128,6 +128,8 @@ static void arm1136_r2_initfn(Object *obj)
set_feature(cpu-env, ARM_FEATURE_VFP);
cpu-midr = ARM_CPUID_ARM1136_R2;
cpu-reset_fpsid = 0x410120b4;
+cpu-mvfr0 = 0x;
+cpu-mvfr1 = 0x;
}
static void arm1136_initfn(Object *obj)
@@ -138,6 +140,8 @@ static void arm1136_initfn(Object *obj)
set_feature(cpu-env, ARM_FEATURE_VFP);
cpu-midr = ARM_CPUID_ARM1136;
cpu-reset_fpsid = 0x410120b4;
+cpu-mvfr0 = 0x;
+cpu-mvfr1 = 0x;
}
static void arm1176_initfn(Object *obj)
@@ -148,6 +152,8 @@ static void arm1176_initfn(Object *obj)
set_feature(cpu-env, ARM_FEATURE_VAPA);
cpu-midr = ARM_CPUID_ARM1176;
cpu-reset_fpsid = 0x410120b5;
+cpu-mvfr0 = 0x;
+cpu-mvfr1 = 0x;
}
static void arm11mpcore_initfn(Object *obj)
@@ -158,6 +164,8 @@ static void arm11mpcore_initfn(Object *obj)
set_feature(cpu-env, ARM_FEATURE_VAPA);
cpu-midr = ARM_CPUID_ARM11MPCORE;
cpu-reset_fpsid = 0x410120b4;
+cpu-mvfr0 = 0x;
+cpu-mvfr1 = 0x;
}
static void cortex_m3_initfn(Object *obj)
@@ -177,6 +185,8 @@ static void cortex_a8_initfn(Object *obj)
set_feature(cpu-env, ARM_FEATURE_THUMB2EE);
cpu-midr = ARM_CPUID_CORTEXA8;
cpu-reset_fpsid = 0x410330c0;
+cpu-mvfr0 = 0x0222;
+cpu-mvfr1 = 0x00011100;
}
static void cortex_a9_initfn(Object *obj)
@@ -194,6 +204,8 @@ static void cortex_a9_initfn(Object *obj)
set_feature(cpu-env, ARM_FEATURE_V7MP);
cpu-midr = ARM_CPUID_CORTEXA9;
cpu-reset_fpsid = 0x41033090;
+cpu-mvfr0 = 0x0222;
+cpu-mvfr1 = 0x0111;
}
static void cortex_a15_initfn(Object *obj)
@@ -209,6 +221,8 @@ static void cortex_a15_initfn(Object *obj)
set_feature(cpu-env, ARM_FEATURE_GENERIC_TIMER);
cpu-midr = ARM_CPUID_CORTEXA15;
cpu-reset_fpsid = 0x410430f0;
+cpu-mvfr0 = 0x10110222;
+cpu-mvfr1 = 0x;
}
static void ti925t_initfn(Object *obj)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 3247dd3..777bb03 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -72,31 +72,23 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t
id)
* for 1136_r2 (in particular r0p2 does not actually implement most
* of the ID registers).
*/
-env-vfp.xregs[ARM_VFP_MVFR0] = 0x;
-env-vfp.xregs[ARM_VFP_MVFR1] = 0x;
memcpy(env-cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(env-cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
env-cp15.c0_cachetype = 0x1dd20d2;
env-cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM1176:
-env-vfp.xregs[ARM_VFP_MVFR0] = 0x;
-env-vfp.xregs[ARM_VFP_MVFR1] = 0x;
memcpy(env-cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(env-cp15.c0_c2, arm1176_cp15_c0_c2, 8 * sizeof(uint32_t));
env-cp15.c0_cachetype = 0x1dd20d2;
env-cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM11MPCORE:
-env-vfp.xregs[ARM_VFP_MVFR0] = 0x;
-env-vfp.xregs[ARM_VFP_MVFR1] = 0x;
memcpy(env-cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(env-cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
env-cp15.c0_cachetype = 0x1dd20d2;
break;
case ARM_CPUID_CORTEXA8:
-env-vfp.xregs[ARM_VFP_MVFR0] = 0x0222;
-env-vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
memcpy(env-cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(env-cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
env-cp15.c0_cachetype = 0x82048004;
@@ -107,8 +99,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env-cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXA9:
-env-vfp.xregs[ARM_VFP_MVFR0] = 0x0222;
-env-vfp.xregs[ARM_VFP_MVFR1] = 0x0111;
memcpy(env-cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
