[Qemu-devel] [PATCH v2 16/16] xlnx-zynqmp: Connect the ZynqMP IOU SLCR

[Alistair Francis]

Connect the I/O Unit System Level Control Registers device
to the ZynqMP model. Unfortunatly the GPIO links can not be
connected yet as the SD device is not yet attached to the
ZynqMP machine.

Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com>
---
V2:
 - Fix up device connection

 hw/arm/xlnx-zynqmp.c         | 13 +++++++++++++
 include/hw/arm/xlnx-zynqmp.h |  2 ++
 2 files changed, 15 insertions(+)

diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 57e926d..a1391ba 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -33,6 +33,8 @@
 #define SATA_ADDR           0xFD0C0000
 #define SATA_NUM_PORTS      2
 
+#define IOU_SLCR_ADDR       0xFF180000
+
 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
     0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
 };
@@ -118,6 +120,10 @@ static void xlnx_zynqmp_init(Object *obj)
         qdev_set_parent_bus(DEVICE(&s->sdhci[i]),
                             sysbus_get_default());
     }
+
+    object_initialize(&s->iou_slcr, sizeof(s->iou_slcr),
+                      TYPE_XLNX_ZYNQMP_IOU_SLCR);
+    qdev_set_parent_bus(DEVICE(&s->iou_slcr), sysbus_get_default());
 }
 
 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
@@ -324,6 +330,13 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error 
**errp)
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
                            gic_spi[sdhci_intr[i]]);
     }
+
+    object_property_set_bool(OBJECT(&s->iou_slcr), true, "realized", &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->iou_slcr), 0, IOU_SLCR_ADDR);
 }
 
 static Property xlnx_zynqmp_props[] = {
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index 1eba937..e3a1f0b 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -22,6 +22,7 @@
 #include "hw/intc/arm_gic.h"
 #include "hw/net/cadence_gem.h"
 #include "hw/char/cadence_uart.h"
+#include "hw/misc/xlnx-zynqmp-iou-slcr.h"
 #include "hw/ide/pci.h"
 #include "hw/ide/ahci.h"
 #include "hw/sd/sdhci.h"
@@ -78,6 +79,7 @@ typedef struct XlnxZynqMPState {
     CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
     SysbusAHCIState sata;
     SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI];
+    XlnxZynqMPIOUSLCR iou_slcr;
 
     char *boot_cpu;
     ARMCPU *boot_cpu_ptr;
-- 
2.5.0