Pull the addresses used for mapping motherboard peripherals into
memory out into a table. This will allow us to simply provide a
second table to implement the Cortex-A Series memory map used by
the A15 variant of Versatile Express, as well as the current
Legacy map used by A9.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/vexpress.c | 137 +++--
1 files changed, 103 insertions(+), 34 deletions(-)
diff --git a/hw/vexpress.c b/hw/vexpress.c
index 64fab45..8c4d3b3 100644
--- a/hw/vexpress.c
+++ b/hw/vexpress.c
@@ -31,13 +31,80 @@
#include exec-memory.h
#define SMP_BOOT_ADDR 0xe000
-#define SMP_BOOTREG_ADDR 0x1030
#define VEXPRESS_BOARD_ID 0x8e0
static struct arm_boot_info vexpress_binfo = {
.smp_loader_start = SMP_BOOT_ADDR,
-.smp_bootreg_addr = SMP_BOOTREG_ADDR,
+};
+
+/* Address maps for peripherals:
+ * the Versatile Express motherboard has two possible maps,
+ * the legacy one (used for A9) and the Cortex-A Series
+ * map (used for newer cores).
+ * Individual daughterboards can also have different maps for
+ * their peripherals.
+ */
+
+enum {
+VE_SYSREGS,
+VE_SP810,
+VE_SERIALPCI,
+VE_PL041,
+VE_MMCI,
+VE_KMI0,
+VE_KMI1,
+VE_UART0,
+VE_UART1,
+VE_UART2,
+VE_UART3,
+VE_WDT,
+VE_TIMER01,
+VE_TIMER23,
+VE_SERIALDVI,
+VE_RTC,
+VE_COMPACTFLASH,
+VE_CLCD,
+VE_NORFLASH0,
+VE_NORFLASH0ALIAS,
+VE_NORFLASH1,
+VE_SRAM,
+VE_VIDEORAM,
+VE_ETHERNET,
+VE_USB,
+VE_DAPROM,
+};
+
+static target_phys_addr_t motherboard_legacy_map[] = {
+/* CS7: 0x1000 .. 0x1002 */
+[VE_SYSREGS] = 0x1000,
+[VE_SP810] = 0x10001000,
+[VE_SERIALPCI] = 0x10002000,
+[VE_PL041] = 0x10004000,
+[VE_MMCI] = 0x10005000,
+[VE_KMI0] = 0x10006000,
+[VE_KMI1] = 0x10007000,
+[VE_UART0] = 0x10009000,
+[VE_UART1] = 0x1000a000,
+[VE_UART2] = 0x1000b000,
+[VE_UART3] = 0x1000c000,
+[VE_WDT] = 0x1000f000,
+[VE_TIMER01] = 0x10011000,
+[VE_TIMER23] = 0x10012000,
+[VE_SERIALDVI] = 0x10016000,
+[VE_RTC] = 0x10017000,
+[VE_COMPACTFLASH] = 0x1001a000,
+[VE_CLCD] = 0x1001f000,
+/* CS0: 0x4000 .. 0x4400 */
+[VE_NORFLASH0] = 0x4000,
+/* CS1: 0x4400 .. 0x4800 */
+[VE_NORFLASH1] = 0x4400,
+/* CS2: 0x4800 .. 0x4a00 */
+[VE_SRAM] = 0x4800,
+/* CS3: 0x4c00 .. 0x5000 */
+[VE_VIDEORAM] = 0x4c00,
+[VE_ETHERNET] = 0x4e00,
+[VE_USB] = 0x4f00,
};
static void vexpress_a9_init(ram_addr_t ram_size,
@@ -61,6 +128,7 @@ static void vexpress_a9_init(ram_addr_t ram_size,
uint32_t proc_id;
uint32_t sys_id;
ram_addr_t low_ram_size, vram_size, sram_size;
+target_phys_addr_t *map = motherboard_legacy_map;
if (!cpu_model) {
cpu_model = cortex-a9;
@@ -116,53 +184,53 @@ static void vexpress_a9_init(ram_addr_t ram_size,
pic[n] = qdev_get_gpio_in(dev, n);
}
-/* Motherboard peripherals CS7 : 0x1000 .. 0x1002 */
+/* Motherboard peripherals: the wiring is the same but the
+ * addresses vary between the legacy and A-Series memory maps.
+ */
+
sys_id = 0x1190f500;
proc_id = 0x0c000191;
-/* 0x1000 System registers */
sysctl = qdev_create(NULL, realview_sysctl);
qdev_prop_set_uint32(sysctl, sys_id, sys_id);
qdev_init_nofail(sysctl);
qdev_prop_set_uint32(sysctl, proc_id, proc_id);
-sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x1000);
+sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, map[VE_SYSREGS]);
+
+/* VE_SP810: not modelled */
+/* VE_SERIALPCI: not modelled */
-/* 0x10001000 SP810 system control */
-/* 0x10002000 serial bus PCI */
-/* 0x10004000 PL041 audio */
pl041 = qdev_create(NULL, pl041);
qdev_prop_set_uint32(pl041, nc_fifo_depth, 512);
qdev_init_nofail(pl041);
-sysbus_mmio_map(sysbus_from_qdev(pl041), 0, 0x10004000);
+sysbus_mmio_map(sysbus_from_qdev(pl041), 0, map[VE_PL041]);
sysbus_connect_irq(sysbus_from_qdev(pl041), 0, pic[11]);
-dev = sysbus_create_varargs(pl181, 0x10005000, pic[9], pic[10], NULL);
+dev = sysbus_create_varargs(pl181, map[VE_MMCI], pic[9], pic[10], NULL);
/* Wire up MMC card detect and read-only signals */
qdev_connect_gpio_out(dev, 0,
qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
qdev_connect_gpio_out(dev, 1,
qdev_get_gpio_in(sysctl,
ARM_SYSCTL_GPIO_MMC_CARDIN));
-sysbus_create_simple(pl050_keyboard, 0x10006000, pic[12]);
-sysbus_create_simple(pl050_mouse, 0x10007000, pic[13]);
-
-sysbus_create_simple(pl011, 0x10009000, pic[5]);
-sysbus_create_simple(pl011, 0x1000a000, pic[6]);
-sysbus_create_simple(pl011, 0x1000b000, pic[7]);
-sysbus_create_simple(pl011, 0x1000c000, pic[8]);
+
