Re: [Qemu-devel] [PATCH v3 04/31] target/arm/cpu.h: add additional float_status flags

[Richard Henderson]

On 02/23/2018 07:36 AM, Alex Bennée wrote:
> Half-precision flush to zero behaviour is controlled by a separate
> FZ16 bit in the FPCR. To handle this we pass a pointer to
> fp_status_fp16 when working on half-precision operations. The value of
> the presented FPCR is calculated from an amalgam of the two when read.
> 
> Signed-off-by: Alex Bennée 
> 
> ---
> v3
>   - add FPCR_[FZ/FZ16/DN] defines to cpu.h and use
>   - only propagate flag status to fp_status as they are ored later
>   - ensure dnan and round mode propagated to fp_status_fp16
> ---

Reviewed-by: Richard Henderson 


r~

[Qemu-devel] [PATCH v3 04/31] target/arm/cpu.h: add additional float_status flags

[Alex Bennée]

Half-precision flush to zero behaviour is controlled by a separate
FZ16 bit in the FPCR. To handle this we pass a pointer to
fp_status_fp16 when working on half-precision operations. The value of
the presented FPCR is calculated from an amalgam of the two when read.

Signed-off-by: Alex Bennée 

---
v3
  - add FPCR_[FZ/FZ16/DN] defines to cpu.h and use
  - only propagate flag status to fp_status as they are ored later
  - ensure dnan and round mode propagated to fp_status_fp16
---
 target/arm/cpu.h   | 32 ++--
 target/arm/helper.c| 26 ++-
 target/arm/translate-a64.c | 53 +-
 3 files changed, 75 insertions(+), 36 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c2bce23fa5..ebbb21391c 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -538,19 +538,29 @@ typedef struct CPUARMState {
 /* scratch space when Tn are not sufficient.  */
 uint32_t scratch[8];
 
-/* fp_status is the "normal" fp status. standard_fp_status retains
- * values corresponding to the ARM "Standard FPSCR Value", ie
- * default-NaN, flush-to-zero, round-to-nearest and is used by
- * any operations (generally Neon) which the architecture defines
- * as controlled by the standard FPSCR value rather than the FPSCR.
+/* There are a number of distinct float control structures:
+ *
+ *  fp_status: is the "normal" fp status.
+ *  fp_status_fp16: used for half-precision calculations
+ *  standard_fp_status : the ARM "Standard FPSCR Value"
+ *
+ * Half-precision operations are governed by a separate
+ * flush-to-zero control bit in FPSCR:FZ16. We pass a separate
+ * status structure to control this.
+ *
+ * The "Standard FPSCR", ie default-NaN, flush-to-zero,
+ * round-to-nearest and is used by any operations (generally
+ * Neon) which the architecture defines as controlled by the
+ * standard FPSCR value rather than the FPSCR.
  *
  * To avoid having to transfer exception bits around, we simply
  * say that the FPSCR cumulative exception flags are the logical
- * OR of the flags in the two fp statuses. This relies on the
+ * OR of the flags in the three fp statuses. This relies on the
  * only thing which needs to read the exception flags being
  * an explicit FPSCR read.
  */
 float_status fp_status;
+float_status fp_status_f16;
 float_status standard_fp_status;
 
 /* ZCR_EL[1-3] */
@@ -1190,12 +1200,20 @@ static inline void xpsr_write(CPUARMState *env, 
uint32_t val, uint32_t mask)
 uint32_t vfp_get_fpscr(CPUARMState *env);
 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
 
-/* For A64 the FPSCR is split into two logically distinct registers,
+/* FPCR, Floating Point Control Register
+ * FPSR, Floating Poiht Status Register
+ *
+ * For A64 the FPSCR is split into two logically distinct registers,
  * FPCR and FPSR. However since they still use non-overlapping bits
  * we store the underlying state in fpscr and just mask on read/write.
  */
 #define FPSR_MASK 0xf89f
 #define FPCR_MASK 0x07f79f00
+
+#define FPCR_FZ16   (1 << 19)   /* ARMv8.2+, FP16 flush-to-zero */
+#define FPCR_FZ (1 << 24)   /* Flush-to-zero enable bit */
+#define FPCR_DN (1 << 25)   /* Default NaN enable bit */
+
 static inline uint32_t vfp_get_fpsr(CPUARMState *env)
 {
 return vfp_get_fpscr(env) & FPSR_MASK;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index c5bc69b961..f450eb200f 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11103,6 +11103,7 @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
 | (env->vfp.vec_stride << 20);
 i = get_float_exception_flags(>vfp.fp_status);
 i |= get_float_exception_flags(>vfp.standard_fp_status);
+i |= get_float_exception_flags(>vfp.fp_status_f16);
 fpscr |= vfp_exceptbits_from_host(i);
 return fpscr;
 }
@@ -11160,16 +11161,31 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t 
val)
 break;
 }
 set_float_rounding_mode(i, >vfp.fp_status);
+set_float_rounding_mode(i, >vfp.fp_status_f16);
 }
-if (changed & (1 << 24)) {
-set_flush_to_zero((val & (1 << 24)) != 0, >vfp.fp_status);
-set_flush_inputs_to_zero((val & (1 << 24)) != 0, >vfp.fp_status);
+if (changed & FPCR_FZ16) {
+bool ftz_enabled = val & FPCR_FZ16;
+set_flush_to_zero(ftz_enabled, >vfp.fp_status_f16);
+set_flush_inputs_to_zero(ftz_enabled, >vfp.fp_status_f16);
+}
+if (changed & FPCR_FZ) {
+bool ftz_enabled = val & FPCR_FZ;
+set_flush_to_zero(ftz_enabled, >vfp.fp_status);
+set_flush_inputs_to_zero(ftz_enabled, >vfp.fp_status);
+}
+if (changed & FPCR_DN) {
+bool