Re: [Qemu-devel] [PATCH v4 0/5] Add Icelake CPU model
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1530781798-183214-1-git-send-email-robert...@linux.intel.com
Subject: [Qemu-devel] [PATCH v4 0/5] Add Icelake CPU model
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
fe8d2d5737..8beb8cc64d master -> master
* [new tag]
patchew/1530781798-183214-1-git-send-email-robert...@linux.intel.com ->
patchew/1530781798-183214-1-git-send-email-robert...@linux.intel.com
t [tag update]patchew/20180705031755.3254-1-pet...@redhat.com ->
patchew/20180705031755.3254-1-pet...@redhat.com
t [tag update]
patchew/20180705080017.31123-1-bal...@linux.vnet.ibm.com ->
patchew/20180705080017.31123-1-bal...@linux.vnet.ibm.com
* [new tag] patchew/20180705091402.26244-1-arm...@redhat.com ->
patchew/20180705091402.26244-1-arm...@redhat.com
* [new tag]
patchew/20180705092139.776069-1-vsement...@virtuozzo.com ->
patchew/20180705092139.776069-1-vsement...@virtuozzo.com
Switched to a new branch 'test'
c57219dd66 i386: Add new CPU model Icelake-{Server, Client}
e4b41e6694 i386: Add CPUID bit for WBNOINVD
0d363e4b5a i386: Add CPUID bit for PCONFIG
1f198579c6 i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR
27bdf2a6a2 i386: Add new MSR indices for IA32_PRED_CMD and
IA32_ARCH_CAPABILITIES
=== OUTPUT BEGIN ===
Checking PATCH 1/5: i386: Add new MSR indices for IA32_PRED_CMD and
IA32_ARCH_CAPABILITIES...
Checking PATCH 2/5: i386: Add CPUID bit and feature words for
IA32_ARCH_CAPABILITIES MSR...
Checking PATCH 3/5: i386: Add CPUID bit for PCONFIG...
Checking PATCH 4/5: i386: Add CPUID bit for WBNOINVD...
ERROR: line over 90 characters
#34: FILE: target/i386/cpu.h:698:
+
do not invalidate cache */
total: 1 errors, 0 warnings, 16 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 5/5: i386: Add new CPU model Icelake-{Server, Client}...
=== OUTPUT END ===
Test command exited with code: 1
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-de...@redhat.com
[Qemu-devel] [PATCH v4 0/5] Add Icelake CPU model
This patch set defines the new guest CPU models of Icelake.
The first patch defines new indices for IA32_PRED_CMD MSR (IBPB) and
IA32_ARCH_CAPABILITIES MSR.
Other patches add CPUID bits feature words for new features, like PCONFIG,
WBNOINVD. The final patch defines Icelake-{Server,Client} CPU models.
Changelog:
v4
At present, mark CPUID_7_0_EDX_ARCH_CAPABILITIES unmigratable.
v3
Remove ARCH_CAPABILITIES from Icelake CPU model, at present. Going to
compose a separate patch to do 1) qemu set ARCH_CAPABILITES MSR with some
default
value. 2) expand current CPU feature expression frame work from CPUID features
only to MSR bit included as well.
Fix some patch format error and update some trivial patch descrptions.
v2
Per Paolo's comment, remove unnecessary CPU vmstate check for
write/read only
IA32_PRED_CMD and IA32_ARCH_CAPABILITIES MSRs.
Robert Hoo (5):
i386: Add new MSR indices for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES
i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR
i386: Add CPUID bit for PCONFIG
i386: Add CPUID bit for WBNOINVD
i386: Add new CPU model Icelake-{Server,Client}
target/i386/cpu.c | 122 --
target/i386/cpu.h | 6 +++
2 files changed, 125 insertions(+), 3 deletions(-)
--
1.8.3.1
