Re: [Qemu-devel] [PATCH v4 3/9] softfloat: For Mips only, correct order in pickNaNMulAdd()

2016-04-13 Thread Aleksandar Markovic 
Thanks, you are right, this area is changed in patch #1 too. However, it was 
not intended to be that way. Patch #1 should leave this function as-is, and the 
entire change for this function should be in this patch. I will organize the 
code as intended in the next version of the series. Yours, Aleksandar

From: Leon Alrae
Sent: Wednesday, April 13, 2016 5:47 AM
To: Aleksandar Markovic; qemu-devel@nongnu.org
Cc: pro...@gmail.com; kbast...@mail.uni-paderborn.de; 
mark.cave-ayl...@ilande.co.uk; ag...@suse.de; blauwir...@gmail.com; 
jcmvb...@gmail.com; Aleksandar Markovic; qemu-...@nongnu.org; 
qemu-...@nongnu.org; Petar Jovanovic; pbonz...@redhat.com; Miodrag Dinic; 
edgar.igles...@gmail.com; g...@mprc.pku.edu.cn; afaer...@suse.de; 
aurel...@aurel32.net; r...@twiddle.net; Maciej Rozycki
Subject: Re: [PATCH v4 3/9] softfloat: For Mips only, correct order in 
pickNaNMulAdd()

On 12/04/16 13:58, Aleksandar Markovic wrote:
> From: Aleksandar Markovic 
>
> Only for Mips platform, and only for cases when snan_bit_is_one is 0,
> correct the order of argument comparisons in pickNaNMulAdd().
>
> For more info, see [2], page 53, section "3.5.3 NaN Propagation".
>
> [1] "MIPS® Architecture For Programmers Volume II-A:
> The MIPS64® Instruction Set Reference Manual",
> Imagination Technologies LTD, Revision 6.04, November 13, 2015
>
> [2] "MIPS Architecture for Programmers Volume IV-j:
> The MIPS32® SIMD Architecture Module",
> Imagination Technologies LTD, Revision 1.12, February 3, 2016
>
> Signed-off-by: Aleksandar Markovic 
> ---
>  fpu/softfloat-specialize.h |   41 +
>  1 file changed, 29 insertions(+), 12 deletions(-)
>
> diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
> index 169246e..807ecc0 100644
> --- a/fpu/softfloat-specialize.h
> +++ b/fpu/softfloat-specialize.h
> @@ -569,19 +569,36 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, 
> flag bIsQNaN, flag bIsSNaN,
>  return 3;
>  }
>
> -/* Prefer sNaN over qNaN, in the c, a, b order. */
> -if (cIsSNaN) {
> -return 2;
> -} else if (aIsSNaN) {
> -return 0;
> -} else if (bIsSNaN) {
> -return 1;
> -} else if (cIsQNaN) {
> -return 2;
> -} else if (aIsQNaN) {
> -return 0;

Initially I was confused with this part of diff until I realized that
you had modified the original order in pickNaNMulAdd in patch #1 -- was
that intended?

Otherwise:

Reviewed-by: Leon Alrae 

> +if (status->snan_bit_is_one) {
> +/* Prefer sNaN over qNaN, in the a, b, c order. */
> +if (aIsSNaN) {
> +return 0;
> +} else if (bIsSNaN) {
> +return 1;
> +} else if (cIsSNaN) {
> +return 2;
> +} else if (aIsQNaN) {
> +return 0;
> +} else if (bIsQNaN) {
> +return 1;
> +} else {
> +return 2;
> +}
>  } else {
> -return 1;
> +/* Prefer sNaN over qNaN, in the c, a, b order. */
> +if (cIsSNaN) {
> +return 2;
> +} else if (aIsSNaN) {
> +return 0;
> +} else if (bIsSNaN) {
> +return 1;
> +} else if (cIsQNaN) {
> +return 2;
> +} else if (aIsQNaN) {
> +return 0;
> +} else {
> +return 1;
> +}
>  }
>  }
>  #elif defined(TARGET_PPC)
>

Re: [Qemu-devel] [PATCH v4 3/9] softfloat: For Mips only, correct order in pickNaNMulAdd()

2016-04-13 Thread Leon Alrae 
On 12/04/16 13:58, Aleksandar Markovic wrote:
> From: Aleksandar Markovic 
> 
> Only for Mips platform, and only for cases when snan_bit_is_one is 0,
> correct the order of argument comparisons in pickNaNMulAdd().
> 
> For more info, see [2], page 53, section "3.5.3 NaN Propagation".
> 
> [1] "MIPS® Architecture For Programmers Volume II-A:
> The MIPS64® Instruction Set Reference Manual",
> Imagination Technologies LTD, Revision 6.04, November 13, 2015
> 
> [2] "MIPS Architecture for Programmers Volume IV-j:
> The MIPS32® SIMD Architecture Module",
> Imagination Technologies LTD, Revision 1.12, February 3, 2016
> 
> Signed-off-by: Aleksandar Markovic 
> ---
>  fpu/softfloat-specialize.h |   41 +
>  1 file changed, 29 insertions(+), 12 deletions(-)
> 
> diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
> index 169246e..807ecc0 100644
> --- a/fpu/softfloat-specialize.h
> +++ b/fpu/softfloat-specialize.h
> @@ -569,19 +569,36 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, 
> flag bIsQNaN, flag bIsSNaN,
>  return 3;
>  }
>  
> -/* Prefer sNaN over qNaN, in the c, a, b order. */
> -if (cIsSNaN) {
> -return 2;
> -} else if (aIsSNaN) {
> -return 0;
> -} else if (bIsSNaN) {
> -return 1;
> -} else if (cIsQNaN) {
> -return 2;
> -} else if (aIsQNaN) {
> -return 0;

Initially I was confused with this part of diff until I realized that
you had modified the original order in pickNaNMulAdd in patch #1 -- was
that intended?

Otherwise:

Reviewed-by: Leon Alrae 

> +if (status->snan_bit_is_one) {
> +/* Prefer sNaN over qNaN, in the a, b, c order. */
> +if (aIsSNaN) {
> +return 0;
> +} else if (bIsSNaN) {
> +return 1;
> +} else if (cIsSNaN) {
> +return 2;
> +} else if (aIsQNaN) {
> +return 0;
> +} else if (bIsQNaN) {
> +return 1;
> +} else {
> +return 2;
> +}
>  } else {
> -return 1;
> +/* Prefer sNaN over qNaN, in the c, a, b order. */
> +if (cIsSNaN) {
> +return 2;
> +} else if (aIsSNaN) {
> +return 0;
> +} else if (bIsSNaN) {
> +return 1;
> +} else if (cIsQNaN) {
> +return 2;
> +} else if (aIsQNaN) {
> +return 0;
> +} else {
> +return 1;
> +}
>  }
>  }
>  #elif defined(TARGET_PPC)
>

[Qemu-devel] [PATCH v4 3/9] softfloat: For Mips only, correct order in pickNaNMulAdd()

2016-04-12 Thread Aleksandar Markovic 
From: Aleksandar Markovic 

Only for Mips platform, and only for cases when snan_bit_is_one is 0,
correct the order of argument comparisons in pickNaNMulAdd().

For more info, see [2], page 53, section "3.5.3 NaN Propagation".

[1] "MIPS® Architecture For Programmers Volume II-A:
The MIPS64® Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015

[2] "MIPS Architecture for Programmers Volume IV-j:
The MIPS32® SIMD Architecture Module",
Imagination Technologies LTD, Revision 1.12, February 3, 2016

Signed-off-by: Aleksandar Markovic 
---
 fpu/softfloat-specialize.h |   41 +
 1 file changed, 29 insertions(+), 12 deletions(-)

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 169246e..807ecc0 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -569,19 +569,36 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag 
bIsQNaN, flag bIsSNaN,
 return 3;
 }
 
-/* Prefer sNaN over qNaN, in the c, a, b order. */
-if (cIsSNaN) {
-return 2;
-} else if (aIsSNaN) {
-return 0;
-} else if (bIsSNaN) {
-return 1;
-} else if (cIsQNaN) {
-return 2;
-} else if (aIsQNaN) {
-return 0;
+if (status->snan_bit_is_one) {
+/* Prefer sNaN over qNaN, in the a, b, c order. */
+if (aIsSNaN) {
+return 0;
+} else if (bIsSNaN) {
+return 1;
+} else if (cIsSNaN) {
+return 2;
+} else if (aIsQNaN) {
+return 0;
+} else if (bIsQNaN) {
+return 1;
+} else {
+return 2;
+}
 } else {
-return 1;
+/* Prefer sNaN over qNaN, in the c, a, b order. */
+if (cIsSNaN) {
+return 2;
+} else if (aIsSNaN) {
+return 0;
+} else if (bIsSNaN) {
+return 1;
+} else if (cIsQNaN) {
+return 2;
+} else if (aIsQNaN) {
+return 0;
+} else {
+return 1;
+}
 }
 }
 #elif defined(TARGET_PPC)
-- 
1.7.9.5