This test uses the palmetto platform and the Aspeed SPI controller to
test the m25p80 flash module device model. The flash model is defined
by the platform (n25q256a) and it would be nice to find way to control
it, using a property probably.
Signed-off-by: Cédric Le Goater
Reviewed-by: Peter Maydell
Brainstormed-with: Greg Kurz
---
Changes since v5:
- use an explicit bswap for the values read/written to the flash
region.
Changes since v4:
- fixed Makefile targets
- replaced -M with -m in qtest command line
Changes since v2:
- changed mkstemp() path prefix
Changes since v1:
- fixed guest args to use -drive and not -mtdblock
tests/Makefile.include |2
tests/m25p80-test.c| 252 +
2 files changed, 254 insertions(+)
create mode 100644 tests/m25p80-test.c
Index: qemu-aspeed.git/tests/Makefile.include
===
--- qemu-aspeed.git.orig/tests/Makefile.include
+++ qemu-aspeed.git/tests/Makefile.include
@@ -288,6 +288,7 @@ check-qtest-sparc64-y = tests/endianness
check-qtest-arm-y = tests/tmp105-test$(EXESUF)
check-qtest-arm-y += tests/ds1338-test$(EXESUF)
+check-qtest-arm-y += tests/m25p80-test$(EXESUF)
gcov-files-arm-y += hw/misc/tmp105.c
check-qtest-arm-y += tests/virtio-blk-test$(EXESUF)
gcov-files-arm-y += arm-softmmu/hw/block/virtio-blk.c
@@ -618,6 +619,7 @@ tests/bios-tables-test$(EXESUF): tests/b
tests/pxe-test$(EXESUF): tests/pxe-test.o tests/boot-sector.o $(libqos-obj-y)
tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y)
tests/ds1338-test$(EXESUF): tests/ds1338-test.o $(libqos-imx-obj-y)
+tests/m25p80-test$(EXESUF): tests/m25p80-test.o
tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y)
tests/q35-test$(EXESUF): tests/q35-test.o $(libqos-pc-obj-y)
tests/fw_cfg-test$(EXESUF): tests/fw_cfg-test.o $(libqos-pc-obj-y)
Index: qemu-aspeed.git/tests/m25p80-test.c
===
--- /dev/null
+++ qemu-aspeed.git/tests/m25p80-test.c
@@ -0,0 +1,252 @@
+/*
+ * QTest testcase for the M25P80 Flash (Using the Aspeed SPI
+ * Controller)
+ *
+ * Copyright (C) 2016 IBM Corp.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bswap.h"
+#include "libqtest.h"
+
+/*
+ * ASPEED SPI Controller registers
+ */
+#define R_CONF 0x00
+#define CONF_ENABLE_W0 (1 << 16)
+#define R_CE_CTRL 0x04
+#define CRTL_EXTENDED0 0 /* 32 bit addressing for SPI */
+#define R_CTRL0 0x10
+#define CTRL_CE_STOP_ACTIVE (1 << 2)
+#define CTRL_USERMODE0x3
+
+#define ASPEED_FMC_BASE0x1E62
+#define ASPEED_FLASH_BASE 0x2000
+
+/*
+ * Flash commands
+ */
+enum {
+JEDEC_READ = 0x9f,
+BULK_ERASE = 0xc7,
+READ = 0x03,
+PP = 0x02,
+WREN = 0x6,
+EN_4BYTE_ADDR = 0xB7,
+ERASE_SECTOR = 0xd8,
+};
+
+#define FLASH_JEDEC 0x20ba19 /* n25q256a */
+#define FLASH_SIZE (32 * 1024 * 1024)
+
+#define PAGE_SIZE 256
+
+/*
+ * Use an explicit bswap for the values read/wrote to the flash region
+ * as they are BE and the Aspeed CPU is LE.
+ */
+static inline uint32_t make_be32(uint32_t data)
+{
+return bswap32(data);
+}
+
+static void spi_conf(uint32_t value)
+{
+uint32_t conf = readl(ASPEED_FMC_BASE + R_CONF);
+
+conf |= value;
+writel(ASPEED_FMC_BASE + R_CONF, conf);
+}
+
+static void spi_ctrl_start_user(void)
+{
+uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0);
+
+ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
+writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);
+
+ctrl &= ~CTRL_CE_STOP_ACTIVE;
+writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);
+}
+
+static void spi_ctrl_stop_user(void)
+{
+uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0);
+
+ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
+writel(ASPEED_FMC_BASE +