[Qemu-devel] [PATCH v5 6/7] stm32f205: Add the stm32f205 SoC
This patch adds the stm32f205 SoC. This will be used by the
Netduino 2 to create a machine.
Signed-off-by: Alistair Francis
---
default-configs/arm-softmmu.mak | 1 +
hw/arm/Makefile.objs| 1 +
hw/arm/stm32f205_soc.c | 157
include/hw/arm/stm32f205_soc.h | 69 ++
4 files changed, 228 insertions(+)
create mode 100644 hw/arm/stm32f205_soc.c
create mode 100644 include/hw/arm/stm32f205_soc.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index a2ea8f7..8068100 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -81,6 +81,7 @@ CONFIG_ZYNQ=y
CONFIG_STM32F205_TIMER=y
CONFIG_STM32F205_USART=y
CONFIG_STM32F205_SYSCFG=y
+CONFIG_STM32F205_SOC=y
CONFIG_VERSATILE_PCI=y
CONFIG_VERSATILE_I2C=y
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 6088e53..9769317 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -8,3 +8,4 @@ obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o
pxa2xx_pic.o
obj-$(CONFIG_DIGIC) += digic.o
obj-y += omap1.o omap2.o strongarm.o
obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
+obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
new file mode 100644
index 000..bd9514e
--- /dev/null
+++ b/hw/arm/stm32f205_soc.c
@@ -0,0 +1,157 @@
+/*
+ * STM32F205 SoC
+ *
+ * Copyright (c) 2014 Alistair Francis
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/arm/stm32f205_soc.h"
+
+/* At the moment only Timer 2 to 5 are modelled */
+static const uint32_t timer_addr[] = { 0x4000, 0x4400,
+0x4800, 0x4C00 };
+static const uint32_t usart_addr[] = { 0x40011000, 0x40004400,
+0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
+
+static const int timer_irq[] = {28, 29, 30, 50};
+static const int usart_irq[] = {37, 38, 39, 52, 53, 71, 82, 83};
+
+static void stm32f205_soc_initfn(Object *obj)
+{
+STM32F205State *s = STM32F205_SOC(obj);
+int i;
+
+object_initialize(&s->syscfg, sizeof(s->syscfg), TYPE_STM32F205_SYSCFG);
+qdev_set_parent_bus(DEVICE(&s->syscfg), sysbus_get_default());
+
+for (i = 0; i < 5; i++) {
+object_initialize(&s->usart[i], sizeof(s->usart[i]),
+ TYPE_STM32F205_USART);
+qdev_set_parent_bus(DEVICE(&s->usart[i]), sysbus_get_default());
+}
+
+for (i = 0; i < 4; i++) {
+object_initialize(&s->timer[i], sizeof(s->timer[i]),
+ TYPE_STM32F205_TIMER);
+qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default());
+}
+}
+
+static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
+{
+STM32F205State *s = STM32F205_SOC(dev_soc);
+DeviceState *syscfgdev, *usartdev, *timerdev;
+SysBusDevice *syscfgbusdev, *usartbusdev, *timerbusdev;
+qemu_irq *pic;;
+Error *err = NULL;
+int i;
+
+MemoryRegion *system_memory = get_system_memory();
+MemoryRegion *sram = g_new(MemoryRegion, 1);
+MemoryRegion *flash = g_new(MemoryRegion, 1);
+MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
+
+memory_region_init_ram(flash, NULL, "netduino.flash", FLASH_SIZE,
+ &error_abort);
+memory_region_init_alias(flash_alias, NULL, "netduino.flash.alias",
+ flash, 0, FLASH_SIZE);
+
+vmstate_register_ram_global(flash);
+
+memory_region_set_readonly(flash, true);
+memory_region_set_readonly(flash_alias, true);
+
+memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
+memory_region_add_subregion(system_memory, 0, flash_alias);
+
+memory_region_init_ram(sram, NULL, "netduino.sram", SRAM_SIZE,
+ &error_abort);
+vmstate_register_ram_global(sram);
+memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
+
+pic
Re: [Qemu-devel] [PATCH v5 6/7] stm32f205: Add the stm32f205 SoC
On Thu, Oct 16, 2014 at 10:54 PM, Alistair Francis wrote:
> This patch adds the stm32f205 SoC. This will be used by the
> Netduino 2 to create a machine.
>
> Signed-off-by: Alistair Francis
> ---
> default-configs/arm-softmmu.mak | 1 +
> hw/arm/Makefile.objs| 1 +
> hw/arm/stm32f205_soc.c | 157
>
> include/hw/arm/stm32f205_soc.h | 69 ++
> 4 files changed, 228 insertions(+)
> create mode 100644 hw/arm/stm32f205_soc.c
> create mode 100644 include/hw/arm/stm32f205_soc.h
>
> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
> index a2ea8f7..8068100 100644
> --- a/default-configs/arm-softmmu.mak
> +++ b/default-configs/arm-softmmu.mak
> @@ -81,6 +81,7 @@ CONFIG_ZYNQ=y
> CONFIG_STM32F205_TIMER=y
> CONFIG_STM32F205_USART=y
> CONFIG_STM32F205_SYSCFG=y
> +CONFIG_STM32F205_SOC=y
>
> CONFIG_VERSATILE_PCI=y
> CONFIG_VERSATILE_I2C=y
> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
> index 6088e53..9769317 100644
> --- a/hw/arm/Makefile.objs
> +++ b/hw/arm/Makefile.objs
> @@ -8,3 +8,4 @@ obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o
> pxa2xx_pic.o
> obj-$(CONFIG_DIGIC) += digic.o
> obj-y += omap1.o omap2.o strongarm.o
> obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
> +obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
> diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
> new file mode 100644
> index 000..bd9514e
> --- /dev/null
> +++ b/hw/arm/stm32f205_soc.c
> @@ -0,0 +1,157 @@
> +/*
> + * STM32F205 SoC
> + *
> + * Copyright (c) 2014 Alistair Francis
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> copy
> + * of this software and associated documentation files (the "Software"), to
> deal
> + * in the Software without restriction, including without limitation the
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "hw/arm/stm32f205_soc.h"
> +
> +/* At the moment only Timer 2 to 5 are modelled */
> +static const uint32_t timer_addr[] = { 0x4000, 0x4400,
> +0x4800, 0x4C00 };
> +static const uint32_t usart_addr[] = { 0x40011000, 0x40004400,
> +0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
> +
You have 6 addresses for USART ...
> +static const int timer_irq[] = {28, 29, 30, 50};
> +static const int usart_irq[] = {37, 38, 39, 52, 53, 71, 82, 83};
> +
... but 8 IRQS and the loop below uses only 5 values. What's the system exactly?
> +static void stm32f205_soc_initfn(Object *obj)
> +{
> +STM32F205State *s = STM32F205_SOC(obj);
> +int i;
> +
> +object_initialize(&s->syscfg, sizeof(s->syscfg), TYPE_STM32F205_SYSCFG);
> +qdev_set_parent_bus(DEVICE(&s->syscfg), sysbus_get_default());
> +
> +for (i = 0; i < 5; i++) {
> +object_initialize(&s->usart[i], sizeof(s->usart[i]),
> + TYPE_STM32F205_USART);
> +qdev_set_parent_bus(DEVICE(&s->usart[i]), sysbus_get_default());
> +}
> +
> +for (i = 0; i < 4; i++) {
> +object_initialize(&s->timer[i], sizeof(s->timer[i]),
> + TYPE_STM32F205_TIMER);
> +qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default());
> +}
> +}
> +
> +static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
> +{
> +STM32F205State *s = STM32F205_SOC(dev_soc);
> +DeviceState *syscfgdev, *usartdev, *timerdev;
> +SysBusDevice *syscfgbusdev, *usartbusdev, *timerbusdev;
> +qemu_irq *pic;;
stray ;
> +Error *err = NULL;
> +int i;
> +
> +MemoryRegion *system_memory = get_system_memory();
> +MemoryRegion *sram = g_new(MemoryRegion, 1);
> +MemoryRegion *flash = g_new(MemoryRegion, 1);
> +MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
> +
> +memory_region_init_ram(flash, NULL, "netduino.flash", FLASH_SIZE,
> + &error_abort);
> +memory_region_init_alias(flash_alias, NULL, "netduino.flash.alias",
> + flash, 0, FLASH_SIZE);
> +
> +vmstate_register_ram_global(flash);
> +
> +memory_region_set_readonly(flash, true
Re: [Qemu-devel] [PATCH v5 6/7] stm32f205: Add the stm32f205 SoC
On Mon, Oct 20, 2014 at 5:47 PM, Peter Crosthwaite
wrote:
> On Thu, Oct 16, 2014 at 10:54 PM, Alistair Francis
> wrote:
>> This patch adds the stm32f205 SoC. This will be used by the
>> Netduino 2 to create a machine.
>>
>> Signed-off-by: Alistair Francis
>> ---
>> default-configs/arm-softmmu.mak | 1 +
>> hw/arm/Makefile.objs| 1 +
>> hw/arm/stm32f205_soc.c | 157
>>
>> include/hw/arm/stm32f205_soc.h | 69 ++
>> 4 files changed, 228 insertions(+)
>> create mode 100644 hw/arm/stm32f205_soc.c
>> create mode 100644 include/hw/arm/stm32f205_soc.h
>>
>> diff --git a/default-configs/arm-softmmu.mak
>> b/default-configs/arm-softmmu.mak
>> index a2ea8f7..8068100 100644
>> --- a/default-configs/arm-softmmu.mak
>> +++ b/default-configs/arm-softmmu.mak
>> @@ -81,6 +81,7 @@ CONFIG_ZYNQ=y
>> CONFIG_STM32F205_TIMER=y
>> CONFIG_STM32F205_USART=y
>> CONFIG_STM32F205_SYSCFG=y
>> +CONFIG_STM32F205_SOC=y
>>
>> CONFIG_VERSATILE_PCI=y
>> CONFIG_VERSATILE_I2C=y
>> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
>> index 6088e53..9769317 100644
>> --- a/hw/arm/Makefile.objs
>> +++ b/hw/arm/Makefile.objs
>> @@ -8,3 +8,4 @@ obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o
>> pxa2xx_pic.o
>> obj-$(CONFIG_DIGIC) += digic.o
>> obj-y += omap1.o omap2.o strongarm.o
>> obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
>> +obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
>> diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
>> new file mode 100644
>> index 000..bd9514e
>> --- /dev/null
>> +++ b/hw/arm/stm32f205_soc.c
>> @@ -0,0 +1,157 @@
>> +/*
>> + * STM32F205 SoC
>> + *
>> + * Copyright (c) 2014 Alistair Francis
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a
>> copy
>> + * of this software and associated documentation files (the "Software"), to
>> deal
>> + * in the Software without restriction, including without limitation the
>> rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be included
>> in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>> OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>> + * THE SOFTWARE.
>> + */
>> +
>> +#include "hw/arm/stm32f205_soc.h"
>> +
>> +/* At the moment only Timer 2 to 5 are modelled */
>> +static const uint32_t timer_addr[] = { 0x4000, 0x4400,
>> +0x4800, 0x4C00 };
>> +static const uint32_t usart_addr[] = { 0x40011000, 0x40004400,
>> +0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
>> +
>
> You have 6 addresses for USART ...
>
>> +static const int timer_irq[] = {28, 29, 30, 50};
>> +static const int usart_irq[] = {37, 38, 39, 52, 53, 71, 82, 83};
>> +
>
> ... but 8 IRQS and the loop below uses only 5 values. What's the system
> exactly?
These must be left over from the Netduino Plus 2. I think it's just
the first five, but I'll
double check and fix in a respin
>
>> +static void stm32f205_soc_initfn(Object *obj)
>> +{
>> +STM32F205State *s = STM32F205_SOC(obj);
>> +int i;
>> +
>> +object_initialize(&s->syscfg, sizeof(s->syscfg), TYPE_STM32F205_SYSCFG);
>> +qdev_set_parent_bus(DEVICE(&s->syscfg), sysbus_get_default());
>> +
>> +for (i = 0; i < 5; i++) {
>> +object_initialize(&s->usart[i], sizeof(s->usart[i]),
>> + TYPE_STM32F205_USART);
>> +qdev_set_parent_bus(DEVICE(&s->usart[i]), sysbus_get_default());
>> +}
>> +
>> +for (i = 0; i < 4; i++) {
>> +object_initialize(&s->timer[i], sizeof(s->timer[i]),
>> + TYPE_STM32F205_TIMER);
>> +qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default());
>> +}
>> +}
>> +
>> +static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
>> +{
>> +STM32F205State *s = STM32F205_SOC(dev_soc);
>> +DeviceState *syscfgdev, *usartdev, *timerdev;
>> +SysBusDevice *syscfgbusdev, *usartbusdev, *timerbusdev;
>> +qemu_irq *pic;;
>
> stray ;
Will fix
>
>> +Error *err = NULL;
>> +int i;
>> +
>> +MemoryRegion *system_memory = get_system_memory();
>> +MemoryRegion *sram = g_new(MemoryRegion, 1);
>> +MemoryRegion *flash = g_new(MemoryRegion, 1);
>> +MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
