Re: [Qemu-devel] [PATCH v5 9/9] target-mips: Clean up position of abs2008/nan2008 cases in genfarith()

[Aleksandar Markovic]

Diff looks messy, but, in fact, this change is just changing location of
six cases in gen_farith().

This is illustrated in the diagram below: (I added indentation of 2 spaces for
abs2008-related cases, and 4 spaces for nan2008-related cases, to stress
the effect of grouping cases with similar handling; right order of cases is
of tremendous help during development; the diagram makes sense only
if it is displayed with fixed width fonts; you can copy/paste it in any editor
if that is not he case)

case OPC_ADD_S   case OPC_ADD_S
case OPC_SUB_S   case OPC_SUB_S
case OPC_MUL_S   case OPC_MUL_S
case OPC_DIV_S   case OPC_DIV_S
case OPC_SQRT_S  case OPC_SQRT_S   
  case OPC_ABS_S  -| case OPC_MOV_S
case OPC_MOV_S |-->case OPC_ABS_S  
  case OPC_NEG_S   case OPC_NEG_S  
case OPC_ROUND_L_S |-->  case OPC_CVT_L_S  
case OPC_TRUNC_L_S | case OPC_ROUND_L_S
case OPC_CEIL_L_S  | case OPC_TRUNC_L_S
case OPC_FLOOR_L_S | case OPC_CEIL_L_S 
case OPC_ROUND_W_S | case OPC_FLOOR_L_S
case OPC_TRUNC_W_S |  |--->  case OPC_CVT_W_S  
case OPC_CEIL_W_S  |  |  case OPC_ROUND_W_S
case OPC_FLOOR_W_S |  |  case OPC_TRUNC_W_S
case OPC_SEL_S |  |  case OPC_CEIL_W_S 
case OPC_SELEQZ_S  |  |  case OPC_FLOOR_W_S
case OPC_SELNEZ_S  |  |  case OPC_SEL_S
case OPC_MOVCF_S   |  |  case OPC_SELEQZ_S 
case OPC_MOVZ_S|  |  case OPC_SELNEZ_S 
case OPC_MOVN_S|  |  case OPC_MOVCF_S  
case OPC_RECIP_S   |  |  case OPC_MOVZ_S   
case OPC_RSQRT_S   |  |  case OPC_MOVN_S   
case OPC_MADDF_S   |  |  case OPC_RECIP_S  
case OPC_MSUBF_S   |  |  case OPC_RSQRT_S  
case OPC_RINT_S|  |  case OPC_MADDF_S  
case OPC_CLASS_S   |  |  case OPC_MSUBF_S  
case OPC_MIN_S |  |  case OPC_RINT_S   
case OPC_MINA_S|  |  case OPC_CLASS_S  
case OPC_MAX_S |  |  case OPC_MIN_S
case OPC_MAXA_S|  |  case OPC_MINA_S   
case OPC_CVT_D_S   |  |  case OPC_MAX_S
case OPC_CVT_W_S  |  case OPC_MAXA_S   
case OPC_CVT_L_S  -| case OPC_CVT_D_S  
case OPC_CVT_PS_Scase OPC_CVT_PS_S 
case OPC_CMP_F_S case OPC_CMP_F_S  
case OPC_CMP_UN_Scase OPC_CMP_UN_S 
case OPC_CMP_EQ_Scase OPC_CMP_EQ_S 
case OPC_CMP_UEQ_S   case OPC_CMP_UEQ_S
case OPC_CMP_OLT_S   case OPC_CMP_OLT_S
case OPC_CMP_ULT_S   case OPC_CMP_ULT_S
case OPC_CMP_OLE_S   case OPC_CMP_OLE_S
case OPC_CMP_ULE_S   case OPC_CMP_ULE_S
case OPC_CMP_SF_Scase OPC_CMP_SF_S 
case OPC_CMP_NGLE_S  case OPC_CMP_NGLE_S   
case OPC_CMP_SEQ_S   case OPC_CMP_SEQ_S
case OPC_CMP_NGL_S   case OPC_CMP_NGL_S
case OPC_CMP_LT_Scase OPC_CMP_LT_S 
case OPC_CMP_NGE_S   case OPC_CMP_NGE_S
case OPC_CMP_LE_Scase OPC_CMP_LE_S 
case OPC_CMP_NGT_S   case OPC_CMP_NGT_S
case OPC_ADD_D   case OPC_ADD_D
case OPC_SUB_D   case OPC_SUB_D
case OPC_MUL_D   case OPC_MUL_D
case OPC_DIV_D   case OPC_DIV_D
case OPC_SQRT_D  case OPC_SQRT_D   
  case OPC_ABS_D  -| case OPC_MOV_D
case OPC_MOV_D |-->case OPC_ABS_D  
  case OPC_NEG_D   case OPC_NEG_D  
case OPC_ROUND_L_D |-->  case OPC_CVT_L_D  
case OPC_TRUNC_L_D | case OPC_ROUND_L_D
case OPC_CEIL_L_D  | case OPC_TRUNC_L_D
case OPC_FLOOR_L_D | case OPC_CEIL_L_D 
case OPC_ROUND_W_D | case OPC_FLOOR_L_D
case OPC_TRUNC_W_D |  |--->  case OPC_CVT_W_D  

[Qemu-devel] [PATCH v5 9/9] target-mips: Clean up position of abs2008/nan2008 cases in genfarith()

[Aleksandar Markovic]

From: Aleksandar Markovic 

This patch slightly reorders cases in genfarith() so that abs2008/nan2008-
dependant cases are grouped together, for easier maintenantce (code becomes
less prone to errors).

Signed-off-by: Aleksandar Markovic 
---
 target-mips/translate.c | 152 
 1 file changed, 76 insertions(+), 76 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index b7ab98a..76df972 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -8876,25 +8876,25 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 tcg_temp_free_i32(fp0);
 }
 break;
-case OPC_ABS_S:
+case OPC_MOV_S:
 {
 TCGv_i32 fp0 = tcg_temp_new_i32();
 
 gen_load_fpr32(ctx, fp0, fs);
-if (ctx->abs2008) {
-tcg_gen_andi_i32(fp0, fp0, 0x7fffUL);
-} else {
-gen_helper_float_abs_s(fp0, fp0);
-}
 gen_store_fpr32(ctx, fp0, fd);
 tcg_temp_free_i32(fp0);
 }
 break;
-case OPC_MOV_S:
+case OPC_ABS_S:
 {
 TCGv_i32 fp0 = tcg_temp_new_i32();
 
 gen_load_fpr32(ctx, fp0, fs);
+if (ctx->abs2008) {
+tcg_gen_andi_i32(fp0, fp0, 0x7fffUL);
+} else {
+gen_helper_float_abs_s(fp0, fp0);
+}
 gen_store_fpr32(ctx, fp0, fd);
 tcg_temp_free_i32(fp0);
 }
@@ -8913,6 +8913,23 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 tcg_temp_free_i32(fp0);
 }
 break;
+case OPC_CVT_L_S:
+check_cp1_64bitmode(ctx);
+{
+TCGv_i32 fp32 = tcg_temp_new_i32();
+TCGv_i64 fp64 = tcg_temp_new_i64();
+
+gen_load_fpr32(ctx, fp32, fs);
+if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->nan2008)) {
+gen_helper_float_cvt_2008_l_s(fp64, cpu_env, fp32);
+} else {
+gen_helper_float_cvt_l_s(fp64, cpu_env, fp32);
+}
+tcg_temp_free_i32(fp32);
+gen_store_fpr64(ctx, fp64, fd);
+tcg_temp_free_i64(fp64);
+}
+break;
 case OPC_ROUND_L_S:
 check_cp1_64bitmode(ctx);
 {
@@ -8981,6 +8998,20 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 tcg_temp_free_i64(fp64);
 }
 break;
+case OPC_CVT_W_S:
+{
+TCGv_i32 fp0 = tcg_temp_new_i32();
+
+gen_load_fpr32(ctx, fp0, fs);
+if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->nan2008)) {
+gen_helper_float_cvt_2008_w_s(fp0, cpu_env, fp0);
+} else {
+gen_helper_float_cvt_w_s(fp0, cpu_env, fp0);
+}
+gen_store_fpr32(ctx, fp0, fd);
+tcg_temp_free_i32(fp0);
+}
+break;
 case OPC_ROUND_W_S:
 {
 TCGv_i32 fp0 = tcg_temp_new_i32();
@@ -9276,37 +9307,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 tcg_temp_free_i64(fp64);
 }
 break;
-case OPC_CVT_W_S:
-{
-TCGv_i32 fp0 = tcg_temp_new_i32();
-
-gen_load_fpr32(ctx, fp0, fs);
-if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->nan2008)) {
-gen_helper_float_cvt_2008_w_s(fp0, cpu_env, fp0);
-} else {
-gen_helper_float_cvt_w_s(fp0, cpu_env, fp0);
-}
-gen_store_fpr32(ctx, fp0, fd);
-tcg_temp_free_i32(fp0);
-}
-break;
-case OPC_CVT_L_S:
-check_cp1_64bitmode(ctx);
-{
-TCGv_i32 fp32 = tcg_temp_new_i32();
-TCGv_i64 fp64 = tcg_temp_new_i64();
-
-gen_load_fpr32(ctx, fp32, fs);
-if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->nan2008)) {
-gen_helper_float_cvt_2008_l_s(fp64, cpu_env, fp32);
-} else {
-gen_helper_float_cvt_l_s(fp64, cpu_env, fp32);
-}
-tcg_temp_free_i32(fp32);
-gen_store_fpr64(ctx, fp64, fd);
-tcg_temp_free_i64(fp64);
-}
-break;
 case OPC_CVT_PS_S:
 check_ps(ctx);
 {
@@ -9413,6 +9413,16 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
 tcg_temp_free_i64(fp0);
 }
 break;
+case OPC_MOV_D:
+check_cp1_registers(ctx, fs | fd);
+{
+TCGv_i64 fp0 = tcg_temp_new_i64();
+
+gen_load_fpr64(ctx, fp0, fs);
+gen_store_fpr64(ctx, fp0, fd);
+tcg_temp_free_i64(fp0);
+}
+break;
 case OPC_ABS_D:
 check_cp1_registers(ctx, fs | fd);
 {
@@ -9428,26 +9438,31 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,