Re: [Qemu-devel] [PATCH v6 05/32] target-arm: make arm_current_el() return EL3
On 10 October 2014 18:03, Greg Bellows greg.bell...@linaro.org wrote:
From: Fabian Aggeler aggel...@ethz.ch
Make arm_current_el() return EL3 for secure PL1 and monitor mode.
Increase MMU modes since mmu_index is directly infered from arm_
inferred
current_el(). Changes assertion in arm_el_is_aa64() to allow EL3.
Change
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
Signed-off-by: Greg Bellows greg.bell...@linaro.org
==
v5 - v6
- Rework arm_current_el() logic to properly return EL3 for secure PL1 when EL3
is 32-bit.
- Replace direct access of env-aarch64 with is_a64()
---
target-arm/cpu.h | 29 -
1 file changed, 20 insertions(+), 9 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 149f258..ed32b97 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -100,7 +100,7 @@ typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
struct arm_boot_info;
-#define NB_MMU_MODES 2
+#define NB_MMU_MODES 4
/* We currently assume float and double are IEEE single and double
precision respectively.
@@ -798,11 +798,12 @@ static inline bool arm_is_secure(CPUARMState *env)
/* Return true if the specified exception level is running in AArch64 state.
*/
static inline bool arm_el_is_aa64(CPUARMState *env, int el)
{
-/* We don't currently support EL2 or EL3, and this isn't valid for EL0
+/* We don't currently support EL2, and this isn't valid for EL0
* (if we're in EL0, is_a64() is what you want, and if we're not in EL0
* then the state of EL0 isn't well defined.)
*/
-assert(el == 1);
+assert(el == 1 || el == 3);
+
/* AArch64-capable CPUs always run with EL1 in AArch64 mode. This
* is a QEMU-imposed simplification which we may wish to change later.
* If we in future support EL2 and/or EL3, then the state of lower
@@ -991,17 +992,27 @@ static inline bool cptype_valid(int cptype)
*/
static inline int arm_current_el(CPUARMState *env)
{
-if (env-aarch64) {
+if (is_a64(env)) {
return extract32(env-pstate, 2, 2);
}
-if ((env-uncached_cpsr 0x1f) == ARM_CPU_MODE_USR) {
+switch (env-uncached_cpsr 0x1f) {
Use CPSR_M, not a raw 0x1f, please.
+case ARM_CPU_MODE_USR:
return 0;
+case ARM_CPU_MODE_HYP:
+return 2;
+case ARM_CPU_MODE_MON:
+return 3;
+default:
+if (arm_is_secure(env) !arm_el_is_aa64(env, 3)) {
+/* If EL3 is 32-bit then all secure privileged modes run in
+ * EL3
+ */
+return 3;
+}
+
+return 1;
Otherwise
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
thanks
-- PMM
[Qemu-devel] [PATCH v6 05/32] target-arm: make arm_current_el() return EL3
From: Fabian Aggeler aggel...@ethz.ch
Make arm_current_el() return EL3 for secure PL1 and monitor mode.
Increase MMU modes since mmu_index is directly infered from arm_
current_el(). Changes assertion in arm_el_is_aa64() to allow EL3.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
Signed-off-by: Greg Bellows greg.bell...@linaro.org
==
v5 - v6
- Rework arm_current_el() logic to properly return EL3 for secure PL1 when EL3
is 32-bit.
- Replace direct access of env-aarch64 with is_a64()
---
target-arm/cpu.h | 29 -
1 file changed, 20 insertions(+), 9 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 149f258..ed32b97 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -100,7 +100,7 @@ typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
struct arm_boot_info;
-#define NB_MMU_MODES 2
+#define NB_MMU_MODES 4
/* We currently assume float and double are IEEE single and double
precision respectively.
@@ -798,11 +798,12 @@ static inline bool arm_is_secure(CPUARMState *env)
/* Return true if the specified exception level is running in AArch64 state. */
static inline bool arm_el_is_aa64(CPUARMState *env, int el)
{
-/* We don't currently support EL2 or EL3, and this isn't valid for EL0
+/* We don't currently support EL2, and this isn't valid for EL0
* (if we're in EL0, is_a64() is what you want, and if we're not in EL0
* then the state of EL0 isn't well defined.)
*/
-assert(el == 1);
+assert(el == 1 || el == 3);
+
/* AArch64-capable CPUs always run with EL1 in AArch64 mode. This
* is a QEMU-imposed simplification which we may wish to change later.
* If we in future support EL2 and/or EL3, then the state of lower
@@ -991,17 +992,27 @@ static inline bool cptype_valid(int cptype)
*/
static inline int arm_current_el(CPUARMState *env)
{
-if (env-aarch64) {
+if (is_a64(env)) {
return extract32(env-pstate, 2, 2);
}
-if ((env-uncached_cpsr 0x1f) == ARM_CPU_MODE_USR) {
+switch (env-uncached_cpsr 0x1f) {
+case ARM_CPU_MODE_USR:
return 0;
+case ARM_CPU_MODE_HYP:
+return 2;
+case ARM_CPU_MODE_MON:
+return 3;
+default:
+if (arm_is_secure(env) !arm_el_is_aa64(env, 3)) {
+/* If EL3 is 32-bit then all secure privileged modes run in
+ * EL3
+ */
+return 3;
+}
+
+return 1;
}
-/* We don't currently implement the Virtualization or TrustZone
- * extensions, so EL2 and EL3 don't exist for us.
- */
-return 1;
}
typedef struct ARMCPRegInfo ARMCPRegInfo;
--
1.8.3.2
