[Qemu-devel] [PATCH v6 09/11] target-avr: updating translate.c to use instructions translation

[Michael Rolnik]

From: Michael Rolnik 

Signed-off-by: Michael Rolnik 
---
 target-avr/Makefile.objs |   4 +-
 target-avr/translate.c   | 148 +--
 2 files changed, 69 insertions(+), 83 deletions(-)

diff --git a/target-avr/Makefile.objs b/target-avr/Makefile.objs
index 2a10104..9757721 100644
--- a/target-avr/Makefile.objs
+++ b/target-avr/Makefile.objs
@@ -18,6 +18,8 @@
 #  
 #
 
-obj-y   += translate.o cpu.o helper.o
+obj-y   += translate.o helper.o cpu.o translate-inst.o
 obj-y   += gdbstub.o
 obj-$(CONFIG_SOFTMMU) += machine.o
+
+obj-y   += decode.o
diff --git a/target-avr/translate.c b/target-avr/translate.c
index 81ee44e..28babc9 100644
--- a/target-avr/translate.c
+++ b/target-avr/translate.c
@@ -18,60 +18,30 @@
  *  
  */
 
-#include "qemu/osdep.h"
-
-#include "cpu.h"
-#include "exec/exec-all.h"
-#include "disas/disas.h"
-#include "tcg-op.h"
-#include "exec/cpu_ldst.h"
-
-#include "exec/helper-proto.h"
-#include "exec/helper-gen.h"
-#include "exec/log.h"
-
-typedef struct DisasContext DisasContext;
-typedef struct InstInfo InstInfo;
-
-/*This is the state at translation time.  */
-struct DisasContext {
-struct TranslationBlock*tb;
-
-/*Routine used to access memory */
-int memidx;
-int bstate;
-int singlestep;
-};
-
-enum {
-BS_NONE = 0,/*  Nothing special (none of the below  */
-BS_STOP = 1,/*  We want to stop translation for any reason  */
-BS_BRANCH = 2,/*  A branch condition is reached   */
-BS_EXCP = 3,/*  An exception condition is reached   */
-};
-
-static TCGv_env cpu_env;
-
-static TCGv cpu_pc;
-
-static TCGv cpu_Cf;
-static TCGv cpu_Zf;
-static TCGv cpu_Nf;
-static TCGv cpu_Vf;
-static TCGv cpu_Sf;
-static TCGv cpu_Hf;
-static TCGv cpu_Tf;
-static TCGv cpu_If;
-
-static TCGv cpu_rampD;
-static TCGv cpu_rampX;
-static TCGv cpu_rampY;
-static TCGv cpu_rampZ;
-
-static TCGv cpu_io[64];
-static TCGv cpu_r[32];
-static TCGv cpu_eind;
-static TCGv cpu_sp;
+#include "translate.h"
+
+TCGv_env cpu_env;
+
+TCGv cpu_pc;
+
+TCGv cpu_Cf;
+TCGv cpu_Zf;
+TCGv cpu_Nf;
+TCGv cpu_Vf;
+TCGv cpu_Sf;
+TCGv cpu_Hf;
+TCGv cpu_Tf;
+TCGv cpu_If;
+
+TCGv cpu_rampD;
+TCGv cpu_rampX;
+TCGv cpu_rampY;
+TCGv cpu_rampZ;
+
+TCGv cpu_io[64];
+TCGv cpu_r[32];
+TCGv cpu_eind;
+TCGv cpu_sp;
 
 #include "exec/gen-icount.h"
 #define REG(x)  (cpu_r[x])
@@ -120,25 +90,32 @@ void avr_translate_init(void)
 done_init = 1;
 }
 
-static inline void gen_goto_tb(CPUAVRState *env, DisasContext *ctx, int n,
-target_ulong dest)
+static void decode_opc(AVRCPU *cpu, DisasContext *ctx, InstInfo *inst)
 {
-TranslationBlock   *tb;
-
-tb = ctx->tb;
-
-if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)
-&&  (ctx->singlestep == 0)) {
-tcg_gen_goto_tb(n);
-tcg_gen_movi_i32(cpu_pc, dest);
-tcg_gen_exit_tb((uintptr_t)tb + n);
-} else {
-tcg_gen_movi_i32(cpu_pc, dest);
-
-if (ctx->singlestep) {
-gen_helper_debug(cpu_env);
-}
-tcg_gen_exit_tb(0);
+CPUAVRState*env = &cpu->env;
+
+inst->opcode = cpu_ldl_code(env, inst->cpc * 2);/*  pc points to words  */
+/*  target is defined as bigendian for push_ret/pop_ret
+optimization. but my decode assumes instruction to be in little
+endian format, hence bswap
+*/
+inst->opcode = bswap32(inst->opcode);
+inst->length = 16;
+inst->translate = NULL;
+
+/*  the following function looks onto the opcode as a string of bytes   */
+avr_decode(inst->cpc, &inst->length, inst->opcode, &inst->translate);
+
+if (inst->length == 16) {
+inst->npc = inst->cpc + 1;
+/*  get opcode as 16bit value   */
+inst->opcode = inst->opcode & 0x;
+}
+if (inst->length == 32) {
+inst->npc = inst->cpc + 2;
+/*  get opcode as 32bit value   */
+inst->opcode = (inst->opcode << 16)
+ | (inst->opcode >> 16);
 }
 }
 
@@ -172,18 +149,21 @@ void gen_intermediate_code(CPUAVRState *env, struct 
TranslationBlock *tb)
 gen_tb_start(tb);
 
 /*  decode first instruction*/
-cpc = pc_start;
-npc = cpc + 1;
+ctx.inst[0].cpc = pc_start;
+decode_opc(cpu, &ctx, &ctx.inst[0]);
 do {
-/*  translate current instruction   */
+/*  set curr/next PCs   */
+cpc = ctx.inst[0].cpc;
+npc = ctx.inst[0].npc;
+
+/*  decode next instruction */
+ctx.inst[1].cpc = ctx.inst[0].npc;
+decode_opc(cpu, &ctx, &ctx.inst[1]);
+
+/*  translate current instruction */
 tcg_gen_insn_star

Re: [Qemu-devel] [PATCH v6 09/11] target-avr: updating translate.c to use instructions translation

[Richard Henderson]

On 06/12/2016 12:01 PM, Michael Rolnik wrote:

+/*  target is defined as bigendian for push_ret/pop_ret
+optimization. but my decode assumes instruction to be in little
+endian format, hence bswap
+*/
+inst->opcode = bswap32(inst->opcode);


You don't have to do that.  Indeed, you shouldn't.

Note in my reply to patch 8, how one can individually specify a big-endian load 
for one memory operation.



r~