[Qemu-devel] [PATCHv3 5/7] spapr: Adjust placement of PCI host bridge to allow > 1TiB RAM
Currently the default PCI host bridge for the 'pseries' machine type is constructed with its IO windows in the 1TiB..(1TiB + 64GiB) range in guest memory space. This means that if > 1TiB of guest RAM is specified, the RAM will collide with the PCI IO windows, causing serious problems. Problems won't be obvious until guest RAM goes a bit beyond 1TiB, because there's a little unused space at the bottom of the area reserved for PCI, but essentially this means that > 1TiB of RAM has never worked with the pseries machine type. This patch fixes this by altering the placement of PHBs on large-RAM VMs. Instead of always placing the first PHB at 1TiB, it is placed at the next 1 TiB boundary after the maximum RAM address. Technically, this changes behaviour in a migration-breaking way for existing machines with > 1TiB maximum memory, but since having > 1 TiB memory was broken anyway, this seems like a reasonable trade-off. Signed-off-by: David Gibson --- hw/ppc/spapr.c | 16 ++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index cb9da96..e6b110d 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -2375,15 +2375,27 @@ static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, unsigned n_dma, uint32_t *liobns, Error **errp) { const uint64_t base_buid = 0x8002000ULL; -const hwaddr phb0_base = 0x100ULL; /* 1 TiB */ const hwaddr phb_spacing = 0x10ULL; /* 64 GiB */ const hwaddr mmio_offset = 0xa000; /* 2 GiB + 512 MiB */ const hwaddr pio_offset = 0x8000; /* 2 GiB */ const uint32_t max_index = 255; +const hwaddr phb0_alignment = 0x100ULL; /* 1 TiB */ -hwaddr phb_base; +uint64_t ram_top = MACHINE(spapr)->ram_size; +hwaddr phb0_base, phb_base; int i; +/* Do we have hotpluggable memory? */ +if (MACHINE(spapr)->maxram_size > ram_top) { +/* Can't just use maxram_size, because there may be an + * alignment gap between normal and hotpluggable memory + * regions */ +ram_top = spapr->hotplug_memory.base + +memory_region_size(&spapr->hotplug_memory.mr); +} + +phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); + if (index > max_index) { error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", max_index); -- 2.7.4
Re: [Qemu-devel] [PATCHv3 5/7] spapr: Adjust placement of PCI host bridge to allow > 1TiB RAM
On 13/10/2016 01:57, David Gibson wrote: > Currently the default PCI host bridge for the 'pseries' machine type is > constructed with its IO windows in the 1TiB..(1TiB + 64GiB) range in > guest memory space. This means that if > 1TiB of guest RAM is specified, > the RAM will collide with the PCI IO windows, causing serious problems. > > Problems won't be obvious until guest RAM goes a bit beyond 1TiB, because > there's a little unused space at the bottom of the area reserved for PCI, > but essentially this means that > 1TiB of RAM has never worked with the > pseries machine type. > > This patch fixes this by altering the placement of PHBs on large-RAM VMs. > Instead of always placing the first PHB at 1TiB, it is placed at the next > 1 TiB boundary after the maximum RAM address. > > Technically, this changes behaviour in a migration-breaking way for > existing machines with > 1TiB maximum memory, but since having > 1 TiB > memory was broken anyway, this seems like a reasonable trade-off. > > Signed-off-by: David Gibson Reviewed-by: Laurent Vivier > --- > hw/ppc/spapr.c | 16 ++-- > 1 file changed, 14 insertions(+), 2 deletions(-) > > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c > index cb9da96..e6b110d 100644 > --- a/hw/ppc/spapr.c > +++ b/hw/ppc/spapr.c > @@ -2375,15 +2375,27 @@ static void spapr_phb_placement(sPAPRMachineState > *spapr, uint32_t index, > unsigned n_dma, uint32_t *liobns, Error > **errp) > { > const uint64_t base_buid = 0x8002000ULL; > -const hwaddr phb0_base = 0x100ULL; /* 1 TiB */ > const hwaddr phb_spacing = 0x10ULL; /* 64 GiB */ > const hwaddr mmio_offset = 0xa000; /* 2 GiB + 512 MiB */ > const hwaddr pio_offset = 0x8000; /* 2 GiB */ > const uint32_t max_index = 255; > +const hwaddr phb0_alignment = 0x100ULL; /* 1 TiB */ > > -hwaddr phb_base; > +uint64_t ram_top = MACHINE(spapr)->ram_size; > +hwaddr phb0_base, phb_base; > int i; > > +/* Do we have hotpluggable memory? */ > +if (MACHINE(spapr)->maxram_size > ram_top) { > +/* Can't just use maxram_size, because there may be an > + * alignment gap between normal and hotpluggable memory > + * regions */ > +ram_top = spapr->hotplug_memory.base + > +memory_region_size(&spapr->hotplug_memory.mr); > +} > + > +phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); > + > if (index > max_index) { > error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", > max_index); >