[Qemu-devel] [PULL 00/19] target-arm queue

[Peter Maydell]

Latest set of arm patches. I may end up doing another pullreq at the
end of the week, but this is big enough to send out, plus it has
several instances of "let me take the first N patches in your series"
in it, so getting those into master makes patch respins for those
submitters easier.

thanks
-- PMM

The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:

  Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' 
into staging (2018-10-15 18:44:04 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20181016

for you to fetch changes up to bdaffef4bb0729a74c7a325dba5c61d8cd8f464f:

  coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls 
(2018-10-16 16:16:42 +0100)


target-arm queue:
 * hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure 
UART
 * target/arm: Fix aarch64_sve_change_el wrt EL0
 * target/arm: Define fields of ISAR registers
 * target/arm: Align cortex-r5 id_isar0
 * target/arm: Fix cortex-a7 id_isar0
 * net/cadence_gem: Fix various bugs, add support for new
   features that will be used by the Xilinx Versal board
 * target-arm: powerctl: Enable HVC when starting CPUs to EL2
 * target/arm: Add the Cortex-A72
 * target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
 * target/arm: Mask PMOVSR writes based on supported counters
 * target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
 * coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls


Aaron Lindsay (2):
  target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing 
IO
  target/arm: Mask PMOVSR writes based on supported counters

Edgar E. Iglesias (10):
  net: cadence_gem: Disable TSU feature bit
  net: cadence_gem: Announce availability of priority queues
  net: cadence_gem: Use uint32_t for 32bit descriptor words
  net: cadence_gem: Add macro with max number of descriptor words
  net: cadence_gem: Add support for extended descriptors
  net: cadence_gem: Add support for selecting the DMA MemoryRegion
  net: cadence_gem: Implement support for 64bit descriptor addresses
  net: cadence_gem: Announce 64bit addressing support
  target-arm: powerctl: Enable HVC when starting CPUs to EL2
  target/arm: Add the Cortex-A72

Jerome Forissier (1):
  hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure 
UART

Peter Maydell (2):
  target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
  coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping 
calls

Richard Henderson (4):
  target/arm: Fix aarch64_sve_change_el wrt EL0
  target/arm: Define fields of ISAR registers
  target/arm: Align cortex-r5 id_isar0
  target/arm: Fix cortex-a7 id_isar0

 include/hw/net/cadence_gem.h   |   7 +-
 target/arm/cpu.h   |  95 +-
 hw/arm/virt.c  |   4 +
 hw/net/cadence_gem.c   | 192 +
 target/arm/arm-powerctl.c  |  10 ++
 target/arm/cpu.c   |   7 +-
 target/arm/cpu64.c |  66 +-
 target/arm/helper.c|  27 ++--
 target/arm/op_helper.c |   6 +-
 scripts/coccinelle/inplace-byteswaps.cocci |  65 ++
 10 files changed, 408 insertions(+), 71 deletions(-)
 create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci

Re: [Qemu-devel] [PULL 00/19] target-arm queue

[Peter Maydell]

On 26 April 2018 at 11:46, Peter Maydell  wrote:
> First arm pullreq of the 2.13 cycle!
>
> -- PMM
>
> The following changes since commit 4743c23509a51bd4ee85cc272287a41917d1be35:
>
>   Update version for v2.12.0 release (2018-04-24 16:44:55 +0100)
>
> are available in the Git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20180426
>
> for you to fetch changes up to fbf32752663878947de455ff57cb5b9318f14bec:
>
>   xilinx_spips: Correct SNOOP_NONE state when flushing the txfifo (2018-04-26 
> 11:04:40 +0100)
>

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 00/19] target-arm queue

[Peter Maydell]

First arm pullreq of the 2.13 cycle!

-- PMM

The following changes since commit 4743c23509a51bd4ee85cc272287a41917d1be35:

  Update version for v2.12.0 release (2018-04-24 16:44:55 +0100)

are available in the Git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20180426

for you to fetch changes up to fbf32752663878947de455ff57cb5b9318f14bec:

  xilinx_spips: Correct SNOOP_NONE state when flushing the txfifo (2018-04-26 
11:04:40 +0100)


target-arm queue:
 * xilinx_spips: Correct SNOOP_NONE state when flushing the txfifo
 * timer/aspeed: fix vmstate version id
 * hw/arm/aspeed_soc: don't use vmstate_register_ram_global for SRAM
 * hw/arm/aspeed: don't make 'boot_rom' region 'nomigrate'
 * hw/arm/highbank: don't make sysram 'nomigrate'
 * hw/arm/raspi: Don't bother setting default_cpu_type
 * PMU emulation: some minor bugfixes and preparation for
   support of other events than just the cycle counter
 * target/arm: Use v7m_stack_read() for reading the frame signature
 * target/arm: Remove stale TODO comment
 * arm: always start from first_cpu when registering loader cpu reset callback
 * device_tree: Increase FDT_MAX_SIZE to 1 MiB


Aaron Lindsay (9):
  target/arm: Check PMCNTEN for whether PMCCNTR is enabled
  target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0
  target/arm: Mask PMU register writes based on PMCR_EL0.N
  target/arm: Fetch GICv3 state directly from CPUARMState
  target/arm: Support multiple EL change hooks
  target/arm: Add pre-EL change hooks
  target/arm: Allow EL change hooks to do IO
  target/arm: Fix bitmask for PMCCFILTR writes
  target/arm: Make PMOVSCLR and PMUSERENR 64 bits wide

Cédric Le Goater (1):
  timer/aspeed: fix vmstate version id

Geert Uytterhoeven (1):
  device_tree: Increase FDT_MAX_SIZE to 1 MiB

Igor Mammedov (1):
  arm: always start from first_cpu when registering loader cpu reset 
callback

Peter Maydell (6):
  target/arm: Remove stale TODO comment
  target/arm: Use v7m_stack_read() for reading the frame signature
  hw/arm/raspi: Don't bother setting default_cpu_type
  hw/arm/highbank: don't make sysram 'nomigrate'
  hw/arm/aspeed: don't make 'boot_rom' region 'nomigrate'
  hw/arm/aspeed_soc: don't use vmstate_register_ram_global for SRAM

Sai Pavan Boddu (1):
  xilinx_spips: Correct SNOOP_NONE state when flushing the txfifo

 target/arm/cpu.h   | 48 +-
 target/arm/internals.h | 14 +++--
 device_tree.c  |  2 +-
 hw/arm/aspeed.c|  2 +-
 hw/arm/aspeed_soc.c|  3 +-
 hw/arm/boot.c  |  2 +-
 hw/arm/highbank.c  |  2 +-
 hw/arm/raspi.c |  2 --
 hw/intc/arm_gicv3_cpuif.c  | 10 ++-
 hw/ssi/xilinx_spips.c  |  3 +-
 hw/timer/aspeed_timer.c|  2 +-
 target/arm/cpu.c   | 37 +++
 target/arm/helper.c| 73 ++
 target/arm/op_helper.c |  8 +
 target/arm/translate-a64.c |  6 
 target/arm/translate.c | 12 
 16 files changed, 148 insertions(+), 78 deletions(-)

Re: [Qemu-devel] [PULL 00/19] target-arm queue

[Peter Maydell]

On 11 May 2015 at 14:40, Peter Maydell peter.mayd...@linaro.org wrote:
 This is mostly the GIC TZ changes, with a couple of other
 minor bugfixes.

 -- PMM

 The following changes since commit b951cda21d6b232f138ccf008e12bce8ddc95465:

   Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into 
 staging (2015-05-11 12:01:09 +0100)

 are available in the git repository at:


   git://git.linaro.org/people/pmaydell/qemu-arm.git 
 tags/pull-target-arm-20150511

 for you to fetch changes up to 49855cdaed78f66f501df6e18b8b3b7012cea2eb:

   hw/arm/highbank.c: Wire FIQ between CPU  GIC (2015-05-11 14:28:54 +0100)

Oops:

hw/intc/arm_gic_kvm.c: In function ‘kvm_arm_gic_put’:
hw/intc/arm_gic_kvm.c:357:12: error: ‘GICState’ has no member named ‘enabled’
hw/intc/arm_gic_kvm.c: In function ‘kvm_arm_gic_get’:
hw/intc/arm_gic_kvm.c:458:6: error: ‘GICState’ has no member named ‘enabled’

I could have sworn I'd tested that. Will fix  respin...

-- PMM

Re: [Qemu-devel] [PULL 00/19] target-arm queue

[Peter Crosthwaite]

On Tue, May 12, 2015 at 1:01 AM, Peter Maydell peter.mayd...@linaro.org wrote:
 On 11 May 2015 at 14:40, Peter Maydell peter.mayd...@linaro.org wrote:
 This is mostly the GIC TZ changes, with a couple of other
 minor bugfixes.

 -- PMM

 The following changes since commit b951cda21d6b232f138ccf008e12bce8ddc95465:

   Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into 
 staging (2015-05-11 12:01:09 +0100)

 are available in the git repository at:


   git://git.linaro.org/people/pmaydell/qemu-arm.git 
 tags/pull-target-arm-20150511

 for you to fetch changes up to 49855cdaed78f66f501df6e18b8b3b7012cea2eb:

   hw/arm/highbank.c: Wire FIQ between CPU  GIC (2015-05-11 14:28:54 +0100)

 Oops:

 hw/intc/arm_gic_kvm.c: In function ‘kvm_arm_gic_put’:
 hw/intc/arm_gic_kvm.c:357:12: error: ‘GICState’ has no member named ‘enabled’
 hw/intc/arm_gic_kvm.c: In function ‘kvm_arm_gic_get’:
 hw/intc/arm_gic_kvm.c:458:6: error: ‘GICState’ has no member named ‘enabled’

 I could have sworn I'd tested that. Will fix  respin...


Feel like grabbing the new Zynq series (v9) with it? :)

Regards,
Peter

 -- PMM

Re: [Qemu-devel] [PULL 00/19] target-arm queue

[Peter Maydell]

On 12 May 2015 at 09:10, Peter Crosthwaite peter.crosthwa...@xilinx.com wrote:
 On Tue, May 12, 2015 at 1:01 AM, Peter Maydell peter.mayd...@linaro.org 
 wrote:
 I could have sworn I'd tested that. Will fix  respin...


 Feel like grabbing the new Zynq series (v9) with it? :)

Maybe. I was going to except for that last minute issue in v8.
No real issue with doing two pullreqs, though; in some
ways that's better than one large one.

-- PMM

[Qemu-devel] [PULL 00/19] target-arm queue

[Peter Maydell]

v2 of the pull, fixing a silly compile failure on ARM hosts.
Diff is:

--- a/hw/intc/arm_gic_kvm.c
+++ b/hw/intc/arm_gic_kvm.c
@@ -353,8 +353,8 @@ static void kvm_arm_gic_put(GICState *s)
  * Distributor State
  */
 
-/* s-ctlr - GICD_CTLR */
-reg = s-ctlr;
+/* s-enabled - GICD_CTLR */
+reg = s-enabled;
 kvm_gicd_access(s, 0x0, 0, reg, true);
 
 /* Sanity checking on GICD_TYPER and s-num_irq, s-num_cpu */
@@ -453,9 +453,9 @@ static void kvm_arm_gic_get(GICState *s)
  * Distributor State
  */
 
-/* GICD_CTLR - s-ctlr */
+/* GICD_CTLR - s-enabled */
 kvm_gicd_access(s, 0x0, 0, reg, false);
-s-ctlr = reg;
+s-enabled = reg  1;
 
 /* Sanity checking on GICD_TYPER - s-num_irq, s-num_cpu */
 kvm_gicd_access(s, 0x4, 0, reg, false);

so I'm not going to resend all the patches, just this cover letter.

-- PMM

The following changes since commit 19fbe5084c1da6af95177c86e4cab64241d479a8:

  Merge remote-tracking branch 'remotes/stefanha/tags/net-pull-request' into 
staging (2015-05-12 10:40:31 +0100)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20150512

for you to fetch changes up to 5ae79fe825bedc89db8b6bde9d0ed0bb5d59558c:

  hw/arm/highbank.c: Wire FIQ between CPU  GIC (2015-05-12 11:57:19 +0100)


target-arm queue:
 * Support TZ and grouping in the GIC
 * hw/sd: sd_reset cleanup
 * armv7m_nvic: fix bug in systick device


Adrian Huang (1):
  armv7m_nvic: systick: Reload the RELOAD value and count down only if 
ENABLE bit is set

Fabian Aggeler (12):
  hw/intc/arm_gic: Create outbound FIQ lines
  hw/intc/arm_gic: Add Security Extensions property
  hw/intc/arm_gic: Add Interrupt Group Registers
  hw/intc/arm_gic: Make ICDDCR/GICD_CTLR banked
  hw/intc/arm_gic: Make ICCBPR/GICC_BPR banked
  hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked
  hw/intc/arm_gic: Implement Non-secure view of RPR
  hw/intc/arm_gic: Restrict priority view
  hw/intc/arm_gic: Handle grouping for GICC_HPPIR
  hw/intc/arm_gic: Change behavior of EOIR writes
  hw/intc/arm_gic: Change behavior of IAR writes
  hw/arm/vexpress.c: Wire FIQ between CPU  GIC

Greg Bellows (1):
  hw/arm/virt.c: Wire FIQ between CPU  GIC

Peter Maydell (5):
  hw/sd: Don't pass BlockBackend to sd_reset()
  hw/intc/arm_gic: Switch to read/write callbacks with tx attributes
  hw/intc/arm_gic_kvm.c: Save and restore GICD_IGROUPRn state
  hw/intc/arm_gic: Add grouping support to gic_update()
  hw/arm/highbank.c: Wire FIQ between CPU  GIC

 hw/arm/highbank.c|   3 +
 hw/arm/vexpress.c|   2 +
 hw/arm/virt.c|   2 +
 hw/intc/arm_gic.c| 469 ---
 hw/intc/arm_gic_common.c |  22 +-
 hw/intc/arm_gic_kvm.c|  59 +++--
 hw/intc/armv7m_nvic.c|  17 +-
 hw/intc/gic_internal.h   |  29 ++-
 hw/sd/sd.c   |  17 +-
 include/hw/intc/arm_gic_common.h |  24 +-
 10 files changed, 513 insertions(+), 131 deletions(-)

Re: [Qemu-devel] [PULL 00/19] target-arm queue

[Peter Maydell]

On 12 May 2015 at 12:03, Peter Maydell peter.mayd...@linaro.org wrote:

 v2 of the pull, fixing a silly compile failure on ARM hosts.
 
 target-arm queue:
  * Support TZ and grouping in the GIC
  * hw/sd: sd_reset cleanup
  * armv7m_nvic: fix bug in systick device

 

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 00/19] target-arm queue

[Peter Maydell]

This is mostly the GIC TZ changes, with a couple of other
minor bugfixes.

-- PMM

The following changes since commit b951cda21d6b232f138ccf008e12bce8ddc95465:

  Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging 
(2015-05-11 12:01:09 +0100)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20150511

for you to fetch changes up to 49855cdaed78f66f501df6e18b8b3b7012cea2eb:

  hw/arm/highbank.c: Wire FIQ between CPU  GIC (2015-05-11 14:28:54 +0100)


target-arm queue:
 * Support TZ and grouping in the GIC
 * hw/sd: sd_reset cleanup
 * armv7m_nvic: fix bug in systick device


Adrian Huang (1):
  armv7m_nvic: systick: Reload the RELOAD value and count down only if 
ENABLE bit is set

Fabian Aggeler (12):
  hw/intc/arm_gic: Create outbound FIQ lines
  hw/intc/arm_gic: Add Security Extensions property
  hw/intc/arm_gic: Add Interrupt Group Registers
  hw/intc/arm_gic: Make ICDDCR/GICD_CTLR banked
  hw/intc/arm_gic: Make ICCBPR/GICC_BPR banked
  hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked
  hw/intc/arm_gic: Implement Non-secure view of RPR
  hw/intc/arm_gic: Restrict priority view
  hw/intc/arm_gic: Handle grouping for GICC_HPPIR
  hw/intc/arm_gic: Change behavior of EOIR writes
  hw/intc/arm_gic: Change behavior of IAR writes
  hw/arm/vexpress.c: Wire FIQ between CPU  GIC

Greg Bellows (1):
  hw/arm/virt.c: Wire FIQ between CPU  GIC

Peter Maydell (5):
  hw/sd: Don't pass BlockBackend to sd_reset()
  hw/intc/arm_gic: Switch to read/write callbacks with tx attributes
  hw/intc/arm_gic_kvm.c: Save and restore GICD_IGROUPRn state
  hw/intc/arm_gic: Add grouping support to gic_update()
  hw/arm/highbank.c: Wire FIQ between CPU  GIC

 hw/arm/highbank.c|   3 +
 hw/arm/vexpress.c|   2 +
 hw/arm/virt.c|   2 +
 hw/intc/arm_gic.c| 469 ---
 hw/intc/arm_gic_common.c |  22 +-
 hw/intc/arm_gic_kvm.c|  51 +++--
 hw/intc/armv7m_nvic.c|  17 +-
 hw/intc/gic_internal.h   |  29 ++-
 hw/sd/sd.c   |  17 +-
 include/hw/intc/arm_gic_common.h |  24 +-
 10 files changed, 509 insertions(+), 127 deletions(-)

Re: [Qemu-devel] [PULL 00/19] target-arm queue

[Peter Maydell]

On 29 September 2014 19:26, Peter Maydell peter.mayd...@linaro.org wrote:
 ARM pullreq: nothing fantastically exciting, but getting the
 EL2/EL3 patchset in ought to help with ongoing TZ work.

 -- PMM


 The following changes since commit 70556264a89a268efba1d7e8e341adcdd7881eb4:

   libqos: use microseconds instead of iterations for virtio timeout 
 (2014-09-29 17:31:11 +0100)

 are available in the git repository at:

   git://git.linaro.org/people/pmaydell/qemu-arm.git 
 tags/pull-target-arm-20140929

 for you to fetch changes up to 136e67e9b50b61fb03fedcea5c4fbe74cf44fdcc:

   target-arm: Add support for VIRQ and VFIQ (2014-09-29 18:48:51 +0100)

 
 target-arm:
  * more EL2/EL3 preparation work
  * don't handle c15_cpar changes via tb_flush()
  * fix some unused function warnings in ARM devices
  * build the GDB XML for 32 bit CPUs into qemu-*-aarch64
  * implement guest breakpoint support

 

Applied, thanks.

-- PMM

Re: [Qemu-devel] [PULL 00/19] target-arm queue

[Peter Maydell]

On 19 August 2014 19:09, Peter Maydell peter.mayd...@linaro.org wrote:
 Flushing my queue of reviewed ARM patches: single step,
 plus a collection of straightforward patches from other
 people.

 thanks
 -- PMM


 The following changes since commit 0e4a77370594c91dd126f9872893ed473374cc72:

   Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into 
 staging (2014-08-19 13:00:57 +0100)

 are available in the git repository at:


   git://git.linaro.org/people/pmaydell/qemu-arm.git 
 tags/pull-target-arm-20140819

 for you to fetch changes up to 14a906f755f77b325666d67e071c572478d06067:

   arm: stellaris: Remove misleading address_space_mem var (2014-08-19 
 19:02:40 +0100)

 
 target-arm:
  * fix preferred return address for A64 BRK insn
  * implement AArch64 single-stepping
  * support loading gzip compressed AArch64 kernels
  * use correct PSCI function IDs in the DT when KVM uses PSCI 0.2
  * minor cleanups

 
 Christoffer Dall (2):
   target-arm: Rename QEMU PSCI v0.1 definitions
   arm/virt: Use PSCI v0.2 function IDs in the DT when KVM uses PSCI v0.2

 Peter Crosthwaite (3):
   arm: cortex-a9: Fix cache-line size and associativity
   arm: armv7m: Rename address_space_mem - system_memory
   arm: stellaris: Remove misleading address_space_mem var

 Peter Maydell (12):
   target-arm: Fix return address for A64 BRK instructions
   target-arm: Collect up the debug cp register definitions
   target-arm: Allow STATE_BOTH reginfo descriptions for more than cp14
   target-arm: Provide both 32 and 64 bit versions of debug registers
   target-arm: Adjust debug ID registers per-CPU
   target-arm: Don't allow AArch32 to access RES0 CPSR bits
   target-arm: Correctly handle PSTATE.SS when taking exception to AArch32
   target-arm: Set PSTATE.SS correctly on exception return from AArch64
   target-arm: A64: Avoid duplicate exit_tb(0) in non-linked goto_tb
   target-arm: Implement ARMv8 single-step handling for A64 code
   target-arm: Implement ARMv8 single-stepping for AArch32 code
   target-arm: Implement MDSCR_EL1 as having state

 Richard W.M. Jones (2):
   loader: Add load_image_gzipped function.
   aarch64: Allow -kernel option to take a gzip-compressed kernel.

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 00/19] target-arm queue

[Peter Maydell]

Flushing my queue of reviewed ARM patches: single step,
plus a collection of straightforward patches from other
people.

thanks
-- PMM


The following changes since commit 0e4a77370594c91dd126f9872893ed473374cc72:

  Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging 
(2014-08-19 13:00:57 +0100)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20140819

for you to fetch changes up to 14a906f755f77b325666d67e071c572478d06067:

  arm: stellaris: Remove misleading address_space_mem var (2014-08-19 19:02:40 
+0100)


target-arm:
 * fix preferred return address for A64 BRK insn
 * implement AArch64 single-stepping
 * support loading gzip compressed AArch64 kernels
 * use correct PSCI function IDs in the DT when KVM uses PSCI 0.2
 * minor cleanups


Christoffer Dall (2):
  target-arm: Rename QEMU PSCI v0.1 definitions
  arm/virt: Use PSCI v0.2 function IDs in the DT when KVM uses PSCI v0.2

Peter Crosthwaite (3):
  arm: cortex-a9: Fix cache-line size and associativity
  arm: armv7m: Rename address_space_mem - system_memory
  arm: stellaris: Remove misleading address_space_mem var

Peter Maydell (12):
  target-arm: Fix return address for A64 BRK instructions
  target-arm: Collect up the debug cp register definitions
  target-arm: Allow STATE_BOTH reginfo descriptions for more than cp14
  target-arm: Provide both 32 and 64 bit versions of debug registers
  target-arm: Adjust debug ID registers per-CPU
  target-arm: Don't allow AArch32 to access RES0 CPSR bits
  target-arm: Correctly handle PSTATE.SS when taking exception to AArch32
  target-arm: Set PSTATE.SS correctly on exception return from AArch64
  target-arm: A64: Avoid duplicate exit_tb(0) in non-linked goto_tb
  target-arm: Implement ARMv8 single-step handling for A64 code
  target-arm: Implement ARMv8 single-stepping for AArch32 code
  target-arm: Implement MDSCR_EL1 as having state

Richard W.M. Jones (2):
  loader: Add load_image_gzipped function.
  aarch64: Allow -kernel option to take a gzip-compressed kernel.

 hw/arm/armv7m.c|   8 +--
 hw/arm/boot.c  |   7 +++
 hw/arm/stellaris.c |   3 +-
 hw/arm/virt.c  |  31 --
 hw/core/loader.c   |  48 +++
 include/hw/arm/arm.h   |   2 +-
 include/hw/loader.h|   1 +
 target-arm/cpu-qom.h   |   1 +
 target-arm/cpu.c   |   7 ++-
 target-arm/cpu.h   | 115 ++-
 target-arm/cpu64.c |   1 +
 target-arm/helper.c| 145 +++--
 target-arm/helper.h|   1 +
 target-arm/internals.h |   6 ++
 target-arm/kvm-consts.h|  49 +++
 target-arm/op_helper.c |  27 -
 target-arm/translate-a64.c |  98 +++---
 target-arm/translate.c |  89 +---
 target-arm/translate.h |  12 
 19 files changed, 563 insertions(+), 88 deletions(-)

[Qemu-devel] [PULL 00/19] target-arm queue

[Peter Maydell]

Whoops. Resend of previous pull but with the PD0/PD1 patch dropped.
I haven't re-transmitted the individual patchmails.

The following changes since commit 4a331bb33bdf112ba95470e5d6ea3561b049c280:

  Merge remote-tracking branch 'remotes/stefanha/tags/net-pull-request' into 
staging (2014-06-09 15:00:21 +0100)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20140609-1

for you to fetch changes up to 3b1a41381254f6080b5cfeb149c28a9237d42a0b:

  target-arm: Delete unused iwmmxt_msadb helper (2014-06-09 16:06:12 +0100)



target-arm queue:
 * support -bios option in vexpress boards
 * register the Cortex-A57 impdef system registers
 * fix handling of UXN bit in ARMv8 page tables
 * complete support of crypto insns in A32/T32
 * implement CRC and crypto insns in A64
 * fix bugs in generic timer control register




Ard Biesheuvel (1):
  target-arm: add support for v8 SHA1 and SHA256 instructions

Fabian Aggeler (1):
  target-arm: Prepare cpreg writefns/readfns for EL3/SecExt

Grant Likely (1):
  vexpress: Add support for the -bios flag to provide firmware

Ian Campbell (1):
  target-arm: Correct handling of UXN bit in ARMv8 LPAE page tables

Peter Maydell (15):
  target-arm/cpu64.c: Actually register Cortex-A57 impdef registers
  target-arm: Allow 3reg_wide undefreq to encode more bad size options
  target-arm: add support for v8 VMULL.P64 instruction
  target-arm: A64: Use PMULL feature bit for PMULL
  target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64
  target-arm: Remove unnecessary setting of feature bits
  target-arm: Clean up handling of ARMv8 optional feature bits
  target-arm: VFPv4 implies half-precision extension
  target-arm: A64: Implement CRC instructions
  target-arm: A32/T32: Mask CRC value in calling code, not helper
  target-arm: A64: Implement AES instructions
  target-arm: A64: Implement 3-register SHA instructions
  target-arm: A64: Implement two-register SHA instructions
  target-arm: Fix errors in writes to generic timer control registers
  target-arm: Delete unused iwmmxt_msadb helper

 hw/arm/vexpress.c  |  13 +++
 linux-user/elfload.c   |   9 +-
 target-arm/cpu.c   |  13 +--
 target-arm/cpu.h   |   3 +
 target-arm/cpu64.c |  15 ++-
 target-arm/crypto_helper.c | 257 +++--
 target-arm/helper-a64.c|  60 +--
 target-arm/helper-a64.h|   4 +-
 target-arm/helper.c|  76 ++
 target-arm/helper.h|  14 ++-
 target-arm/iwmmxt_helper.c |   9 --
 target-arm/neon_helper.c   |  30 ++
 target-arm/translate-a64.c | 211 -
 target-arm/translate.c | 144 ++---
 14 files changed, 731 insertions(+), 127 deletions(-)

Re: [Qemu-devel] [PULL 00/19] target-arm queue

[Peter Maydell]

On 9 June 2014 16:10, Peter Maydell peter.mayd...@linaro.org wrote:
 Whoops. Resend of previous pull but with the PD0/PD1 patch dropped.
 I haven't re-transmitted the individual patchmails.

 The following changes since commit 4a331bb33bdf112ba95470e5d6ea3561b049c280:

   Merge remote-tracking branch 'remotes/stefanha/tags/net-pull-request' into 
 staging (2014-06-09 15:00:21 +0100)

 are available in the git repository at:


   git://git.linaro.org/people/pmaydell/qemu-arm.git 
 tags/pull-target-arm-20140609-1

 for you to fetch changes up to 3b1a41381254f6080b5cfeb149c28a9237d42a0b:

   target-arm: Delete unused iwmmxt_msadb helper (2014-06-09 16:06:12 +0100)

 
 
 target-arm queue:
  * support -bios option in vexpress boards
  * register the Cortex-A57 impdef system registers
  * fix handling of UXN bit in ARMv8 page tables
  * complete support of crypto insns in A32/T32
  * implement CRC and crypto insns in A64
  * fix bugs in generic timer control register

Applied this version; thanks.

-- PMM