[Qemu-devel] [PULL 24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
From: Bastian Koppelmann
manual decoding in gen_arith() is not necessary with decodetree. For now
the function is called trans_arith as the original gen_arith still
exists. The former will be renamed to gen_arith as soon as the old
gen_arith can be removed.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 3 +-
target/riscv/insn_trans/trans_rvi.inc.c | 21 +
target/riscv/translate.c| 40 +++--
3 files changed, 34 insertions(+), 30 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index d6b4197841f5..6f3ab7aa52d3 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -36,11 +36,12 @@
# Argument sets:
&bimm rs2 rs1
&iimm rs1 rd
+&rrd rs1 rs2
&shift shamt rs1 rd
&atomicaq rl rs2 rs1 rd
# Formats 32:
-@r ... . . ... . ... %rs2 %rs1
%rd
+@r ... . . ... . ... &r%rs2 %rs1
%rd
@i . ... . ... &i imm=%imm_i %rs1
%rd
@b ... . . ... . ... &b imm=%imm_b %rs2 %rs1
@s ... . . ... . ... imm=%imm_s %rs2 %rs1
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c
b/target/riscv/insn_trans/trans_rvi.inc.c
index 0265740bdb69..8879f2da35c7 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -312,14 +312,12 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a)
static bool trans_add(DisasContext *ctx, arg_add *a)
{
-gen_arith(ctx, OPC_RISC_ADD, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &tcg_gen_add_tl);
}
static bool trans_sub(DisasContext *ctx, arg_sub *a)
{
-gen_arith(ctx, OPC_RISC_SUB, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &tcg_gen_sub_tl);
}
static bool trans_sll(DisasContext *ctx, arg_sll *a)
@@ -342,8 +340,7 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
static bool trans_xor(DisasContext *ctx, arg_xor *a)
{
-gen_arith(ctx, OPC_RISC_XOR, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &tcg_gen_xor_tl);
}
static bool trans_srl(DisasContext *ctx, arg_srl *a)
@@ -360,14 +357,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a)
static bool trans_or(DisasContext *ctx, arg_or *a)
{
-gen_arith(ctx, OPC_RISC_OR, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &tcg_gen_or_tl);
}
static bool trans_and(DisasContext *ctx, arg_and *a)
{
-gen_arith(ctx, OPC_RISC_AND, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &tcg_gen_and_tl);
}
#ifdef TARGET_RISCV64
@@ -414,14 +409,12 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
static bool trans_addw(DisasContext *ctx, arg_addw *a)
{
-gen_arith(ctx, OPC_RISC_ADDW, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &gen_addw);
}
static bool trans_subw(DisasContext *ctx, arg_subw *a)
{
-gen_arith(ctx, OPC_RISC_SUBW, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &gen_subw);
}
static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 0157758a160a..8eb883463322 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -198,12 +198,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int
rd, int rs1,
gen_get_gpr(source2, rs2);
switch (opc) {
-CASE_OP_32_64(OPC_RISC_ADD):
-tcg_gen_add_tl(source1, source1, source2);
-break;
-CASE_OP_32_64(OPC_RISC_SUB):
-tcg_gen_sub_tl(source1, source1, source2);
-break;
#if defined(TARGET_RISCV64)
case OPC_RISC_SLLW:
tcg_gen_andi_tl(source2, source2, 0x1F);
@@ -220,9 +214,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int
rd, int rs1,
case OPC_RISC_SLTU:
tcg_gen_setcond_tl(TCG_COND_LTU, source1, source1, source2);
break;
-case OPC_RISC_XOR:
-tcg_gen_xor_tl(source1, source1, source2);
-break;
#if defined(TARGET_RISCV64)
case OPC_RISC_SRLW:
/* clear upper 32 */
@@ -248,12 +239,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int
rd, int rs1,
tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
tcg_gen_sar_tl(source1, source1, source2);
break;
-case OPC_RISC_OR:
-tcg_gen_or_tl(source1, source1, source2);
-break;
-case OPC_RISC_AND:
-tcg_gen_and_tl(source1, source1, source2);
-break;
CASE_OP_32_64(OPC_RISC_MUL):
if (!has_ext(ctx, RVM)) {
goto do_illegal;
@@ -730,8 +715,33 @@ static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
tcg_gen_add_tl(ret, arg1, arg2);
[Qemu-devel] [PULL 24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
From: Bastian Koppelmann
manual decoding in gen_arith() is not necessary with decodetree. For now
the function is called trans_arith as the original gen_arith still
exists. The former will be renamed to gen_arith as soon as the old
gen_arith can be removed.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 3 +-
target/riscv/insn_trans/trans_rvi.inc.c | 21 +
target/riscv/translate.c| 40 +++--
3 files changed, 34 insertions(+), 30 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index d6b4197841f5..6f3ab7aa52d3 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -36,11 +36,12 @@
# Argument sets:
&bimm rs2 rs1
&iimm rs1 rd
+&rrd rs1 rs2
&shift shamt rs1 rd
&atomicaq rl rs2 rs1 rd
# Formats 32:
-@r ... . . ... . ... %rs2 %rs1
%rd
+@r ... . . ... . ... &r%rs2 %rs1
%rd
@i . ... . ... &i imm=%imm_i %rs1
%rd
@b ... . . ... . ... &b imm=%imm_b %rs2 %rs1
@s ... . . ... . ... imm=%imm_s %rs2 %rs1
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c
b/target/riscv/insn_trans/trans_rvi.inc.c
index 0265740bdb69..8879f2da35c7 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -312,14 +312,12 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a)
static bool trans_add(DisasContext *ctx, arg_add *a)
{
-gen_arith(ctx, OPC_RISC_ADD, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &tcg_gen_add_tl);
}
static bool trans_sub(DisasContext *ctx, arg_sub *a)
{
-gen_arith(ctx, OPC_RISC_SUB, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &tcg_gen_sub_tl);
}
static bool trans_sll(DisasContext *ctx, arg_sll *a)
@@ -342,8 +340,7 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
static bool trans_xor(DisasContext *ctx, arg_xor *a)
{
-gen_arith(ctx, OPC_RISC_XOR, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &tcg_gen_xor_tl);
}
static bool trans_srl(DisasContext *ctx, arg_srl *a)
@@ -360,14 +357,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a)
static bool trans_or(DisasContext *ctx, arg_or *a)
{
-gen_arith(ctx, OPC_RISC_OR, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &tcg_gen_or_tl);
}
static bool trans_and(DisasContext *ctx, arg_and *a)
{
-gen_arith(ctx, OPC_RISC_AND, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &tcg_gen_and_tl);
}
#ifdef TARGET_RISCV64
@@ -414,14 +409,12 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
static bool trans_addw(DisasContext *ctx, arg_addw *a)
{
-gen_arith(ctx, OPC_RISC_ADDW, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &gen_addw);
}
static bool trans_subw(DisasContext *ctx, arg_subw *a)
{
-gen_arith(ctx, OPC_RISC_SUBW, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &gen_subw);
}
static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 0157758a160a..8eb883463322 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -198,12 +198,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int
rd, int rs1,
gen_get_gpr(source2, rs2);
switch (opc) {
-CASE_OP_32_64(OPC_RISC_ADD):
-tcg_gen_add_tl(source1, source1, source2);
-break;
-CASE_OP_32_64(OPC_RISC_SUB):
-tcg_gen_sub_tl(source1, source1, source2);
-break;
#if defined(TARGET_RISCV64)
case OPC_RISC_SLLW:
tcg_gen_andi_tl(source2, source2, 0x1F);
@@ -220,9 +214,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int
rd, int rs1,
case OPC_RISC_SLTU:
tcg_gen_setcond_tl(TCG_COND_LTU, source1, source1, source2);
break;
-case OPC_RISC_XOR:
-tcg_gen_xor_tl(source1, source1, source2);
-break;
#if defined(TARGET_RISCV64)
case OPC_RISC_SRLW:
/* clear upper 32 */
@@ -248,12 +239,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int
rd, int rs1,
tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
tcg_gen_sar_tl(source1, source1, source2);
break;
-case OPC_RISC_OR:
-tcg_gen_or_tl(source1, source1, source2);
-break;
-case OPC_RISC_AND:
-tcg_gen_and_tl(source1, source1, source2);
-break;
CASE_OP_32_64(OPC_RISC_MUL):
if (!has_ext(ctx, RVM)) {
goto do_illegal;
@@ -730,8 +715,33 @@ static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
tcg
