On Tue, 2018-01-09 at 09:19 -0200, Murilo Opsfelder Araújo wrote:
> On 01/09/2018 07:21 AM, Suraj Jitindar Singh wrote:
> > The new H-Call H_GET_CPU_CHARACTERISTICS is used by the guest to
> > query
> > behaviours and available characteristics of the cpu.
> >
> > Implement the handler for this new H-Call which formulates its
> > response
> > based on the setting of the new capabilities added in the previous
> > patch.
> >
> > Note: Currently we return H_FUNCTION under TCG which will direct
> > the
> > guest to fall back to doing a displacement flush
> >
> > Discussion:
> > Is TCG affected?
> > Is there any point in telling the guest to do these workarounds on
> > TCG
> > given they're unlikely to translate to host instructions which have
> > the
> > desired effect?
>
> Hi, Suraj.
>
> What if this is left to the cover letter?
Again, only because this is RFC.
>
> > ---
> > hw/ppc/spapr_hcall.c | 81
> > ++
> > include/hw/ppc/spapr.h | 1 +
> > 2 files changed, 82 insertions(+)
> >
> > diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
> > index 51eba52e86..b62b47c8d9 100644
> > --- a/hw/ppc/spapr_hcall.c
> > +++ b/hw/ppc/spapr_hcall.c
> > @@ -1654,6 +1654,84 @@ static target_ulong
> > h_client_architecture_support(PowerPCCPU *cpu,
> > return H_SUCCESS;
> > }
> >
> > +#define CPU_CHARACTERISTIC_SPEC_BARRIER (1ULL << (63 - 0))
> > +#define CPU_CHARACTERISTIC_BCCTR_SERIAL (1ULL << (63 - 1))
> > +#define CPU_CHARACTERISTIC_ORI_L1_CACHE (1ULL << (63 - 2))
> > +#define CPU_CHARACTERISTIC_MTTRIG_L1_CACHE (1ULL << (63 - 3))
> > +#define CPU_CHARACTERISTIC_L1_CACHE_PRIV(1ULL << (63 - 4))
> > +#define CPU_CHARACTERISTIC_BRANCH_HINTS (1ULL << (63 - 5))
> > +#define CPU_CHARACTERISTIC_MTTRIG_THR_RECONF(1ULL << (63 - 6))
> > +#define CPU_BEHAVIOUR_FAVOUR_SECURITY (1ULL << (63 - 0))
> > +#define CPU_BEHAVIOUR_L1_CACHE_FLUSH(1ULL << (63 - 1))
> > +#define CPU_BEHAVIOUR_SPEC_BARRIER (1ULL << (63 - 2))
>
> Can PPC_BIT be used here?
Yep, will do
>
> Cheers
> Murilo
>
