[Qemu-devel] [Qemu devel v8 PATCH 3/5] msf2: Add Smartfusion2 SPI controller
Modelled Microsemi's Smartfusion2 SPI controller. Signed-off-by: Subbaraya Sundeep --- hw/ssi/Makefile.objs | 1 + hw/ssi/mss-spi.c | 404 +++ include/hw/ssi/mss-spi.h | 58 +++ 3 files changed, 463 insertions(+) create mode 100644 hw/ssi/mss-spi.c create mode 100644 include/hw/ssi/mss-spi.h diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs index 487add2..f5bcc65 100644 --- a/hw/ssi/Makefile.objs +++ b/hw/ssi/Makefile.objs @@ -4,6 +4,7 @@ common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o +common-obj-$(CONFIG_MSF2) += mss-spi.o obj-$(CONFIG_OMAP) += omap_spi.o obj-$(CONFIG_IMX) += imx_spi.o diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c new file mode 100644 index 000..5a8e308 --- /dev/null +++ b/hw/ssi/mss-spi.c @@ -0,0 +1,404 @@ +/* + * Block model of SPI controller present in + * Microsemi's SmartFusion2 and SmartFusion SoCs. + * + * Copyright (C) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/ssi/mss-spi.h" +#include "qemu/log.h" + +#ifndef MSS_SPI_ERR_DEBUG +#define MSS_SPI_ERR_DEBUG 0 +#endif + +#define DB_PRINT_L(lvl, fmt, args...) do { \ +if (MSS_SPI_ERR_DEBUG >= lvl) { \ +qemu_log("%s: " fmt "\n", __func__, ## args); \ +} \ +} while (0); + +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) + +#define FIFO_CAPACITY 32 + +#define R_SPI_CONTROL 0 +#define R_SPI_DFSIZE 1 +#define R_SPI_STATUS 2 +#define R_SPI_INTCLR 3 +#define R_SPI_RX 4 +#define R_SPI_TX 5 +#define R_SPI_CLKGEN 6 +#define R_SPI_SS 7 +#define R_SPI_MIS 8 +#define R_SPI_RIS 9 + +#define S_TXDONE (1 << 0) +#define S_RXRDY (1 << 1) +#define S_RXCHOVRF (1 << 2) +#define S_RXFIFOFUL (1 << 4) +#define S_RXFIFOFULNXT (1 << 5) +#define S_RXFIFOEMP (1 << 6) +#define S_RXFIFOEMPNXT (1 << 7) +#define S_TXFIFOFUL (1 << 8) +#define S_TXFIFOFULNXT (1 << 9) +#define S_TXFIFOEMP (1 << 10) +#define S_TXFIFOEMPNXT (1 << 11) +#define S_FRAMESTART (1 << 12) +#define S_SSEL (1 << 13) +#define S_ACTIVE (1 << 14) + +#define C_ENABLE (1 << 0) +#define C_MODE (1 << 1) +#define C_INTRXDATA (1 << 4) +#define C_INTTXDATA (1 << 5) +#define C_INTRXOVRFLO(1 << 6) +#define C_SPS(1 << 26) +#define C_BIGFIFO(1 << 29) +#define C_RESET (1 << 31) + +#define FRAMESZ_MASK 0x1F +#define FMCOUNT_MASK 0x0000 +#define FMCOUNT_SHIFT8 + +static void txfifo_reset(MSSSpiState *s) +{ +fifo32_reset(&s->tx_fifo); + +s->regs[R_SPI_STATUS] &= ~S_TXFIFOFUL; +s->regs[R_SPI_STATUS] |= S_TXFIFOEMP; +} + +static void rxfifo_reset(MSSSpiState *s) +{ +fifo32_reset(&s->rx_fifo); + +s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL; +s->regs[R_SPI_STATUS] |= S_RXFIFOEMP; +} + +static void set_fifodepth(MSSSpiState *s) +{ +unsigned int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK; + +if (size <= 8) { +s->fifo_depth = 32; +} else if (size <= 16) { +s->fifo_depth = 16; +} else if (size <= 32) { +s->fifo_depth = 8; +} else { +s->fifo_depth = 4; +} +} + +static void update_mis(MSSSpiState *s) +{ +uint32_t reg = s->regs[R_SPI_CONTROL]; +uint32_t tmp; + +/* + * form the Control register interrupt enable bits + * same as RIS, MIS and Interrupt clear registers for simplicity + */ +tmp = ((reg & C_INTRXOVRFLO) >> 4) | ((reg & C_INTRXDATA) >> 3) | + ((reg & C_INTTXDATA) >> 5); +s->re
Re: [Qemu-devel] [Qemu devel v8 PATCH 3/5] msf2: Add Smartfusion2 SPI controller
On Thu, Sep 7, 2017 at 12:24 PM, Subbaraya Sundeep wrote: > Modelled Microsemi's Smartfusion2 SPI controller. > > Signed-off-by: Subbaraya Sundeep Reviewed-by: Alistair Francis Thanks, Alistair > --- > hw/ssi/Makefile.objs | 1 + > hw/ssi/mss-spi.c | 404 > +++ > include/hw/ssi/mss-spi.h | 58 +++ > 3 files changed, 463 insertions(+) > create mode 100644 hw/ssi/mss-spi.c > create mode 100644 include/hw/ssi/mss-spi.h > > diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs > index 487add2..f5bcc65 100644 > --- a/hw/ssi/Makefile.objs > +++ b/hw/ssi/Makefile.objs > @@ -4,6 +4,7 @@ common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o > common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o > common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o > common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o > +common-obj-$(CONFIG_MSF2) += mss-spi.o > > obj-$(CONFIG_OMAP) += omap_spi.o > obj-$(CONFIG_IMX) += imx_spi.o > diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c > new file mode 100644 > index 000..5a8e308 > --- /dev/null > +++ b/hw/ssi/mss-spi.c > @@ -0,0 +1,404 @@ > +/* > + * Block model of SPI controller present in > + * Microsemi's SmartFusion2 and SmartFusion SoCs. > + * > + * Copyright (C) 2017 Subbaraya Sundeep > + * > + * Permission is hereby granted, free of charge, to any person obtaining a > copy > + * of this software and associated documentation files (the "Software"), to > deal > + * in the Software without restriction, including without limitation the > rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > + * THE SOFTWARE. > + */ > + > +#include "qemu/osdep.h" > +#include "hw/ssi/mss-spi.h" > +#include "qemu/log.h" > + > +#ifndef MSS_SPI_ERR_DEBUG > +#define MSS_SPI_ERR_DEBUG 0 > +#endif > + > +#define DB_PRINT_L(lvl, fmt, args...) do { \ > +if (MSS_SPI_ERR_DEBUG >= lvl) { \ > +qemu_log("%s: " fmt "\n", __func__, ## args); \ > +} \ > +} while (0); > + > +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) > + > +#define FIFO_CAPACITY 32 > + > +#define R_SPI_CONTROL 0 > +#define R_SPI_DFSIZE 1 > +#define R_SPI_STATUS 2 > +#define R_SPI_INTCLR 3 > +#define R_SPI_RX 4 > +#define R_SPI_TX 5 > +#define R_SPI_CLKGEN 6 > +#define R_SPI_SS 7 > +#define R_SPI_MIS 8 > +#define R_SPI_RIS 9 > + > +#define S_TXDONE (1 << 0) > +#define S_RXRDY (1 << 1) > +#define S_RXCHOVRF (1 << 2) > +#define S_RXFIFOFUL (1 << 4) > +#define S_RXFIFOFULNXT (1 << 5) > +#define S_RXFIFOEMP (1 << 6) > +#define S_RXFIFOEMPNXT (1 << 7) > +#define S_TXFIFOFUL (1 << 8) > +#define S_TXFIFOFULNXT (1 << 9) > +#define S_TXFIFOEMP (1 << 10) > +#define S_TXFIFOEMPNXT (1 << 11) > +#define S_FRAMESTART (1 << 12) > +#define S_SSEL (1 << 13) > +#define S_ACTIVE (1 << 14) > + > +#define C_ENABLE (1 << 0) > +#define C_MODE (1 << 1) > +#define C_INTRXDATA (1 << 4) > +#define C_INTTXDATA (1 << 5) > +#define C_INTRXOVRFLO(1 << 6) > +#define C_SPS(1 << 26) > +#define C_BIGFIFO(1 << 29) > +#define C_RESET (1 << 31) > + > +#define FRAMESZ_MASK 0x1F > +#define FMCOUNT_MASK 0x0000 > +#define FMCOUNT_SHIFT8 > + > +static void txfifo_reset(MSSSpiState *s) > +{ > +fifo32_reset(&s->tx_fifo); > + > +s->regs[R_SPI_STATUS] &= ~S_TXFIFOFUL; > +s->regs[R_SPI_STATUS] |= S_TXFIFOEMP; > +} > + > +static void rxfifo_reset(MSSSpiState *s) > +{ > +fifo32_reset(&s->rx_fifo); > + > +s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL; > +s->regs[R_SPI_STATUS] |= S_RXFIFOEMP; > +} > + > +static void set_fifodepth(MSSSpiState *s) > +{ > +unsigned int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK; > + > +if (size <= 8) { > +s->fifo_depth = 32; > +} else if (size <= 16) { > +s->fifo_depth = 16; > +} else if (size <= 32) { > +s->fifo_depth = 8; > +} else { > +s->fif
Re: [Qemu-devel] [Qemu devel v8 PATCH 3/5] msf2: Add Smartfusion2 SPI controller
Hi Alistair, On Wed, Sep 13, 2017 at 5:20 AM, Alistair Francis wrote: > On Thu, Sep 7, 2017 at 12:24 PM, Subbaraya Sundeep > wrote: > > Modelled Microsemi's Smartfusion2 SPI controller. > > > > Signed-off-by: Subbaraya Sundeep > > Reviewed-by: Alistair Francis > > Thank you, Sundeep > Thanks, > Alistair > > > --- > > hw/ssi/Makefile.objs | 1 + > > hw/ssi/mss-spi.c | 404 ++ > + > > include/hw/ssi/mss-spi.h | 58 +++ > > 3 files changed, 463 insertions(+) > > create mode 100644 hw/ssi/mss-spi.c > > create mode 100644 include/hw/ssi/mss-spi.h > > > > diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs > > index 487add2..f5bcc65 100644 > > --- a/hw/ssi/Makefile.objs > > +++ b/hw/ssi/Makefile.objs > > @@ -4,6 +4,7 @@ common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o > > common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o > > common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o > > common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o > > +common-obj-$(CONFIG_MSF2) += mss-spi.o > > > > obj-$(CONFIG_OMAP) += omap_spi.o > > obj-$(CONFIG_IMX) += imx_spi.o > > diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c > > new file mode 100644 > > index 000..5a8e308 > > --- /dev/null > > +++ b/hw/ssi/mss-spi.c > > @@ -0,0 +1,404 @@ > > +/* > > + * Block model of SPI controller present in > > + * Microsemi's SmartFusion2 and SmartFusion SoCs. > > + * > > + * Copyright (C) 2017 Subbaraya Sundeep > > + * > > + * Permission is hereby granted, free of charge, to any person > obtaining a copy > > + * of this software and associated documentation files (the > "Software"), to deal > > + * in the Software without restriction, including without limitation > the rights > > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or > sell > > + * copies of the Software, and to permit persons to whom the Software is > > + * furnished to do so, subject to the following conditions: > > + * > > + * The above copyright notice and this permission notice shall be > included in > > + * all copies or substantial portions of the Software. > > + * > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > EXPRESS OR > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF > MERCHANTABILITY, > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT > SHALL > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR > OTHER > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > ARISING FROM, > > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER > DEALINGS IN > > + * THE SOFTWARE. > > + */ > > + > > +#include "qemu/osdep.h" > > +#include "hw/ssi/mss-spi.h" > > +#include "qemu/log.h" > > + > > +#ifndef MSS_SPI_ERR_DEBUG > > +#define MSS_SPI_ERR_DEBUG 0 > > +#endif > > + > > +#define DB_PRINT_L(lvl, fmt, args...) do { \ > > +if (MSS_SPI_ERR_DEBUG >= lvl) { \ > > +qemu_log("%s: " fmt "\n", __func__, ## args); \ > > +} \ > > +} while (0); > > + > > +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) > > + > > +#define FIFO_CAPACITY 32 > > + > > +#define R_SPI_CONTROL 0 > > +#define R_SPI_DFSIZE 1 > > +#define R_SPI_STATUS 2 > > +#define R_SPI_INTCLR 3 > > +#define R_SPI_RX 4 > > +#define R_SPI_TX 5 > > +#define R_SPI_CLKGEN 6 > > +#define R_SPI_SS 7 > > +#define R_SPI_MIS 8 > > +#define R_SPI_RIS 9 > > + > > +#define S_TXDONE (1 << 0) > > +#define S_RXRDY (1 << 1) > > +#define S_RXCHOVRF (1 << 2) > > +#define S_RXFIFOFUL (1 << 4) > > +#define S_RXFIFOFULNXT (1 << 5) > > +#define S_RXFIFOEMP (1 << 6) > > +#define S_RXFIFOEMPNXT (1 << 7) > > +#define S_TXFIFOFUL (1 << 8) > > +#define S_TXFIFOFULNXT (1 << 9) > > +#define S_TXFIFOEMP (1 << 10) > > +#define S_TXFIFOEMPNXT (1 << 11) > > +#define S_FRAMESTART (1 << 12) > > +#define S_SSEL (1 << 13) > > +#define S_ACTIVE (1 << 14) > > + > > +#define C_ENABLE (1 << 0) > > +#define C_MODE (1 << 1) > > +#define C_INTRXDATA (1 << 4) > > +#define C_INTTXDATA (1 << 5) > > +#define C_INTRXOVRFLO(1 << 6) > > +#define C_SPS(1 << 26) > > +#define C_BIGFIFO(1 << 29) > > +#define C_RESET (1 << 31) > > + > > +#define FRAMESZ_MASK 0x1F > > +#define FMCOUNT_MASK 0x0000 > > +#define FMCOUNT_SHIFT8 > > + > > +static void txfifo_reset(MSSSpiState *s) > > +{ > > +fifo32_reset(&s->tx_fifo); > > + > > +s->regs[R_SPI_STATUS] &= ~S_TXFIFOFUL; > > +s->regs[R_SPI_STATUS] |= S_TXFIFOEMP; > > +} > > + > > +static void rxfifo_reset(MSSSpiState *s) > > +{ > > +fifo32_reset(&s->rx_fifo); > > + > > +s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL; > > +s->regs[R_