On Fri, Jan 13, 2017 at 05:28:12PM +1100, Suraj Jitindar Singh wrote:
> The vpm0 bit was removed from the LPCR in POWER9, this bit controlled
> whether ISI and DSI interrupts were directed to the hypervisor or the
> partition. These interrupts now go to the hypervisor irrespective, thus
> it is no longer necessary to check the vmp0 bit in the LPCR.
>
> Signed-off-by: Suraj Jitindar Singh
Reviewed-by: David Gibson
> ---
> target/ppc/mmu-hash64.c | 20 ++--
> 1 file changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index 3a2acb8..fe7da18 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -640,7 +640,15 @@ static void ppc_hash64_set_isi(CPUState *cs, CPUPPCState
> *env,
> if (msr_ir) {
> vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
> } else {
> -vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
> +switch (env->mmu_model) {
> +case POWERPC_MMU_3_00:
> +/* Field deprecated in ISAv3.00 - interrupts always go to hyperv
> */
> +vpm = true;
> +break;
> +default:
> +vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
> +break;
> +}
> }
> if (vpm && !msr_hv) {
> cs->exception_index = POWERPC_EXCP_HISI;
> @@ -658,7 +666,15 @@ static void ppc_hash64_set_dsi(CPUState *cs, CPUPPCState
> *env, uint64_t dar,
> if (msr_dr) {
> vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
> } else {
> -vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
> +switch (env->mmu_model) {
> +case POWERPC_MMU_3_00:
> +/* Field deprecated in ISAv3.00 - interrupts always go to hyperv
> */
> +vpm = true;
> +break;
> +default:
> +vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
> +break;
> +}
> }
> if (vpm && !msr_hv) {
> cs->exception_index = POWERPC_EXCP_HDSI;
--
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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