Re: [Qemu-devel] [RFC PATCH 5/6] target/ppc: convert VMX logical instructions to use vector operations

[Richard Henderson]

On 12/7/18 2:56 AM, Mark Cave-Ayland wrote:
> Signed-off-by: Mark Cave-Ayland 
> ---
>  target/ppc/translate.c  |  1 +
>  target/ppc/translate/vmx-impl.inc.c | 64 
> ++---
>  2 files changed, 40 insertions(+), 25 deletions(-)

Reviewed-by: Richard Henderson 

r~

[Qemu-devel] [RFC PATCH 5/6] target/ppc: convert VMX logical instructions to use vector operations

[Mark Cave-Ayland]

Signed-off-by: Mark Cave-Ayland 
---
 target/ppc/translate.c  |  1 +
 target/ppc/translate/vmx-impl.inc.c | 64 ++---
 2 files changed, 40 insertions(+), 25 deletions(-)

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 5923c688cd..92d023864e 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -24,6 +24,7 @@
 #include "disas/disas.h"
 #include "exec/exec-all.h"
 #include "tcg-op.h"
+#include "tcg-op-gvec.h"
 #include "qemu/host-utils.h"
 #include "exec/cpu_ldst.h"
 
diff --git a/target/ppc/translate/vmx-impl.inc.c 
b/target/ppc/translate/vmx-impl.inc.c
index 30046c6e31..b252fce71b 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -14,6 +14,11 @@ static inline TCGv_ptr gen_avr_ptr(int reg)
 return r;
 }
 
+static inline long avr64_offset(int reg, bool high)
+{
+return offsetof(CPUPPCState, avr[reg].u64[(high ? 0 : 1)]);
+}
+
 #define GEN_VR_LDX(name, opc2, opc3)  \
 static void glue(gen_, name)(DisasContext *ctx)
   \
 { \
@@ -257,41 +262,50 @@ GEN_VX_VMUL10(vmul10euq, 1, 0);
 GEN_VX_VMUL10(vmul10cuq, 0, 1);
 GEN_VX_VMUL10(vmul10ecuq, 1, 1);
 
-/* Logical operations */
-#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3)\
-static void glue(gen_, name)(DisasContext *ctx)
 \
+#define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3)\
+static void glue(gen_, name)(DisasContext *ctx) \
 {   \
-TCGv_i64 t0 = tcg_temp_new_i64();   \
-TCGv_i64 t1 = tcg_temp_new_i64();   \
-TCGv_i64 avr = tcg_temp_new_i64();  \
+if (unlikely(!ctx->altivec_enabled)) {  \
+gen_exception(ctx, POWERPC_EXCP_VPU);   \
+return; \
+}   \
 \
+tcg_op(vece,\
+   avr64_offset(rD(ctx->opcode), true), \
+   avr64_offset(rA(ctx->opcode), true), \
+   avr64_offset(rB(ctx->opcode), true), \
+   16, 16); \
+}
+
+#define GEN_VXFORM_VN(name, vece, tcg_op, opc2, opc3)   \
+static void glue(gen_, name)(DisasContext *ctx) \
+{   \
 if (unlikely(!ctx->altivec_enabled)) {  \
 gen_exception(ctx, POWERPC_EXCP_VPU);   \
 return; \
 }   \
-get_avr64(t0, rA(ctx->opcode), true);   \
-get_avr64(t1, rB(ctx->opcode), true);   \
-tcg_op(avr, t0, t1);\
-set_avr64(rD(ctx->opcode), avr, true);  \
 \
-get_avr64(t0, rA(ctx->opcode), false);  \
-get_avr64(t1, rB(ctx->opcode), false);  \
-tcg_op(avr, t0, t1);\
-set_avr64(rD(ctx->opcode), avr, false); \
+tcg_op(vece,\
+   avr64_offset(rD(ctx->opcode), true), \
+   avr64_offset(rA(ctx->opcode), true), \
+   avr64_offset(rB(ctx->opcode), true), \
+   16, 16); \
 \
-tcg_temp_free_i64(t0);  \
-tcg_temp_free_i64(t1);  \
-tcg_temp_free_i64(avr); \
+tcg_gen_gvec_not(vece,  \
+ avr64_offset(rD(ctx->opcode), true),   \
+ avr64_offset(rD(ctx->opcode), true),   \
+ 16, 16);   \
 }
 
-GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
-GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64,