On 07/17/2017 12:45 PM, Ricardo Ribalda Delgado wrote:
Hi
I am missing the following functionality to fully emulate an AMD bulldozer v4:
-mno-avx
-mno-avx2
-mno-f16c
-mno-fma
-mno-fma4
-mno-prfchw
-mno-rdrnd
-mno-xop
To my knowledge, no one is working on any of these at present.
Getting AVX2 into qemu is a significant amount of work.
Once upon a time I began cleaning up the SSE support in the i386 translator,
modeling it off of the way vector support is done for the AArch64 translator.
I got just about far enough to think the SSE support was starting to look ok,
but never actually started in on actual AVX1 support.
The code is still sitting in
git://github.com/rth7680/qemu.git i386-avx
if you wish to look at what I was doing.
There may well be a simpler and more direct way of getting AVX support done.
The ugliest bit is the difference between any given SSE instruction when it is,
or isn't, encoded with the VEX prefix. Which to me implies getting rid of the
existing SSE tables.
r~
