[Qemu-devel] qemu/hw mips_r4k.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/12/07 01:13:38 Modified files: hw : mips_r4k.c Log message: Remove broken ds1225y init, it is useless on this machine anyway. Spotted by Atsushi Nemoto. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/mips_r4k.c?cvsroot=qemur1=1.56r2=1.57
[Qemu-devel] qemu/hw mips_r4k.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Paul Brook pbrook 07/11/11 12:02:33 Modified files: hw : mips_r4k.c Log message: mips_r4k warning fixes. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/mips_r4k.c?cvsroot=qemur1=1.52r2=1.53
[Qemu-devel] qemu/hw mips_r4k.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/10/13 14:00:23 Modified files: hw : mips_r4k.c Log message: Static-ify function. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/mips_r4k.c?cvsroot=qemur1=1.48r2=1.49
[Qemu-devel] qemu/hw mips_r4k.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/03/17 15:21:30 Modified files: hw : mips_r4k.c Log message: Remove useless static specifier. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/mips_r4k.c?cvsroot=qemur1=1.37r2=1.38 ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu/hw mips_r4k.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/01/06 01:37:51 Modified files: hw : mips_r4k.c Log message: Different MIPS BIOS binary names per endianness, and more relaxed size rules for the binaries, by Alec Voropay. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/mips_r4k.c?cvsroot=qemur1=1.29r2=1.30 ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu/hw mips_r4k.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/01/06 02:24:15 Modified files: hw : mips_r4k.c Log message: Unbreak the last patch. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/mips_r4k.c?cvsroot=qemur1=1.30r2=1.31 ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu/hw mips_r4k.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/01/01 20:31:07 Modified files: hw : mips_r4k.c Log message: Fix initrd load address. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/mips_r4k.c?cvsroot=qemur1=1.28r2=1.29 ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu/hw mips_r4k.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 06/12/23 00:23:19 Modified files: hw : mips_r4k.c Log message: More serial ports for the mips machine. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/mips_r4k.c?cvsroot=qemur1=1.26r2=1.27 ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
Re: [Qemu-devel] qemu hw/mips_r4k.c target-mips/cpu.h target-mip...
You should suppress the SIGN_EXTEND32() macro and just use an 'int32_t' cast... Fabrice. Thiemo Seufer wrote: CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 06/12/21 01:19:56 Modified files: hw : mips_r4k.c target-mips: cpu.h exec.h fop_template.c helper.c mips-defs.h op.c op_helper.c op_helper_mem.c op_mem.c op_template.c translate.c Log message: Preliminiary MIPS64 support, disabled by default due to performance impact. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/mips_r4k.c?cvsroot=qemur1=1.24r2=1.25 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/cpu.h?cvsroot=qemur1=1.13r2=1.14 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/exec.h?cvsroot=qemur1=1.12r2=1.13 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/fop_template.c?cvsroot=qemur1=1.1r2=1.2 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/helper.c?cvsroot=qemur1=1.19r2=1.20 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/mips-defs.h?cvsroot=qemur1=1.5r2=1.6 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op.c?cvsroot=qemur1=1.16r2=1.17 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_helper.c?cvsroot=qemur1=1.20r2=1.21 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_helper_mem.c?cvsroot=qemur1=1.3r2=1.4 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_mem.c?cvsroot=qemur1=1.4r2=1.5 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_template.c?cvsroot=qemur1=1.1r2=1.2 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/translate.c?cvsroot=qemur1=1.28r2=1.29 ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
Re: [Qemu-devel] qemu hw/mips_r4k.c target-mips/cpu.h target-mip...
Fabrice Bellard wrote: You should suppress the SIGN_EXTEND32() macro and just use an 'int32_t' cast... Then it may not work. A MIPS64 CPU requires properly sign-extended 32bit values. Host architectures can define either sign- or zero- Extension for 32bit values in 64bit Registers. Thiemo ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu hw/mips_r4k.c target-mips/cpu.h target-mip...
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 06/12/21 13:48:28 Modified files: hw : mips_r4k.c target-mips: cpu.h helper.c op.c op_helper.c translate.c Log message: Scrap SIGN_EXTEND32. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/mips_r4k.c?cvsroot=qemur1=1.25r2=1.26 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/cpu.h?cvsroot=qemur1=1.14r2=1.15 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/helper.c?cvsroot=qemur1=1.20r2=1.21 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op.c?cvsroot=qemur1=1.17r2=1.18 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_helper.c?cvsroot=qemur1=1.21r2=1.22 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/translate.c?cvsroot=qemur1=1.29r2=1.30 ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
Re: [Qemu-devel] qemu hw/mips_r4k.c target-mips/cpu.h target-mip...
On 12/21/06, Thiemo Seufer [EMAIL PROTECTED] wrote: Fabrice Bellard wrote: You should suppress the SIGN_EXTEND32() macro and just use an 'int32_t' cast... Then it may not work. A MIPS64 CPU requires properly sign-extended 32bit values. Host architectures can define either sign- or zero- Extension for 32bit values in 64bit Registers. Whether or not it works, GCC *WILL* optimize it away as a redundant statement, if it deems so (i.e., if it's called with some flag that enables cse/gcse and peephole optimizations, and the variable(s) in question is(are) not declared volatile). IMHO macros like these SHOULD stay, as they are mostly innocuous and happen to document the target machine behaviour. Cheers, A. ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
Re: [Qemu-devel] qemu hw/mips_r4k.c target-mips/cpu.h target-mip...
André Braga wrote: On 12/21/06, Thiemo Seufer [EMAIL PROTECTED] wrote: Fabrice Bellard wrote: You should suppress the SIGN_EXTEND32() macro and just use an 'int32_t' cast... Then it may not work. A MIPS64 CPU requires properly sign-extended 32bit values. Host architectures can define either sign- or zero- Extension for 32bit values in 64bit Registers. Whether or not it works, GCC *WILL* optimize it away as a redundant statement, Only iff it is redundant, which is what we want to achieve. if it deems so (i.e., if it's called with some flag that enables cse/gcse and peephole optimizations, and the variable(s) in question is(are) not declared volatile). Currently it appears to work as is. Given that the CPU env is a global it is unlikely gcc can use fancy optimizations. When compiling with -combine we may need to declare the emulated machine registers volatile. IMHO macros like these SHOULD stay, as they are mostly innocuous and happen to document the target machine behaviour. I disagree, it clutters the source more, and a cast provides the same information. Thiemo ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu hw/mips_r4k.c target-mips/cpu.h target-mip...
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 06/12/21 01:19:56 Modified files: hw : mips_r4k.c target-mips: cpu.h exec.h fop_template.c helper.c mips-defs.h op.c op_helper.c op_helper_mem.c op_mem.c op_template.c translate.c Log message: Preliminiary MIPS64 support, disabled by default due to performance impact. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/mips_r4k.c?cvsroot=qemur1=1.24r2=1.25 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/cpu.h?cvsroot=qemur1=1.13r2=1.14 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/exec.h?cvsroot=qemur1=1.12r2=1.13 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/fop_template.c?cvsroot=qemur1=1.1r2=1.2 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/helper.c?cvsroot=qemur1=1.19r2=1.20 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/mips-defs.h?cvsroot=qemur1=1.5r2=1.6 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op.c?cvsroot=qemur1=1.16r2=1.17 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_helper.c?cvsroot=qemur1=1.20r2=1.21 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_helper_mem.c?cvsroot=qemur1=1.3r2=1.4 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_mem.c?cvsroot=qemur1=1.4r2=1.5 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_template.c?cvsroot=qemur1=1.1r2=1.2 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/translate.c?cvsroot=qemur1=1.28r2=1.29 ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu hw/mips_r4k.c target-mips/cpu.h target-mip...
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 06/12/06 17:48:53 Modified files: hw : mips_r4k.c target-mips: cpu.h translate.c Log message: Halt/reboot support for Linux, by Daniel Jacobowitz. This is a band-aid until we emulate real MIPS hardware with real firmware. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/mips_r4k.c?cvsroot=qemur1=1.21r2=1.22 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/cpu.h?cvsroot=qemur1=1.11r2=1.12 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/translate.c?cvsroot=qemur1=1.18r2=1.19 ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu/hw mips_r4k.c
CVSROOT:/sources/qemu Module name:qemu Branch: Changes by: Fabrice Bellard [EMAIL PROTECTED] 06/05/11 21:15:08 Modified files: hw : mips_r4k.c Log message: mips bios loading fix CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/qemu/hw/mips_r4k.c.diff?tr1=1.16tr2=1.17r1=textr2=text ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
Re: [Qemu-devel] qemu/hw mips_r4k.c
Fabrice Bellard wrote: CVSROOT: /sources/qemu Module name: qemu Branch: Changes by: Fabrice Bellard [EMAIL PROTECTED] 06/05/11 21:15:08 Modified files: hw : mips_r4k.c Log message: mips bios loading fix CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/qemu/hw/mips_r4k.c.diff?tr1=1.16tr2=1.17r1=textr2=text Why is this correct? I would have expected moving parts of the initialisation in front of the file loads would be the right fix. (Those parts which aren't supposed to be done by the BIOS.) Thiemo ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
Re: [Qemu-devel] qemu/hw mips_r4k.c
Thiemo Seufer wrote: Fabrice Bellard wrote: CVSROOT:/sources/qemu Module name:qemu Branch: Changes by: Fabrice Bellard [EMAIL PROTECTED] 06/05/11 21:15:08 Modified files: hw : mips_r4k.c Log message: mips bios loading fix CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/qemu/hw/mips_r4k.c.diff?tr1=1.16tr2=1.17r1=textr2=text Why is this correct? I would have expected moving parts of the initialisation in front of the file loads would be the right fix. (Those parts which aren't supposed to be done by the BIOS.) The bug I fixed was that the BIOS could not be used without specifying -kernel x. Fabrice. ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
Re: [Qemu-devel] qemu/hw mips_r4k.c
Thiemo Seufer wrote: Fabrice Bellard wrote: CVSROOT:/sources/qemu Module name:qemu Branch: Changes by: Fabrice Bellard [EMAIL PROTECTED] 06/05/02 22:18:28 Modified files: hw : mips_r4k.c Log message: performance boost (on P4 hosts at least, rdtsc is a _very_ bad random generator) CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/qemu/hw/mips_r4k.c.diff?tr1=1.15tr2=1.16r1=textr2=text Does this really provide a measurable performance improvement? Real hardware simply increments cp0_random together with the cycle counter, this is randomized enough for TLB entry replacement. Unfortunately, at least on my P4 PC it is not random enough: it is always a multiple of two, so the number of TLBs is divided by two ! The speed improvement is _very_ noticeable. Your patch to accelerate tlb_flush_page() is still interesting, but I would like to be sure that it does not reduce the speed of the x86 target. In particular, it could be possible to make it even faster by reducing the size of the memset by using a smarter hash for tb_jmp_cache (a few bit of the index could depend only on the memory page number). Fabrice. ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
Re: [Qemu-devel] qemu/hw mips_r4k.c
Fabrice Bellard wrote: Thiemo Seufer wrote: Fabrice Bellard wrote: CVSROOT:/sources/qemu Module name:qemu Branch: Changes by: Fabrice Bellard [EMAIL PROTECTED] 06/05/02 22:18:28 Modified files: hw : mips_r4k.c Log message: performance boost (on P4 hosts at least, rdtsc is a _very_ bad random generator) CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/qemu/hw/mips_r4k.c.diff?tr1=1.15tr2=1.16r1=textr2=text Does this really provide a measurable performance improvement? Real hardware simply increments cp0_random together with the cycle counter, this is randomized enough for TLB entry replacement. Unfortunately, at least on my P4 PC it is not random enough: it is always a multiple of two, so the number of TLBs is divided by two ! The speed improvement is _very_ noticeable. Your patch to accelerate tlb_flush_page() is still interesting, but I would like to be sure that it does not reduce the speed of the x86 target. In particular, it could be possible to make it even faster by reducing the size of the memset by using a smarter hash for tb_jmp_cache (a few bit of the index could depend only on the memory page number). As interim solution I moved it to mips specific code, I still don't trust the MIPS TLB handling that much since it starts to fail once I remove seemingly unnecessary flushes. I still have nearly no time to work on qemu ATM. :-( Thiemo ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu/hw mips_r4k.c
CVSROOT:/sources/qemu Module name:qemu Branch: Changes by: Fabrice Bellard [EMAIL PROTECTED] 06/05/02 22:18:28 Modified files: hw : mips_r4k.c Log message: performance boost (on P4 hosts at least, rdtsc is a _very_ bad random generator) CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/qemu/hw/mips_r4k.c.diff?tr1=1.15tr2=1.16r1=textr2=text ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
Re: [Qemu-devel] qemu/hw mips_r4k.c
Fabrice Bellard wrote: CVSROOT: /sources/qemu Module name: qemu Branch: Changes by: Fabrice Bellard [EMAIL PROTECTED] 06/05/02 22:18:28 Modified files: hw : mips_r4k.c Log message: performance boost (on P4 hosts at least, rdtsc is a _very_ bad random generator) CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/qemu/hw/mips_r4k.c.diff?tr1=1.15tr2=1.16r1=textr2=text Does this really provide a measurable performance improvement? Real hardware simply increments cp0_random together with the cycle counter, this is randomized enough for TLB entry replacement. Thiemo ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu/hw mips_r4k.c
CVSROOT:/sources/qemu Module name:qemu Branch: Changes by: Fabrice Bellard [EMAIL PROTECTED] 05/12/18 17:51:01 Modified files: hw : mips_r4k.c Log message: do not init ne2000 if no network enabled CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/qemu/hw/mips_r4k.c.diff?tr1=1.12tr2=1.13r1=textr2=text ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu/hw mips_r4k.c
CVSROOT:/cvsroot/qemu Module name:qemu Branch: Changes by: Fabrice Bellard [EMAIL PROTECTED] 05/12/05 19:56:38 Modified files: hw : mips_r4k.c Log message: kernel command line support (Daniel Jacobowitz) CVSWeb URLs: http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/hw/mips_r4k.c.diff?tr1=1.11tr2=1.12r1=textr2=text ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu/hw mips_r4k.c
CVSROOT:/cvsroot/qemu Module name:qemu Branch: Changes by: Fabrice Bellard [EMAIL PROTECTED] 05/07/02 15:11:25 Modified files: hw : mips_r4k.c Log message: kernel load fix (Ralf Baechle) CVSWeb URLs: http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/hw/mips_r4k.c.diff?tr1=1.1tr2=1.2r1=textr2=text ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu/hw mips_r4k.c
CVSROOT:/cvsroot/qemu Module name:qemu Branch: Changes by: Fabrice Bellard [EMAIL PROTECTED] 05/07/02 18:11:03 Modified files: hw : mips_r4k.c Log message: i8259 PIC support CVSWeb URLs: http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/hw/mips_r4k.c.diff?tr1=1.5tr2=1.6r1=textr2=text ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
