[Qemu-devel] qemu/target-ppc cpu.h
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/12/10 08:13:10 Modified files: target-ppc : cpu.h Log message: Cleanup: remove useless TARGET_GPR_BITS definition. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.109r2=1.110
[Qemu-devel] qemu/target-ppc cpu.h translate_init.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/12/10 07:40:16 Modified files: target-ppc : cpu.h translate_init.c Log message: Fix PowerPC 74xx definitions. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.108r2=1.109 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.70r2=1.71
[Qemu-devel] qemu/target-ppc cpu.h exec.h helper.c op_helper...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/24 02:03:56 Modified files: target-ppc : cpu.h exec.h helper.c op_helper.c translate.c Log message: Fix incorrect debug prints (reported by Paul Brook). Remove obsolete / duplicated debug prints and improve output consistency. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.107r2=1.108 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/exec.h?cvsroot=qemur1=1.32r2=1.33 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.97r2=1.98 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemur1=1.72r2=1.73 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.114r2=1.115
[Qemu-devel] qemu/target-ppc cpu.h translate_init.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/21 13:08:23 Modified files: target-ppc : cpu.h translate_init.c Log message: Fix PowerPC 7xx definitions. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.104r2=1.105 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.69r2=1.70
[Qemu-devel] qemu/target-ppc cpu.h helper.c translate_init.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/19 11:41:10 Modified files: target-ppc : cpu.h helper.c translate_init.c Log message: PowerPC 620 MMU do not have the same exact behavior as standard 64 bits PowerPC ones. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.102r2=1.103 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.94r2=1.95 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.67r2=1.68
[Qemu-devel] qemu/target-ppc cpu.h helper.c helper_regs.h op...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/17 21:14:09 Modified files: target-ppc : cpu.h helper.c helper_regs.h op_helper.c Log message: PowerPC hypervisor mode is not fundamentally available only for PowerPC 64. Remove TARGET_PPC64 dependency and add code provision to be able to define a fake 32 bits CPU with hypervisor feature support. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.97r2=1.98 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.92r2=1.93 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper_regs.h?cvsroot=qemur1=1.4r2=1.5 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemur1=1.69r2=1.70
[Qemu-devel] qemu/target-ppc cpu.h helper.c translate_init.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/17 22:42:36 Modified files: target-ppc : cpu.h helper.c translate_init.c Log message: Define Freescale cores specific MMU model, exceptions and input bus. (but do not provide any actual implementation). CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.98r2=1.99 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.93r2=1.94 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.63r2=1.64
[Qemu-devel] qemu/target-ppc cpu.h translate_init.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/17 23:02:21 Modified files: target-ppc : cpu.h translate_init.c Log message: Add definitions for Freescale PowerPC implementations, ie MPC5xx, MPC8xx, e200, e300, e500 and e600 cores. Make those CPUs and PowerPC 440 available for user-mode emulation, thus providing a way of testing their implementation specific instructions. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.99r2=1.100 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.64r2=1.65
[Qemu-devel] qemu/target-ppc cpu.h translate_init.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/17 23:14:54 Modified files: target-ppc : cpu.h translate_init.c Log message: Improve PowerPC instructions set dump. Remove meaningless define from cpu.h Misc cleanups. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.100r2=1.101 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.65r2=1.66
Re: [Qemu-devel] qemu target-ppc/cpu.h target-ppc/op.c target-pp...
On Fri, 2007-11-16 at 14:11 +, Jocelyn Mayer wrote: CVSROOT: /sources/qemu Module name: qemu Changes by: Jocelyn Mayer j_mayer 07/11/16 14:11:29 Modified files: target-ppc : cpu.h op.c op_helper.c op_helper.h translate.c . : translate-all.c Log message: Always make PowerPC hypervisor mode memory accesses and instructions available for full system emulation, then removing all #if TARGET_PPC64H from micro-ops and code translator. Add new macros to dramatically simplify memory access tables definitions in target-ppc/translate.c. Remark: one should take care that having the hypervisor memory accessor available might lead to trigger the gcc inlining limits bug. Then it seems to me that a fix for this bug is needed asap, as reported in my previous messages (titled RFC: fix for random Qemu crashes). -- J. Mayer [EMAIL PROTECTED] Never organized
[Qemu-devel] qemu target-ppc/cpu.h target-ppc/op.c target-pp...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/16 14:11:29 Modified files: target-ppc : cpu.h op.c op_helper.c op_helper.h translate.c . : translate-all.c Log message: Always make PowerPC hypervisor mode memory accesses and instructions available for full system emulation, then removing all #if TARGET_PPC64H from micro-ops and code translator. Add new macros to dramatically simplify memory access tables definitions in target-ppc/translate.c. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.93r2=1.94 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op.c?cvsroot=qemur1=1.67r2=1.68 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemur1=1.68r2=1.69 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.h?cvsroot=qemur1=1.28r2=1.29 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.108r2=1.109 http://cvs.savannah.gnu.org/viewcvs/qemu/translate-all.c?cvsroot=qemur1=1.21r2=1.22
[Qemu-devel] qemu/target-ppc cpu.h translate_init.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/17 02:16:14 Modified files: target-ppc : cpu.h translate_init.c Log message: Make the PowerPC MMU model, exception model and input bus model typedefed enums. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.96r2=1.97 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.61r2=1.62
[Qemu-devel] qemu/target-ppc cpu.h exec.h
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/14 18:45:53 Modified files: target-ppc : cpu.h exec.h Log message: Fix PowerPC targets compilation on 32 bits hosts: now that the SPE extension is available for all targets, we always need to have some 64 bits temporary registers. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.92r2=1.93 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/exec.h?cvsroot=qemur1=1.31r2=1.32
[Qemu-devel] qemu/target-ppc cpu.h op_template.h translate.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/12 23:29:14 Modified files: target-ppc : cpu.h op_template.h translate.c Log message: PowerPC SPE extension fix: must always preserve GPR high bits when running in 32 bits mode. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.91r2=1.92 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_template.h?cvsroot=qemur1=1.14r2=1.15 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.105r2=1.106
[Qemu-devel] qemu/target-ppc cpu.h translate_init.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/10 23:51:03 Modified files: target-ppc : cpu.h translate_init.c Log message: Allow selection of PowerPC CPU giving a PVR. Remove unused pvr_mask field from CPU definition. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.89r2=1.90 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.57r2=1.58
[Qemu-devel] qemu/target-ppc cpu.h exec.h helper.c op_helper...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/03 13:37:12 Modified files: target-ppc : cpu.h exec.h helper.c op_helper.c translate_init.c Log message: PowerPC MMU and exception fixes: * PowerPC 601 (and probably POWER/POWER2) uses a different BAT format than later PowerPC implementation. * Bugfix in BATs check: must not stop after 4 BATs when more are provided. * Enable POWER 'rac' instruction. * Fix exception prefix for all supported PowerPC implementations. * Fix exceptions, MMU model and bus model for PowerPC 601 620. * Enable PowerPC 620 as it could mostly boot a PreP target. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.86r2=1.87 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/exec.h?cvsroot=qemur1=1.30r2=1.31 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.86r2=1.87 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemur1=1.61r2=1.62 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.53r2=1.54
[Qemu-devel] qemu/target-ppc cpu.h helper.c helper_regs.h op...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/04 02:55:34 Modified files: target-ppc : cpu.h helper.c helper_regs.h op.c op_helper.c op_helper.h translate.c translate_init.c Log message: PowerPC 601 need specific callbacks for its BATs setup. Implement PowerPC 601 HID0 register, needed for little-endian mode support. As a consequence, we need to merge hflags coming from MSR with other ones. Use little-endian mode from hflags instead of MSR during code translation. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.87r2=1.88 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.87r2=1.88 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper_regs.h?cvsroot=qemur1=1.2r2=1.3 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op.c?cvsroot=qemur1=1.61r2=1.62 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemur1=1.62r2=1.63 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.h?cvsroot=qemur1=1.25r2=1.26 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.101r2=1.102 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.55r2=1.56
[Qemu-devel] qemu/target-ppc cpu.h
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/25 23:27:04 Modified files: target-ppc : cpu.h Log message: Add PowerPC power-management state check callback. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.84r2=1.85
[Qemu-devel] qemu/target-ppc cpu.h helper.c translate_init.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/14 09:14:09 Modified files: target-ppc : cpu.h helper.c translate_init.c Log message: There is no need of a specific MMU model for PowerPC 601. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.80r2=1.81 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.78r2=1.79 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.50r2=1.51
[Qemu-devel] qemu/target-ppc cpu.h
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/14 09:27:16 Modified files: target-ppc : cpu.h Log message: Merge PowerPC 620 input bus definitions with standard PowerPC 6xx. Avoid hardcoding PowerPC interrupts definitions to ease updates. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.81r2=1.82
[Qemu-devel] qemu/target-ppc cpu.h helper.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/14 10:21:20 Modified files: target-ppc : cpu.h helper.c Log message: Properly implement non-execute bit on PowerPC segments and PTEs. Fix page protection bits for PowerPC 64 MMU. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.82r2=1.83 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.79r2=1.80
[Qemu-devel] qemu/target-ppc cpu.h helper.c translate.c tran...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/07 14:41:00 Modified files: target-ppc : cpu.h helper.c translate.c translate_init.c Log message: Add MSR bits signification per PowerPC implementation flags (to be continued). As a side effect, single step and branch step are available again. Remove irrelevant MSR bits definitions. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.73r2=1.74 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.69r2=1.70 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.86r2=1.87 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.43r2=1.44
[Qemu-devel] qemu/target-ppc cpu.h translate.c translate_init.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/07 15:43:50 Modified files: target-ppc : cpu.h translate.c translate_init.c Log message: Reorganize the CPUPPCState structure to group features. Add #ifdef to avoid compiling not relevant resources: - MMU related stuff for user-mode only targets - PowerPC 64 only resources for PowerPC 32 targets - embedded PowerPC extensions for non-ppcemb targets. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.74r2=1.75 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.87r2=1.88 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.44r2=1.45
[Qemu-devel] qemu/target-ppc cpu.h exec.h op_mem.h op_templa...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/07 18:19:26 Modified files: target-ppc : cpu.h exec.h op_mem.h op_template.h translate.c Log message: Implement PowerPC Altivec load stores, used by Apple firmware for memcpy. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.76r2=1.77 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/exec.h?cvsroot=qemur1=1.27r2=1.28 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_mem.h?cvsroot=qemur1=1.21r2=1.22 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_template.h?cvsroot=qemur1=1.10r2=1.11 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.90r2=1.91
[Qemu-devel] qemu/target-ppc cpu.h helper.c translate_init.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/08 02:58:07 Modified files: target-ppc : cpu.h helper.c translate_init.c Log message: Remove synonymous in PowerPC MSR bits definitions. Fix MSR EP bit buggy definition. Remove unuseful MSR flags. Fix MSR bits and flags definitions for most supported PowerPC implementations. Add MSR definitions/flags constistency checks and optional dump. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.77r2=1.78 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.74r2=1.75 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.49r2=1.50
[Qemu-devel] qemu/target-ppc cpu.h translate_init.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/05 13:11:25 Modified files: target-ppc : cpu.h translate_init.c Log message: Rename PowerPC MMUCSR0 and MMUCFG SPRs: those are not BookE specific. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.71r2=1.72 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.41r2=1.42
[Qemu-devel] qemu/target-ppc cpu.h op_helper.c op_helper.h o...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/04 00:51:58 Modified files: target-ppc : cpu.h op_helper.c op_helper.h op_helper_mem.h op_mem.h translate.c translate_init.c Log message: Make PowerPC cache line size implementation dependant. Implement dcbz tunable cache line size for PowerPC 970. Make hardware reset vector implementation dependant. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.70r2=1.71 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemur1=1.47r2=1.48 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.h?cvsroot=qemur1=1.19r2=1.20 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper_mem.h?cvsroot=qemur1=1.11r2=1.12 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_mem.h?cvsroot=qemur1=1.18r2=1.19 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.84r2=1.85 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.38r2=1.39
[Qemu-devel] qemu/target-ppc cpu.h helper.c op.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/01 21:49:57 Modified files: target-ppc : cpu.h helper.c op.c Log message: Fix reproductible crash: call cpu_loop_exit from micro-op, not from helper.c CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.68r2=1.69 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.63r2=1.64 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op.c?cvsroot=qemur1=1.51r2=1.52
[Qemu-devel] qemu/target-ppc cpu.h exec.h helper.c op.c op_h...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/01 01:51:13 Modified files: target-ppc : cpu.h exec.h helper.c op.c op_helper.c translate.c Log message: Avoid op helpers that would just call helpers for TLB SLB management: call the helpers directly from the micro-ops. Avoid duplicated code for tlbsx. implementation. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.67r2=1.68 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/exec.h?cvsroot=qemur1=1.25r2=1.26 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.61r2=1.62 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op.c?cvsroot=qemur1=1.49r2=1.50 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemur1=1.45r2=1.46 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.79r2=1.80
[Qemu-devel] qemu/target-ppc cpu.h helper.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/09/30 00:50:23 Modified files: target-ppc : cpu.h helper.c Log message: XER is to be treated as a 64 bits register on 64 bits implementations, according to the PowerPC 2.04 specification. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.64r2=1.65 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.59r2=1.60
[Qemu-devel] qemu/target-ppc cpu.h helper.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/09/21 05:23:26 Modified files: target-ppc : cpu.h helper.c Log message: Make CPU hflags be a masked version of the PowerPC MSR. As a side effect, avoid potential bits shadowing in TB flags on 64 bits BookE. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.55r2=1.56 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.54r2=1.55
[Qemu-devel] qemu/target-ppc cpu.h
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/09/18 11:17:30 Modified files: target-ppc : cpu.h Log message: Fix PowerPC 32 emulation on 64 bits hosts: we can use 64 bits registers but not pretend page is 1kB long As it seems most Linux programs assume page-size is 4kB, never allow 1kB pages for user-mode only emulation. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.51r2=1.52
[Qemu-devel] qemu/target-ppc cpu.h op_helper_mem.h
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/09/19 04:34:09 Modified files: target-ppc : cpu.h op_helper_mem.h Log message: More PowerPC target cleanups: - remove unuseful historical macros and definitions - fix comments (bugs and cosmetics) CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.52r2=1.53 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper_mem.h?cvsroot=qemur1=1.10r2=1.11
[Qemu-devel] qemu/target-ppc cpu.h exec.h
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/07/11 10:36:47 Modified files: target-ppc : cpu.h exec.h Log message: Fix PPCEMB for 32bit hosts. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.48r2=1.49 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/exec.h?cvsroot=qemur1=1.21r2=1.22
[Qemu-devel] qemu/target-ppc cpu.h exec.h op.c op_helper.c o...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/04/24 06:50:21 Modified files: target-ppc : cpu.h exec.h op.c op_helper.c op_helper.h op_mem.h op_template.h translate.c Log message: Code provision for new PowerPC embedded target support with: - 1 kB page size - 64 bits GPR - 64 bits physical address space - SPE extension support. Change TARGET_PPCSPE into TARGET_PPCEMB CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.45r2=1.46 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/exec.h?cvsroot=qemur1=1.19r2=1.20 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op.c?cvsroot=qemur1=1.35r2=1.36 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemur1=1.30r2=1.31 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.h?cvsroot=qemur1=1.9r2=1.10 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_mem.h?cvsroot=qemur1=1.12r2=1.13 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_template.h?cvsroot=qemur1=1.7r2=1.8 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.57r2=1.58
[Qemu-devel] qemu/target-ppc cpu.h helper.c op_helper.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/04/16 09:21:46 Modified files: target-ppc : cpu.h helper.c op_helper.c Log message: PowerPC 4xx software driven TLB fixes + debug traces. Add code provision for more MMU models support. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.42r2=1.43 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.45r2=1.46 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemur1=1.28r2=1.29
[Qemu-devel] qemu/target-ppc cpu.h translate_init.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/03/30 10:07:33 Modified files: target-ppc : cpu.h translate_init.c Log message: Fix / update PowerPC BookE definitions. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.33r2=1.34 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.7r2=1.8
[Qemu-devel] qemu/target-ppc cpu.h
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/03/28 20:43:46 Modified files: target-ppc : cpu.h Log message: Solaris host compilation fix by Shaddy Baddah. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.31r2=1.32
[Qemu-devel] qemu/target-ppc cpu.h helper.c translate.c tran...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/03/23 09:40:22 Modified files: target-ppc : cpu.h helper.c translate.c translate_init.c Log message: Fix debug printf: we need different macros for target_ulong prints and GPR ones, as the lengths can be different. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.29r2=1.30 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.33r2=1.34 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.50r2=1.51 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.5r2=1.6 ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu/target-ppc cpu.h op.c translate.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/03/22 22:41:50 Modified files: target-ppc : cpu.h op.c translate.c Log message: PowerPC improvments: - add missing 64 bits rotate instructions - safely define TARGET_PPCSPE when 64 bits registers are used a separate target will be needed to use it in 32 bits mode on 32 bits hosts. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.28r2=1.29 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op.c?cvsroot=qemur1=1.28r2=1.29 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.49r2=1.50 ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
Re: [Qemu-devel] qemu/target-ppc cpu.h exec.h op.c op_helper.c o...
Hi Rob, On Thu, 22 Mar 2007, Rob Landley wrote: On Tuesday 20 March 2007 6:11 pm, Jocelyn Mayer wrote: Log message: PowerPC 2.03 SPE extension - first pass. QEMU supports the Cell processor now? How would one go about testing this? AFAIR Linux gained official Cell support recently... Ciao, Dscho ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu/target-ppc cpu.h exec.h op.c op_helper.c o...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/03/20 22:11:31 Modified files: target-ppc : cpu.h exec.h op.c op_helper.c op_helper.h op_mem.h op_template.h translate.c translate_init.c Log message: PowerPC 2.03 SPE extension - first pass. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.27r2=1.28 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/exec.h?cvsroot=qemur1=1.16r2=1.17 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op.c?cvsroot=qemur1=1.25r2=1.26 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemur1=1.20r2=1.21 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.h?cvsroot=qemur1=1.3r2=1.4 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_mem.h?cvsroot=qemur1=1.10r2=1.11 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_template.h?cvsroot=qemur1=1.6r2=1.7 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.47r2=1.48 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.4r2=1.5 ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu/target-ppc cpu.h exec.h helper.c op.c op_h...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/03/17 14:02:15 Modified files: target-ppc : cpu.h exec.h helper.c op.c op_helper.c op_helper.h op_helper_mem.h op_mem.h translate.c Log message: Make it safe to use 64 bits GPR and/or 64 bits host registers. For symetry, add 64 bits versions of all modified functions. As a side effect, add a lot of code provision for PowerPC 64 support. Move overflow and carry checks in common routines for simple cases. Add isel and popcntb instructions from PowerPC 2.03 specification. Remove remaining micro-operations helpers prototypes from op.c. Fix XER_BC field to be 7 bits long. Add power management support for PowerPC 603 604. Fix compilation warnings. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.26r2=1.27 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/exec.h?cvsroot=qemur1=1.15r2=1.16 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.32r2=1.33 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op.c?cvsroot=qemur1=1.23r2=1.24 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemur1=1.18r2=1.19 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.h?cvsroot=qemur1=1.1r2=1.2 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper_mem.h?cvsroot=qemur1=1.7r2=1.8 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_mem.h?cvsroot=qemur1=1.8r2=1.9 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.44r2=1.45 ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
RE: [Qemu-devel] qemu/target-ppc cpu.h exec.h helper.c op.c op_h...
Hi Jocelyn, Previously it was mentioned that there is a regression that was introduced by your original merge on March 8, 2007. I tested this latest code and it is still there. The nature of the problem is that the networking does not work when booting QEMU and using the built in slirp networking. A dhcp packet will work but the udp and tcp packets do not appear to send. It appears that the packet check sum computed by the Linux network stack is incorrect. When the code in slirp/ip_input.c checks the checksum of the udp or tcp packet it throws the packet away because the checksum was invalid. I took the code from March 7, 2007 in cvs for target-ppc/* and used it with the latest of everything else and the packet checksums are computed correct and the target boots with networking. This points to the problem being what ever instructions the kernel is using to compute the checksum are not being translated correctly by your latest changes. The next step will be to take a closer look at which instructions are used to compute the checksum. I thought I might send out some further analysis of the original stated problem in case you had an idea of where to look to fix the problem off the top of your head. If you have any ideas, please drop me some e-mail. Also with regard to the 2.6.21 kernel and the ppc-prep machine, I patched the kernel to make it send PCI interrupts the same way the prior kernels did. It seems there is a regression there inside the kernel in the way that the IRQ acknowledgements are handled. It could be that the emulation is not right in QEMU, but I figure that mystery is one for another day. If you need a kernel that boots on the ppc-prep please let me know. I also patched the prep loader in the linux kernel so I could boot an image that was larger than 4 megs. Thanks, Jason. -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] rg] On Behalf Of Jocelyn Mayer Sent: Saturday, March 17, 2007 9:02 AM To: qemu-devel@nongnu.org Subject: [Qemu-devel] qemu/target-ppc cpu.h exec.h helper.c op.c op_h... CVSROOT: /sources/qemu Module name: qemu Changes by: Jocelyn Mayer j_mayer 07/03/17 14:02:15 Modified files: target-ppc : cpu.h exec.h helper.c op.c op_helper.c op_helper.h op_helper_mem.h op_mem.h translate.c Log message: Make it safe to use 64 bits GPR and/or 64 bits host registers. For symetry, add 64 bits versions of all modified functions. As a side effect, add a lot of code provision for PowerPC 64 support. Move overflow and carry checks in common routines for simple cases. Add isel and popcntb instructions from PowerPC 2.03 specification. Remove remaining micro-operations helpers prototypes from op.c. Fix XER_BC field to be 7 bits long. Add power management support for PowerPC 603 604. Fix compilation warnings. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsr oot=qemur1=1.26r2=1.27 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/exec.h?cvs root=qemur1=1.15r2=1.16 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?c vsroot=qemur1=1.32r2=1.33 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op.c?cvsro ot=qemur1=1.23r2=1.24 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper. c?cvsroot=qemur1=1.18r2=1.19 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper. h?cvsroot=qemur1=1.1r2=1.2 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper_ mem.h?cvsroot=qemur1=1.7r2=1.8 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_mem.h?c vsroot=qemur1=1.8r2=1.9 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate. c?cvsroot=qemur1=1.44r2=1.45 ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu/target-ppc cpu.h exec.h helper.c op.c op_h...
CVSROOT:/cvsroot/qemu Module name:qemu Branch: Changes by: Fabrice Bellard [EMAIL PROTECTED] 05/07/04 22:17:06 Modified files: target-ppc : cpu.h exec.h helper.c op.c op_helper.c Log message: correct split between helper.c and op_helper.c - moved some uops to op_helper.c (Jocelyn Mayer) CVSWeb URLs: http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/target-ppc/cpu.h.diff?tr1=1.20tr2=1.21r1=textr2=text http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/target-ppc/exec.h.diff?tr1=1.11tr2=1.12r1=textr2=text http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/target-ppc/helper.c.diff?tr1=1.25tr2=1.26r1=textr2=text http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/target-ppc/op.c.diff?tr1=1.19tr2=1.20r1=textr2=text http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/target-ppc/op_helper.c.diff?tr1=1.15tr2=1.16r1=textr2=text ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu/target-ppc cpu.h
CVSROOT:/cvsroot/qemu Module name:qemu Branch: Changes by: Fabrice Bellard [EMAIL PROTECTED] 05/06/04 22:16:41 Modified files: target-ppc : cpu.h Log message: added temporary osi_call callback CVSWeb URLs: http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/target-ppc/cpu.h.diff?tr1=1.17tr2=1.18r1=textr2=text ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
