Re: [Qemu-devel] scsi patch
On 4/25/07, Wang Cheng Yeh [EMAIL PROTECTED] wrote: scsi.tex patch reduces unnecessary mismatch. lsi.txt corrects mismatch condition. When the mismatch happens, register ia saves the instruction address. However, QEMU call lsi_bad_phase first, update new dsp and then save it into register ia. The patch correct this problem. Another fix is in the table indirect addressing. s-rbc is the same as s-dbc in direct, indirect, and table indirect mode. I test 25 times debian installation automatically and there is no problem in scsi. The steps follow http://www.aurel32.net/info/debian_arm_qemu.php will work well !!! I tested the scsi-disk part on Sparc, seems to be fine.
[Qemu-devel] scsi patch
scsi.tex patch reduces unnecessary mismatch.
lsi.txt corrects mismatch condition.
When the mismatch happens, register ia saves the instruction address.
However, QEMU call lsi_bad_phase first, update new dsp and
then save it into register ia.
The patch correct this problem.
Another fix is in the table indirect addressing.
s-rbc is the same as s-dbc in direct, indirect, and table indirect mode.
I test 25 times debian installation automatically and there is no problem in
scsi.
The steps follow http://www.aurel32.net/info/debian_arm_qemu.php
will work well !!!
Index: hw/scsi-disk.c
===
RCS file: /sources/qemu/qemu/hw/scsi-disk.c,v
retrieving revision 1.13
diff -u -p -r1.13 scsi-disk.c
--- hw/scsi-disk.c 29 Aug 2006 04:52:16 - 1.13
+++ hw/scsi-disk.c 25 Apr 2007 04:55:11 -
@@ -345,7 +345,7 @@ int32_t scsi_send_command(SCSIDevice *s,
DPRINTF(Request Sense (len %d)\n, len);
if (len 4)
goto fail;
-memset(buf, 0, 4);
+memset(outbuf, 0, 4);
outbuf[0] = 0xf0;
outbuf[1] = 0;
outbuf[2] = s-sense;
@@ -371,7 +371,7 @@ int32_t scsi_send_command(SCSIDevice *s,
Some later commands are also implemented. */
outbuf[2] = 3;
outbuf[3] = 2; /* Format 2 */
- outbuf[4] = 32;
+ outbuf[4] = 31;
/* Sync data transfer and TCQ. */
outbuf[7] = 0x10 | (s-tcq ? 0x02 : 0);
r-buf_len = 36;
@@ -404,10 +404,11 @@ int32_t scsi_send_command(SCSIDevice *s,
p += 4;
if ((page == 8 || page == 0x3f)) {
/* Caching page. */
+memset(p,0,20);
p[0] = 8;
p[1] = 0x12;
p[2] = 4; /* WCE */
-p += 19;
+p += 20;
}
if ((page == 0x3f || page == 0x2a)
(bdrv_get_type_hint(s-bdrv) == BDRV_TYPE_CDROM)) {
@@ -437,7 +438,7 @@ int32_t scsi_send_command(SCSIDevice *s,
p[19] = (16 * 176) 0xff;
p[20] = (16 * 176) 8; // 16x write speed current
p[21] = (16 * 176) 0xff;
-p += 21;
+p += 22;
}
r-buf_len = p - outbuf;
outbuf[0] = r-buf_len - 4;
Index: hw/lsi53c895a.c
===
RCS file: /sources/qemu/qemu/hw/lsi53c895a.c,v
retrieving revision 1.8
diff -u -p -r1.8 lsi53c895a.c
--- hw/lsi53c895a.c 22 Apr 2007 17:18:38 - 1.8
+++ hw/lsi53c895a.c 25 Apr 2007 04:55:11 -
@@ -855,6 +855,7 @@ again:
offset = sxt24(addr);
cpu_physical_memory_read(s-dsa + offset, (uint8_t *)buf, 8);
s-dbc = cpu_to_le32(buf[0]);
+s-rbc = s-dbc;
addr = cpu_to_le32(buf[1]);
}
if ((s-sstat1 PHASE_MASK) != ((insn 24) 7)) {
@@ -864,6 +865,8 @@ again:
break;
}
s-dnad = addr;
+/* ??? Set ESA. */
+s-ia = s-dsp - 8;
switch (s-sstat1 0x7) {
case PHASE_DO:
s-waiting = 2;
@@ -898,8 +901,6 @@ again:
s-sbc = s-dbc;
s-rbc -= s-dbc;
s-ua = addr + s-dbc;
-/* ??? Set ESA. */
-s-ia = s-dsp - 8;
break;
case 1: /* IO or Read/Write instruction. */
[Qemu-devel] scsi patch
--- ../../tmp/qemu-0.9.0/hw/lsi53c895a.c2007-02-06 07:01: 54.0 +0800 +++ lsi53c895a.c2007-03-08 20:50:03.094098835 +0800 @@ -251,7 +251,7 @@ uint32_t ia; uint32_t sbc; uint32_t csbc; -uint32_t scratch[13]; /* SCRATCHA-SCRATCHR */ +uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */ /* Script ram is stored as 32-bit words in host byteorder. */ uint32_t script_ram[2048]; @@ -1038,7 +1038,7 @@ op0 |= op1; break; case 3: /* XOR */ -op0 |= op1; +op0 ^= op1; break; case 4: /* AND */ op0 = op1; @@ -1765,7 +1765,7 @@ lsi_reg_writeb(s, addr, val 0xff); lsi_reg_writeb(s, addr + 1, (val 8) 0xff); lsi_reg_writeb(s, addr + 2, (val 16) 0xff); -lsi_reg_writeb(s, addr + 2, (val 24) 0xff); +lsi_reg_writeb(s, addr + 3, (val 24) 0xff); }
Re: [Qemu-devel] scsi patch
? wrote: --- ../../tmp/qemu-0.9.0/hw/lsi53c895a.c2007-02-06 07:01: 54.0 +0800 +++ lsi53c895a.c2007-03-08 20:50:03.094098835 +0800 @@ -251,7 +251,7 @@ uint32_t ia; uint32_t sbc; uint32_t csbc; -uint32_t scratch[13]; /* SCRATCHA-SCRATCHR */ +uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */ This still looks inconsistent. SCRATCHR suggests 18 available registers, but the code below handles only 17 scratch registers. Could you check what's the right thing there? Otherwise the patch looks good. Thiemo ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
Re: [Qemu-devel] scsi patch
because (1) address of SCRATCHA is 0x34 (2) address from SCRATCHB to SCRATCHR are 0x5c ~ 0x9f you just see the code about part (2). I think the access code is right. 2007/3/19, Thiemo Seufer [EMAIL PROTECTED]: ? wrote: --- ../../tmp/qemu-0.9.0/hw/lsi53c895a.c2007-02-06 07:01: 54.0 +0800 +++ lsi53c895a.c2007-03-08 20:50:03.094098835 +0800 @@ -251,7 +251,7 @@ uint32_t ia; uint32_t sbc; uint32_t csbc; -uint32_t scratch[13]; /* SCRATCHA-SCRATCHR */ +uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */ This still looks inconsistent. SCRATCHR suggests 18 available registers, but the code below handles only 17 scratch registers. Could you check what's the right thing there? Otherwise the patch looks good. Thiemo ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] scsi patch
--- ../../tmp/qemu-0.9.0/hw/lsi53c895a.c2007-02-06 07:01: 54.0 +0800 +++ lsi53c895a.c2007-03-08 20:50:03.094098835 +0800 @@ -251,7 +251,7 @@ uint32_t ia; uint32_t sbc; uint32_t csbc; -uint32_t scratch[13]; /* SCRATCHA-SCRATCHR */ +uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */ /* Script ram is stored as 32-bit words in host byteorder. */ uint32_t script_ram[2048]; @@ -1038,7 +1038,7 @@ op0 |= op1; break; case 3: /* XOR */ -op0 |= op1; +op0 ^= op1; break; case 4: /* AND */ op0 = op1; @@ -1765,7 +1765,7 @@ lsi_reg_writeb(s, addr, val 0xff); lsi_reg_writeb(s, addr + 1, (val 8) 0xff); lsi_reg_writeb(s, addr + 2, (val 16) 0xff); -lsi_reg_writeb(s, addr + 2, (val 24) 0xff); +lsi_reg_writeb(s, addr + 3, (val 24) 0xff); } ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] SCSI [PATCH] SCSI externals changes
Here is the patch with texi updates and the enum set correctly so the
SCSI disk is visible. (I missed moving some lines from my previous level
of this patch.)
Chuck
diff -Nuar -X diff_excludes /hg-qemu/hw/pc.c /qemu-new/hw/pc.c
--- /hg-qemu/hw/pc.c2006-12-13 06:59:35.0 -0500
+++ /qemu-new/hw/pc.c 2006-12-13 13:52:24.0 -0500
@@ -688,23 +688,21 @@
if (i440fx_state) {
i440fx_init_memory_mappings(i440fx_state);
}
-#if 0
-/* ??? Need to figure out some way for the user to
- specify SCSI devices. */
if (pci_enabled) {
-void *scsi;
-BlockDriverState *bdrv;
-scsi = lsi_scsi_init(pci_bus, -1);
-bdrv = bdrv_new(scsidisk);
-bdrv_open(bdrv, scsi_disk.img, 0);
-lsi_scsi_attach(scsi, bdrv, -1);
-bdrv = bdrv_new(scsicd);
-bdrv_open(bdrv, scsi_cd.iso, 0);
-bdrv_set_type_hint(bdrv, BDRV_TYPE_CDROM);
-lsi_scsi_attach(scsi, bdrv, -1);
+void *scsi;
+if (scsi_hba_lsi 0) {
+if (!(scsi = lsi_scsi_init(pci_bus, -1))){
+ exit(1);
+}
+for(i = 0; i MAX_SCSI_DISKS; i++) {
+if (scsi_disks_info[i].adapter == SCSI_LSI_53C895A
+scsi_disks_info[i].device_type != SCSI_NONE) {
+lsi_scsi_attach(scsi, bs_scsi_table[i],
scsi_disks_info[i].id);
+}
+}
+}
}
-#endif
}
static void pc_init_pci(int ram_size, int vga_ram_size, int boot_device,
diff -Nuar -X diff_excludes /hg-qemu/vl.c /qemu-new/vl.c
--- /hg-qemu/vl.c 2006-12-13 06:59:35.0 -0500
+++ /qemu-new/vl.c 2006-12-13 09:55:20.0 -0500
@@ -109,6 +109,8 @@
/* XXX: use a two level table to limit memory usage */
#define MAX_IOPORTS 65536
+#define DISK_OPTIONS_SIZE 256
+
const char *bios_dir = CONFIG_QEMU_SHAREDIR;
char phys_ram_file[1024];
void *ioport_opaque[MAX_IOPORTS];
@@ -119,6 +121,9 @@
BlockDriverState *bs_table[MAX_DISKS + 1], *fd_table[MAX_FD];
/* point to the block driver where the snapshots are managed */
BlockDriverState *bs_snapshots;
+BlockDriverState *bs_scsi_table[MAX_SCSI_DISKS];
+SCSIDiskInfo scsi_disks_info[MAX_SCSI_DISKS];
+int scsi_hba_lsi; /* Count of scsi disks/cdrom using this lsi adapter */
int vga_ram_size;
int bios_size;
static DisplayState display_state;
@@ -3737,7 +3742,177 @@
term_printf( %s\n, vc-info_str);
}
}
-
+
+ /* Parse IDE and SCSI disk options */
+static int disk_options_init(int num_ide_disks,
+ char ide_disk_options[][DISK_OPTIONS_SIZE],
+ int snapshot,
+ int num_scsi_disks,
+ char scsi_disk_options[][DISK_OPTIONS_SIZE],
+ int cdrom_index,
+ int cyls,
+ int heads,
+ int secs,
+ int translation
+ )
+{
+char buf[256];
+char dev_name[64];
+int id, i, j;
+int cdrom_device;
+int ide_cdrom_created = 0;
+int scsi_index;
+scsi_host_adapters temp_adapter;
+
+/* Process any IDE disks/cdroms */
+for (i=0; i num_ide_disks; i++) {
+
+for (j=0; jMAX_DISKS; j++) {
+if (ide_disk_options[j][0] == '\0') continue;
+
+if (get_param_value(buf, sizeof(buf),type,ide_disk_options[j])) {
+if (!strcmp(buf, disk) ) {
+cdrom_device = 0;
+}else if (!strcmp(buf, cdrom) ) {
+cdrom_device = 1;
+ide_cdrom_created = 1;
+} else {
+fprintf(stderr, qemu: invalid IDE disk type= value:
%s\n, buf);
+return -1;
+}
+}
+else {
+cdrom_device = 0;
+}
+
+if (cdrom_device) {
+snprintf(dev_name, sizeof(dev_name), cdrom%c, i);
+}else{
+snprintf(dev_name, sizeof(dev_name), hd%c, i + 'a');
+}
+
+if (!(get_param_value(buf, sizeof(buf),img,ide_disk_options[j])
) ) {
+fprintf(stderr, qemu: missing IDE disk img= value.\n);
+return -1;
+}
+
+if (!(bs_table[i] = bdrv_new(dev_name) ) ){
+fprintf(stderr, qemu: unable to create new block device
for:%s\n,dev_name);
+return -1;
+}
+
+if (cdrom_device) {
+bdrv_set_type_hint(bs_table[i], BDRV_TYPE_CDROM);
+}
+
+if (bdrv_open(bs_table[i], buf, snapshot ? BDRV_O_SNAPSHOT : 0)
0) {
+fprintf(stderr, qemu: could not open hard disk image: '%s'\n,
+buf);
+return -1;
+}
+if (i == 0 cyls != 0) {
+
