On Fri, 22 Mar 2019 at 16:40, Andrew Jones wrote:
> Hi TCG GIC developers,
>
> There are a few gicv2 test failures when running over TCG that we don't
> see when running over KVM. I don't believe these are regressions - I'm
> pretty sure they've been failing since Andre first introduced the tests.
> I'm just pointing them out now in case anybody would like to look into
> them:
>
> $ git clone git://git.kernel.org/pub/scm/virt/kvm/kvm-unit-tests.git
> $ cd kvm-unit-tests
> $ ./configure --arch=arm64 --cross-prefix=aarch64-linux-gnu-
> $ make -j
> $ export QEMU=/path/to/qemu-system-aarch64
> $ ./run_tests.sh -g gic
> $ grep FAIL logs/gic*
> logs/gicv2-mmio-3p.log:FAIL: gicv2: mmio: ITARGETSR: bits for 5
> non-existent CPUs masked
> logs/gicv2-mmio-3p.log:FAIL: gicv2: mmio: ITARGETSR: register content
> preserved (01030207 => 0103020f)
> logs/gicv2-mmio-3p.log:FAIL: gicv2: mmio: ITARGETSR: byte writes successful
> (0x1f => 0x011f020f)
> logs/gicv2-mmio.log:FAIL: gicv2: mmio: ITARGETSR: bits for 4 non-existent
> CPUs masked
> logs/gicv2-mmio.log:FAIL: gicv2: mmio: ITARGETSR: byte writes successful
> (0x1f => 0x011f020f)
> logs/gicv2-mmio-up.log:FAIL: gicv2: mmio: ITARGETSR: register content
> preserved (01010001 => )
> logs/gicv2-mmio-up.log:FAIL: gicv2: mmio: ITARGETSR: byte writes successful
> (0x1f => 0x)
Haven't looked at the tests or the GIC code, but I'm guessing from
the logs that these are the usual tendency of and our device models
to implement "bits that should be reserved" in registers as
reads-as-written, relying on the guest code not to set them.
This is strictly incorrect (the GICv2 spec says implementations
must make RAZ/WI bits really read-as-zero) but it seems unlikely
to trip up real world code.
I'm happy to review a patch if somebody wants to write one.
thanks
-- PMM
