From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.inc.c | 507 ++--
1 file changed, 308 insertions(+), 199 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 1cc58c86b2..fc1908389e 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -19,6 +19,59 @@
#include "tcg/tcg-gvec-desc.h"
#include "internals.h"
+#define NVPR32
+
+#define require(x) if (unlikely(!(x))) { return false; }
+#define require_align(val, pos) require(is_aligned(val, pos))
+
+/* Destination vector register group cannot overlap source mask register. */
+#define require_vm(vm, rd) do { if (vm == 0) require(rd != 0); } while (0)
+
+#define require_noover(astart, asize, bstart, bsize) \
+ require(!is_overlapped(astart, asize, bstart, bsize))
+#define require_noover_widen(astart, asize, bstart, bsize) \
+ require(!is_overlapped_widen(astart, asize, bstart, bsize))
+
+#define REQUIRE_RVV do {\
+if (s->mstatus_vs == 0) \
+return false; \
+} while (0)
+
+static inline bool is_aligned(const unsigned val, const unsigned pos)
+{
+return pos ? (val & (pos - 1)) == 0 : true;
+}
+
+static inline bool is_overlapped(const int astart, int asize,
+ const int bstart, int bsize)
+{
+asize = asize == 0 ? 1 : asize;
+bsize = bsize == 0 ? 1 : bsize;
+
+const int aend = astart + asize;
+const int bend = bstart + bsize;
+
+return MAX(aend, bend) - MIN(astart, bstart) < asize + bsize;
+}
+
+static inline bool is_overlapped_widen(const int astart, int asize,
+ const int bstart, int bsize)
+{
+asize = asize == 0 ? 1 : asize;
+bsize = bsize == 0 ? 1 : bsize;
+
+const int aend = astart + asize;
+const int bend = bstart + bsize;
+
+if (astart < bstart &&
+is_overlapped(astart, asize, bstart, bsize) &&
+!is_overlapped(astart, asize, bstart + bsize, bsize)) {
+return false;
+} else {
+return MAX(aend, bend) - MIN(astart, bstart) < asize + bsize;
+}
+}
+
static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
{
TCGv s1, s2, dst;
@@ -103,29 +156,121 @@ static bool vext_check_isa_ill(DisasContext *s)
}
/*
- * There are two rules check here.
+ * Check function for vector instruction with format:
+ * single-width result and single-width sources (SEW = SEW op SEW)
+ *
+ * is_vs1: indicates whether insn[19:15] is a vs1 field or not.
+ */
+#define VEXT_CHECK_SSS(s, rd, rs1, rs2, vm, is_vs1) do { \
+require_vm(vm, rd); \
+if (s->flmul > 1) { \
+require_align(rd, s->flmul); \
+require_align(rs2, s->flmul);\
+if (is_vs1) {\
+require_align(rs1, s->flmul);\
+}\
+}\
+} while (0)
+
+/*
+ * Check function for maskable vector instruction with format:
+ * single-width result and single-width sources (SEW = SEW op SEW)
*
- * 1. Vector register numbers are multiples of LMUL. (Section 3.2)
+ * is_vs1: indicates whether insn[19:15] is a vs1 field or not.
+ */
+#define VEXT_CHECK_MSS(s, rd, rs1, rs2, is_vs1) do { \
+if (rd != rs2) { \
+require_noover(rd, 1, rs2, s->flmul);\
+}\
+require_align(rs2, s->flmul);\
+if (is_vs1) {\
+if (rd != rs1) { \
+require_noover(rd, 1, rs1, s->flmul);\
+}\
+require_align(rs1, s->flmul);\
+}\
+} while (0)
+
+/* Common check function for vector widening instructions */
+#define VEXT_WIDE_CHECK_COMMON(s, rd, vm) do { \
+require(s->flmul <= 4);\
+require(s->sew < 3); \
+require_align(rd, s->flmul * 2); \
+require_vm(vm, rd);\
+} while (0)
+
+/* Common check function for vector narrowing instructions */
+#define VEXT_NARROW_CHECK_COMMON(s, rd, rs2, vm) do { \
+require(s->flmul <= 4); \
+require(s->sew < 3); \
+require_align(rs2, s->flmul * 2); \
+require_align(rd, s->flmul); \
+require_vm(vm, rd); \
+} while (0)
+
+/*
+ * Check function for vector instruction with format:
+ * double-width result and single-width sources (2*SEW = SEW op SEW)
*
- * 2. For all widening instructions, the destination LMUL value must also be
-
