Re: [RFC PATCH v3 12/21] target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64()
On 2/23/24 00:32, Jinjie Ruan via wrote: According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt with superpriority is always IRQ, never FIQ, so the NMI exception trap entry behave like IRQ. Signed-off-by: Jinjie Ruan --- v3: - Remove the FIQ NMI handle. --- target/arm/helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0a69638651..1a5e992d26 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11452,6 +11452,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) break; case EXCP_IRQ: case EXCP_VIRQ: +case EXCP_NMI: addr += 0x80; break; case EXCP_FIQ: Handle EXCP_VNMI. r~
[RFC PATCH v3 12/21] target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64()
According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt with superpriority is always IRQ, never FIQ, so the NMI exception trap entry behave like IRQ. Signed-off-by: Jinjie Ruan --- v3: - Remove the FIQ NMI handle. --- target/arm/helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0a69638651..1a5e992d26 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11452,6 +11452,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) break; case EXCP_IRQ: case EXCP_VIRQ: +case EXCP_NMI: addr += 0x80; break; case EXCP_FIQ: -- 2.34.1
