Re: [RFC PATCH v4 03/30] target/loongarch: Add basic vmstate description of CPU.

2022-01-27 Thread yangxiaojuan 
Hi, Mark

在 2022年01月15日 20:52, Mark Cave-Ayland 写道:
> On 08/01/2022 09:13, Xiaojuan Yang wrote:
> 
>> This patch introduce vmstate_loongarch_cpu
>>
>> Signed-off-by: Xiaojuan Yang 
>> Signed-off-by: Song Gao 
>> Reviewed-by: Richard Henderson 
>> ---
>>   target/loongarch/cpu.c   |  3 ++
>>   target/loongarch/internals.h |  4 ++
>>   target/loongarch/machine.c   | 84 
>>   target/loongarch/meson.build |  6 +++
>>   4 files changed, 97 insertions(+)
>>   create mode 100644 target/loongarch/machine.c
>>
>> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
>> index ed03ec2986..6e3dc5e6fa 100644
>> --- a/target/loongarch/cpu.c
>> +++ b/target/loongarch/cpu.c
>> @@ -320,6 +320,9 @@ static void loongarch_cpu_class_init(ObjectClass *c, 
>> void *data)
>>   cc->has_work = loongarch_cpu_has_work;
>>   cc->dump_state = loongarch_cpu_dump_state;
>>   cc->set_pc = loongarch_cpu_set_pc;
>> +#ifndef CONFIG_USER_ONLY
>> +dc->vmsd = &vmstate_loongarch_cpu;
>> +#endif
> 
> Do we need CONFIG_USER_ONLY guards around dc->vmsd? I'd expect this to simply 
> be ignored in linux-user mode. Again it's a bit hard to see the full context 
> without having the complete series available in git somewhere.

I have reorganized the patch and prepare to send the V5 patch.
Here we define the vmsd struct in the machine.c which only used by system mode. 
So we need the CONFIG_USER_ONLY.

You can get LoongArch qemu series code like this:
git clone https://github.com/loongson/qemu.git
git checkout branch tcg-dev

xiaojuan,
thanks 

> 
>>   cc->disas_set_info = loongarch_cpu_disas_set_info;
>>   #ifdef CONFIG_TCG
>>   cc->tcg_ops = &loongarch_tcg_ops;
>> diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
>> index 774a87ec80..c8e6f7012c 100644
>> --- a/target/loongarch/internals.h
>> +++ b/target/loongarch/internals.h
>> @@ -25,4 +25,8 @@ const char *loongarch_exception_name(int32_t exception);
>> void restore_fp_status(CPULoongArchState *env);
>>   +#ifndef CONFIG_USER_ONLY
>> +extern const VMStateDescription vmstate_loongarch_cpu;
>> +#endif
>> +
>>   #endif
>> diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c
>> new file mode 100644
>> index 00..b9effe6db2
>> --- /dev/null
>> +++ b/target/loongarch/machine.c
>> @@ -0,0 +1,84 @@
>> +/* SPDX-License-Identifier: GPL-2.0-or-later */
>> +/*
>> + * QEMU LoongArch machine State
>> + *
>> + * Copyright (c) 2021 Loongson Technology Corporation Limited
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "cpu.h"
>> +#include "migration/cpu.h"
>> +
>> +/* LoongArch CPU state */
>> +
>> +const VMStateDescription vmstate_loongarch_cpu = {
>> +.name = "cpu",
>> +.version_id = 0,
>> +.minimum_version_id = 0,
>> +.fields = (VMStateField[]) {
>> +
>> +VMSTATE_UINTTL_ARRAY(env.gpr, LoongArchCPU, 32),
>> +VMSTATE_UINTTL(env.pc, LoongArchCPU),
>> +VMSTATE_UINT64_ARRAY(env.fpr, LoongArchCPU, 32),
>> +VMSTATE_UINT32(env.fcsr0, LoongArchCPU),
>> +
>> +/* Remaining CSR registers */
>> +VMSTATE_UINT64(env.CSR_CRMD, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_PRMD, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_EUEN, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_MISC, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_ECFG, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_ESTAT, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_ERA, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_BADV, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_BADI, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_EENTRY, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_TLBIDX, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_TLBEHI, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_TLBELO0, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_TLBELO1, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_ASID, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_PGDL, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_PGDH, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_PGD, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_PWCL, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_PWCH, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_STLBPS, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_RVACFG, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_CPUID, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_PRCFG1, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_PRCFG2, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_PRCFG3, LoongArchCPU),
>> +VMSTATE_UINT64_ARRAY(env.CSR_SAVE, LoongArchCPU, 16),
>> +VMSTATE_UINT64(env.CSR_TID, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_TCFG, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_TVAL, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_CNTC, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_TICLR, LoongArchCPU),
>> +VMSTATE_UINT64(env.CSR_LLBCTL, LoongArchCPU),

Re: [RFC PATCH v4 03/30] target/loongarch: Add basic vmstate description of CPU.

2022-01-15 Thread Mark Cave-Ayland 

On 08/01/2022 09:13, Xiaojuan Yang wrote:


This patch introduce vmstate_loongarch_cpu

Signed-off-by: Xiaojuan Yang 
Signed-off-by: Song Gao 
Reviewed-by: Richard Henderson 
---
  target/loongarch/cpu.c   |  3 ++
  target/loongarch/internals.h |  4 ++
  target/loongarch/machine.c   | 84 
  target/loongarch/meson.build |  6 +++
  4 files changed, 97 insertions(+)
  create mode 100644 target/loongarch/machine.c

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index ed03ec2986..6e3dc5e6fa 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -320,6 +320,9 @@ static void loongarch_cpu_class_init(ObjectClass *c, void 
*data)
  cc->has_work = loongarch_cpu_has_work;
  cc->dump_state = loongarch_cpu_dump_state;
  cc->set_pc = loongarch_cpu_set_pc;
+#ifndef CONFIG_USER_ONLY
+dc->vmsd = &vmstate_loongarch_cpu;
+#endif


Do we need CONFIG_USER_ONLY guards around dc->vmsd? I'd expect this to simply be 
ignored in linux-user mode. Again it's a bit hard to see the full context without 
having the complete series available in git somewhere.



  cc->disas_set_info = loongarch_cpu_disas_set_info;
  #ifdef CONFIG_TCG
  cc->tcg_ops = &loongarch_tcg_ops;
diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
index 774a87ec80..c8e6f7012c 100644
--- a/target/loongarch/internals.h
+++ b/target/loongarch/internals.h
@@ -25,4 +25,8 @@ const char *loongarch_exception_name(int32_t exception);
  
  void restore_fp_status(CPULoongArchState *env);
  
+#ifndef CONFIG_USER_ONLY

+extern const VMStateDescription vmstate_loongarch_cpu;
+#endif
+
  #endif
diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c
new file mode 100644
index 00..b9effe6db2
--- /dev/null
+++ b/target/loongarch/machine.c
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU LoongArch machine State
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "migration/cpu.h"
+
+/* LoongArch CPU state */
+
+const VMStateDescription vmstate_loongarch_cpu = {
+.name = "cpu",
+.version_id = 0,
+.minimum_version_id = 0,
+.fields = (VMStateField[]) {
+
+VMSTATE_UINTTL_ARRAY(env.gpr, LoongArchCPU, 32),
+VMSTATE_UINTTL(env.pc, LoongArchCPU),
+VMSTATE_UINT64_ARRAY(env.fpr, LoongArchCPU, 32),
+VMSTATE_UINT32(env.fcsr0, LoongArchCPU),
+
+/* Remaining CSR registers */
+VMSTATE_UINT64(env.CSR_CRMD, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_PRMD, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_EUEN, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_MISC, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_ECFG, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_ESTAT, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_ERA, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_BADV, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_BADI, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_EENTRY, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBIDX, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBEHI, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBELO0, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBELO1, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_ASID, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_PGDL, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_PGDH, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_PGD, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_PWCL, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_PWCH, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_STLBPS, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_RVACFG, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_CPUID, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_PRCFG1, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_PRCFG2, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_PRCFG3, LoongArchCPU),
+VMSTATE_UINT64_ARRAY(env.CSR_SAVE, LoongArchCPU, 16),
+VMSTATE_UINT64(env.CSR_TID, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TCFG, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TVAL, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_CNTC, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TICLR, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_LLBCTL, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_IMPCTL1, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_IMPCTL2, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBRENTRY, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBRBADV, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBRERA, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBRSAVE, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBRELO0, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBRELO1, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBREHI, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBRPRMD, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_MERRCTL, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_MERRINFO1, LoongArchCPU),
+VMSTATE

Re: [RFC PATCH v4 03/30] target/loongarch: Add basic vmstate description of CPU.

2022-01-09 Thread WANG Xuerui 



On 1/8/22 17:13, Xiaojuan Yang wrote:

This patch introduce vmstate_loongarch_cpu

Again, pointless commit message.

Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
  target/loongarch/cpu.c   |  3 ++
  target/loongarch/internals.h |  4 ++
  target/loongarch/machine.c   | 84 
  target/loongarch/meson.build |  6 +++
  4 files changed, 97 insertions(+)
  create mode 100644 target/loongarch/machine.c

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index ed03ec2986..6e3dc5e6fa 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -320,6 +320,9 @@ static void loongarch_cpu_class_init(ObjectClass *c, void 
*data)
  cc->has_work = loongarch_cpu_has_work;
  cc->dump_state = loongarch_cpu_dump_state;
  cc->set_pc = loongarch_cpu_set_pc;
+#ifndef CONFIG_USER_ONLY
+dc->vmsd = &vmstate_loongarch_cpu;
+#endif
  cc->disas_set_info = loongarch_cpu_disas_set_info;
  #ifdef CONFIG_TCG
  cc->tcg_ops = &loongarch_tcg_ops;
diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
index 774a87ec80..c8e6f7012c 100644
--- a/target/loongarch/internals.h
+++ b/target/loongarch/internals.h
@@ -25,4 +25,8 @@ const char *loongarch_exception_name(int32_t exception);
  
  void restore_fp_status(CPULoongArchState *env);
  
+#ifndef CONFIG_USER_ONLY

+extern const VMStateDescription vmstate_loongarch_cpu;
+#endif
+
  #endif
diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c
new file mode 100644
index 00..b9effe6db2
--- /dev/null
+++ b/target/loongarch/machine.c
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU LoongArch machine State

Use consistent casing; "machine state" or "Machine State".

+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "migration/cpu.h"
+
+/* LoongArch CPU state */
+
+const VMStateDescription vmstate_loongarch_cpu = {
+.name = "cpu",
+.version_id = 0,
+.minimum_version_id = 0,
+.fields = (VMStateField[]) {
+
+VMSTATE_UINTTL_ARRAY(env.gpr, LoongArchCPU, 32),
+VMSTATE_UINTTL(env.pc, LoongArchCPU),
+VMSTATE_UINT64_ARRAY(env.fpr, LoongArchCPU, 32),
+VMSTATE_UINT32(env.fcsr0, LoongArchCPU),
+
+/* Remaining CSR registers */

"Remaining CSRs"

+VMSTATE_UINT64(env.CSR_CRMD, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_PRMD, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_EUEN, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_MISC, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_ECFG, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_ESTAT, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_ERA, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_BADV, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_BADI, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_EENTRY, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBIDX, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBEHI, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBELO0, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBELO1, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_ASID, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_PGDL, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_PGDH, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_PGD, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_PWCL, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_PWCH, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_STLBPS, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_RVACFG, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_CPUID, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_PRCFG1, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_PRCFG2, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_PRCFG3, LoongArchCPU),
+VMSTATE_UINT64_ARRAY(env.CSR_SAVE, LoongArchCPU, 16),
+VMSTATE_UINT64(env.CSR_TID, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TCFG, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TVAL, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_CNTC, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TICLR, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_LLBCTL, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_IMPCTL1, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_IMPCTL2, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBRENTRY, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBRBADV, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBRERA, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBRSAVE, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBRELO0, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBRELO1, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBREHI, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBRPRMD, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_MERRCTL, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_MERRINFO1, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_MERRINFO2, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_MERRENTRY, LoongArchCPU),
+VMSTATE_

[RFC PATCH v4 03/30] target/loongarch: Add basic vmstate description of CPU.

2022-01-08 Thread Xiaojuan Yang 
This patch introduce vmstate_loongarch_cpu

Signed-off-by: Xiaojuan Yang 
Signed-off-by: Song Gao 
Reviewed-by: Richard Henderson 
---
 target/loongarch/cpu.c   |  3 ++
 target/loongarch/internals.h |  4 ++
 target/loongarch/machine.c   | 84 
 target/loongarch/meson.build |  6 +++
 4 files changed, 97 insertions(+)
 create mode 100644 target/loongarch/machine.c

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index ed03ec2986..6e3dc5e6fa 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -320,6 +320,9 @@ static void loongarch_cpu_class_init(ObjectClass *c, void 
*data)
 cc->has_work = loongarch_cpu_has_work;
 cc->dump_state = loongarch_cpu_dump_state;
 cc->set_pc = loongarch_cpu_set_pc;
+#ifndef CONFIG_USER_ONLY
+dc->vmsd = &vmstate_loongarch_cpu;
+#endif
 cc->disas_set_info = loongarch_cpu_disas_set_info;
 #ifdef CONFIG_TCG
 cc->tcg_ops = &loongarch_tcg_ops;
diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
index 774a87ec80..c8e6f7012c 100644
--- a/target/loongarch/internals.h
+++ b/target/loongarch/internals.h
@@ -25,4 +25,8 @@ const char *loongarch_exception_name(int32_t exception);
 
 void restore_fp_status(CPULoongArchState *env);
 
+#ifndef CONFIG_USER_ONLY
+extern const VMStateDescription vmstate_loongarch_cpu;
+#endif
+
 #endif
diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c
new file mode 100644
index 00..b9effe6db2
--- /dev/null
+++ b/target/loongarch/machine.c
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU LoongArch machine State
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "migration/cpu.h"
+
+/* LoongArch CPU state */
+
+const VMStateDescription vmstate_loongarch_cpu = {
+.name = "cpu",
+.version_id = 0,
+.minimum_version_id = 0,
+.fields = (VMStateField[]) {
+
+VMSTATE_UINTTL_ARRAY(env.gpr, LoongArchCPU, 32),
+VMSTATE_UINTTL(env.pc, LoongArchCPU),
+VMSTATE_UINT64_ARRAY(env.fpr, LoongArchCPU, 32),
+VMSTATE_UINT32(env.fcsr0, LoongArchCPU),
+
+/* Remaining CSR registers */
+VMSTATE_UINT64(env.CSR_CRMD, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_PRMD, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_EUEN, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_MISC, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_ECFG, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_ESTAT, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_ERA, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_BADV, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_BADI, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_EENTRY, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBIDX, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBEHI, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBELO0, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBELO1, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_ASID, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_PGDL, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_PGDH, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_PGD, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_PWCL, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_PWCH, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_STLBPS, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_RVACFG, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_CPUID, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_PRCFG1, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_PRCFG2, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_PRCFG3, LoongArchCPU),
+VMSTATE_UINT64_ARRAY(env.CSR_SAVE, LoongArchCPU, 16),
+VMSTATE_UINT64(env.CSR_TID, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TCFG, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TVAL, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_CNTC, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TICLR, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_LLBCTL, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_IMPCTL1, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_IMPCTL2, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBRENTRY, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBRBADV, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBRERA, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBRSAVE, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBRELO0, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBRELO1, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBREHI, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_TLBRPRMD, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_MERRCTL, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_MERRINFO1, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_MERRINFO2, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_MERRENTRY, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_MERRERA, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_MERRSAVE, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_CTAG, LoongArchCPU),
+VMSTATE_UINT