subject:"\[RFC v3\] linux\-user\/riscv\: Add syscall riscv

Re: [RFC v3] linux-user/riscv: Add syscall riscv_hwprobe

2023-06-18 Thread Robbin Ehn

On Thu, 2023-06-15 at 10:12 -0700, Palmer Dabbelt wrote:
> On Thu, 08 Jun 2023 00:55:22 PDT (-0700), r...@rivosinc.com wrote:
> > This patch adds the new syscall for the
> > "RISC-V Hardware Probing Interface"
> > (https://docs.kernel.org/riscv/hwprobe.html).
> > 
> > Signed-off-by: Robbin Ehn 
> > ---
> > v1->v2: Moved to syscall.c
> > v2->v3: Separate function, get/put user
> > ---
> >  linux-user/riscv/syscall32_nr.h |   1 +
> >  linux-user/riscv/syscall64_nr.h |   1 +
> >  linux-user/syscall.c| 146 
> >  3 files changed, 148 insertions(+)
> > 
> > diff --git a/linux-user/riscv/syscall32_nr.h 
> > b/linux-user/riscv/syscall32_nr.h
> > index 1327d7dffa..412e58e5b2 100644
> > --- a/linux-user/riscv/syscall32_nr.h
> > +++ b/linux-user/riscv/syscall32_nr.h
> > @@ -228,6 +228,7 @@
> >  #define TARGET_NR_accept4 242
> >  #define TARGET_NR_arch_specific_syscall 244
> >  #define TARGET_NR_riscv_flush_icache (TARGET_NR_arch_specific_syscall + 15)
> > +#define TARGET_NR_riscv_hwprobe (TARGET_NR_arch_specific_syscall + 14)
> >  #define TARGET_NR_prlimit64 261
> >  #define TARGET_NR_fanotify_init 262
> >  #define TARGET_NR_fanotify_mark 263
> > diff --git a/linux-user/riscv/syscall64_nr.h 
> > b/linux-user/riscv/syscall64_nr.h
> > index 6659751933..29e1eb2075 100644
> > --- a/linux-user/riscv/syscall64_nr.h
> > +++ b/linux-user/riscv/syscall64_nr.h
> > @@ -251,6 +251,7 @@
> >  #define TARGET_NR_recvmmsg 243
> >  #define TARGET_NR_arch_specific_syscall 244
> >  #define TARGET_NR_riscv_flush_icache (TARGET_NR_arch_specific_syscall + 15)
> > +#define TARGET_NR_riscv_hwprobe (TARGET_NR_arch_specific_syscall + 14)
> >  #define TARGET_NR_wait4 260
> >  #define TARGET_NR_prlimit64 261
> >  #define TARGET_NR_fanotify_init 262
> > diff --git a/linux-user/syscall.c b/linux-user/syscall.c
> > index 83685f0aa5..e8859cd3be 100644
> > --- a/linux-user/syscall.c
> > +++ b/linux-user/syscall.c
> > @@ -8874,6 +8874,147 @@ static int do_getdents64(abi_long dirfd, abi_long 
> > arg2, abi_long count)
> >  }
> >  #endif /* TARGET_NR_getdents64 */
> >  
> > +#if defined(TARGET_NR_riscv_hwprobe)
> > +
> > +#define RISCV_HWPROBE_KEY_MVENDORID 0
> > +#define RISCV_HWPROBE_KEY_MARCHID   1
> > +#define RISCV_HWPROBE_KEY_MIMPID2
> > +
> > +#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3
> > +#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0)
> > +
> > +#define RISCV_HWPROBE_KEY_IMA_EXT_0 4
> > +#define RISCV_HWPROBE_IMA_FD   (1 << 0)
> > +#define RISCV_HWPROBE_IMA_C(1 << 1)
> > +
> > +#define RISCV_HWPROBE_KEY_CPUPERF_0 5
> > +#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
> > +#define RISCV_HWPROBE_MISALIGNED_EMULATED(1 << 0)
> > +#define RISCV_HWPROBE_MISALIGNED_SLOW(2 << 0)
> > +#define RISCV_HWPROBE_MISALIGNED_FAST(3 << 0)
> > +#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0)
> > +#define RISCV_HWPROBE_MISALIGNED_MASK(7 << 0)
> > +
> > +struct riscv_hwprobe {
> > +abi_llong  key;
> > +abi_ullong value;
> > +};
> > +
> > +static void risc_hwprobe_fill_pairs(CPURISCVState *env,
> > +struct riscv_hwprobe *pair,
> > +size_t pair_count)
> > +{
> > +const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
> > +
> > +for (; pair_count > 0; pair_count--, pair++) {
> > +abi_llong key;
> > +abi_ullong value;
> > +__put_user(0, &pair->value);
> > +__get_user(key, &pair->key);
> > +switch (key) {
> > +case RISCV_HWPROBE_KEY_MVENDORID:
> > +__put_user(cfg->mvendorid, &pair->value);
> > +break;
> > +case RISCV_HWPROBE_KEY_MARCHID:
> > +__put_user(cfg->marchid, &pair->value);
> > +break;
> > +case RISCV_HWPROBE_KEY_MIMPID:
> > +__put_user(cfg->mimpid, &pair->value);
> > +break;
> > +case RISCV_HWPROBE_KEY_BASE_BEHAVIOR:
> > +value = riscv_has_ext(env, RVI) &&
> > +riscv_has_ext(env, RVM) &&
> > +riscv_has_ext(env, RVA) ?
> > +RISCV_HWPROBE_BASE_BEHAVIOR_IMA : 0;
> > +__put_user(value, &pair->value);
> > +break;
> > +case RISCV_HWPROBE_KEY_IMA_EXT_0:
> > +value = riscv_has_ext(env, RVF) &&
> > +riscv_has_ext(env, RVD) ?
> > +RISCV_HWPROBE_IMA_FD : 0;
> > +value |= riscv_has_ext(env, RVC) ?
> > + RISCV_HWPROBE_IMA_C : pair->value;
> > +__put_user(value, &pair->value);
> > +break;
> > +case RISCV_HWPROBE_KEY_CPUPERF_0:
> > +__put_user(RISCV_HWPROBE_MISALIGNED_FAST, &pair->value);
> > +break;
> > +default:
> > +__put_user(-1, &pair->key);
> > +break;
> > +}
> > +}
> > +}
> > +
> > +static int cpu_set_valid(abi_

Re: [RFC v3] linux-user/riscv: Add syscall riscv_hwprobe

2023-06-15 Thread Palmer Dabbelt

On Thu, 08 Jun 2023 00:55:22 PDT (-0700), r...@rivosinc.com wrote:
> This patch adds the new syscall for the
> "RISC-V Hardware Probing Interface"
> (https://docs.kernel.org/riscv/hwprobe.html).
>
> Signed-off-by: Robbin Ehn 
> ---
> v1->v2: Moved to syscall.c
> v2->v3: Separate function, get/put user
> ---
>  linux-user/riscv/syscall32_nr.h |   1 +
>  linux-user/riscv/syscall64_nr.h |   1 +
>  linux-user/syscall.c| 146 
>  3 files changed, 148 insertions(+)
>
> diff --git a/linux-user/riscv/syscall32_nr.h b/linux-user/riscv/syscall32_nr.h
> index 1327d7dffa..412e58e5b2 100644
> --- a/linux-user/riscv/syscall32_nr.h
> +++ b/linux-user/riscv/syscall32_nr.h
> @@ -228,6 +228,7 @@
>  #define TARGET_NR_accept4 242
>  #define TARGET_NR_arch_specific_syscall 244
>  #define TARGET_NR_riscv_flush_icache (TARGET_NR_arch_specific_syscall + 15)
> +#define TARGET_NR_riscv_hwprobe (TARGET_NR_arch_specific_syscall + 14)
>  #define TARGET_NR_prlimit64 261
>  #define TARGET_NR_fanotify_init 262
>  #define TARGET_NR_fanotify_mark 263
> diff --git a/linux-user/riscv/syscall64_nr.h b/linux-user/riscv/syscall64_nr.h
> index 6659751933..29e1eb2075 100644
> --- a/linux-user/riscv/syscall64_nr.h
> +++ b/linux-user/riscv/syscall64_nr.h
> @@ -251,6 +251,7 @@
>  #define TARGET_NR_recvmmsg 243
>  #define TARGET_NR_arch_specific_syscall 244
>  #define TARGET_NR_riscv_flush_icache (TARGET_NR_arch_specific_syscall + 15)
> +#define TARGET_NR_riscv_hwprobe (TARGET_NR_arch_specific_syscall + 14)
>  #define TARGET_NR_wait4 260
>  #define TARGET_NR_prlimit64 261
>  #define TARGET_NR_fanotify_init 262
> diff --git a/linux-user/syscall.c b/linux-user/syscall.c
> index 83685f0aa5..e8859cd3be 100644
> --- a/linux-user/syscall.c
> +++ b/linux-user/syscall.c
> @@ -8874,6 +8874,147 @@ static int do_getdents64(abi_long dirfd, abi_long 
> arg2, abi_long count)
>  }
>  #endif /* TARGET_NR_getdents64 */
>  
> +#if defined(TARGET_NR_riscv_hwprobe)
> +
> +#define RISCV_HWPROBE_KEY_MVENDORID 0
> +#define RISCV_HWPROBE_KEY_MARCHID   1
> +#define RISCV_HWPROBE_KEY_MIMPID2
> +
> +#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3
> +#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0)
> +
> +#define RISCV_HWPROBE_KEY_IMA_EXT_0 4
> +#define RISCV_HWPROBE_IMA_FD   (1 << 0)
> +#define RISCV_HWPROBE_IMA_C(1 << 1)
> +
> +#define RISCV_HWPROBE_KEY_CPUPERF_0 5
> +#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
> +#define RISCV_HWPROBE_MISALIGNED_EMULATED(1 << 0)
> +#define RISCV_HWPROBE_MISALIGNED_SLOW(2 << 0)
> +#define RISCV_HWPROBE_MISALIGNED_FAST(3 << 0)
> +#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0)
> +#define RISCV_HWPROBE_MISALIGNED_MASK(7 << 0)
> +
> +struct riscv_hwprobe {
> +abi_llong  key;
> +abi_ullong value;
> +};
> +
> +static void risc_hwprobe_fill_pairs(CPURISCVState *env,
> +struct riscv_hwprobe *pair,
> +size_t pair_count)
> +{
> +const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
> +
> +for (; pair_count > 0; pair_count--, pair++) {
> +abi_llong key;
> +abi_ullong value;
> +__put_user(0, &pair->value);
> +__get_user(key, &pair->key);
> +switch (key) {
> +case RISCV_HWPROBE_KEY_MVENDORID:
> +__put_user(cfg->mvendorid, &pair->value);
> +break;
> +case RISCV_HWPROBE_KEY_MARCHID:
> +__put_user(cfg->marchid, &pair->value);
> +break;
> +case RISCV_HWPROBE_KEY_MIMPID:
> +__put_user(cfg->mimpid, &pair->value);
> +break;
> +case RISCV_HWPROBE_KEY_BASE_BEHAVIOR:
> +value = riscv_has_ext(env, RVI) &&
> +riscv_has_ext(env, RVM) &&
> +riscv_has_ext(env, RVA) ?
> +RISCV_HWPROBE_BASE_BEHAVIOR_IMA : 0;
> +__put_user(value, &pair->value);
> +break;
> +case RISCV_HWPROBE_KEY_IMA_EXT_0:
> +value = riscv_has_ext(env, RVF) &&
> +riscv_has_ext(env, RVD) ?
> +RISCV_HWPROBE_IMA_FD : 0;
> +value |= riscv_has_ext(env, RVC) ?
> + RISCV_HWPROBE_IMA_C : pair->value;
> +__put_user(value, &pair->value);
> +break;
> +case RISCV_HWPROBE_KEY_CPUPERF_0:
> +__put_user(RISCV_HWPROBE_MISALIGNED_FAST, &pair->value);
> +break;
> +default:
> +__put_user(-1, &pair->key);
> +break;
> +}
> +}
> +}
> +
> +static int cpu_set_valid(abi_long arg3, abi_long arg4)
> +{
> +int ret, i, tmp;
> +size_t host_mask_size, target_mask_size;
> +unsigned long *host_mask;
> +
> +/*
> + * cpu_set_t represent CPU masks as bit masks of type unsigned long *.
> + * arg3 contains the cpu count.
> + */
> +tmp = (8 * sizeof(abi_ulon

[RFC v3] linux-user/riscv: Add syscall riscv_hwprobe

2023-06-08 Thread Robbin Ehn

This patch adds the new syscall for the
"RISC-V Hardware Probing Interface"
(https://docs.kernel.org/riscv/hwprobe.html).

Signed-off-by: Robbin Ehn 
---
v1->v2: Moved to syscall.c
v2->v3: Separate function, get/put user
---
 linux-user/riscv/syscall32_nr.h |   1 +
 linux-user/riscv/syscall64_nr.h |   1 +
 linux-user/syscall.c| 146 
 3 files changed, 148 insertions(+)

diff --git a/linux-user/riscv/syscall32_nr.h b/linux-user/riscv/syscall32_nr.h
index 1327d7dffa..412e58e5b2 100644
--- a/linux-user/riscv/syscall32_nr.h
+++ b/linux-user/riscv/syscall32_nr.h
@@ -228,6 +228,7 @@
 #define TARGET_NR_accept4 242
 #define TARGET_NR_arch_specific_syscall 244
 #define TARGET_NR_riscv_flush_icache (TARGET_NR_arch_specific_syscall + 15)
+#define TARGET_NR_riscv_hwprobe (TARGET_NR_arch_specific_syscall + 14)
 #define TARGET_NR_prlimit64 261
 #define TARGET_NR_fanotify_init 262
 #define TARGET_NR_fanotify_mark 263
diff --git a/linux-user/riscv/syscall64_nr.h b/linux-user/riscv/syscall64_nr.h
index 6659751933..29e1eb2075 100644
--- a/linux-user/riscv/syscall64_nr.h
+++ b/linux-user/riscv/syscall64_nr.h
@@ -251,6 +251,7 @@
 #define TARGET_NR_recvmmsg 243
 #define TARGET_NR_arch_specific_syscall 244
 #define TARGET_NR_riscv_flush_icache (TARGET_NR_arch_specific_syscall + 15)
+#define TARGET_NR_riscv_hwprobe (TARGET_NR_arch_specific_syscall + 14)
 #define TARGET_NR_wait4 260
 #define TARGET_NR_prlimit64 261
 #define TARGET_NR_fanotify_init 262
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 83685f0aa5..e8859cd3be 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -8874,6 +8874,147 @@ static int do_getdents64(abi_long dirfd, abi_long arg2, 
abi_long count)
 }
 #endif /* TARGET_NR_getdents64 */
 
+#if defined(TARGET_NR_riscv_hwprobe)
+
+#define RISCV_HWPROBE_KEY_MVENDORID 0
+#define RISCV_HWPROBE_KEY_MARCHID   1
+#define RISCV_HWPROBE_KEY_MIMPID2
+
+#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3
+#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0)
+
+#define RISCV_HWPROBE_KEY_IMA_EXT_0 4
+#define RISCV_HWPROBE_IMA_FD   (1 << 0)
+#define RISCV_HWPROBE_IMA_C(1 << 1)
+
+#define RISCV_HWPROBE_KEY_CPUPERF_0 5
+#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
+#define RISCV_HWPROBE_MISALIGNED_EMULATED(1 << 0)
+#define RISCV_HWPROBE_MISALIGNED_SLOW(2 << 0)
+#define RISCV_HWPROBE_MISALIGNED_FAST(3 << 0)
+#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0)
+#define RISCV_HWPROBE_MISALIGNED_MASK(7 << 0)
+
+struct riscv_hwprobe {
+abi_llong  key;
+abi_ullong value;
+};
+
+static void risc_hwprobe_fill_pairs(CPURISCVState *env,
+struct riscv_hwprobe *pair,
+size_t pair_count)
+{
+const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
+
+for (; pair_count > 0; pair_count--, pair++) {
+abi_llong key;
+abi_ullong value;
+__put_user(0, &pair->value);
+__get_user(key, &pair->key);
+switch (key) {
+case RISCV_HWPROBE_KEY_MVENDORID:
+__put_user(cfg->mvendorid, &pair->value);
+break;
+case RISCV_HWPROBE_KEY_MARCHID:
+__put_user(cfg->marchid, &pair->value);
+break;
+case RISCV_HWPROBE_KEY_MIMPID:
+__put_user(cfg->mimpid, &pair->value);
+break;
+case RISCV_HWPROBE_KEY_BASE_BEHAVIOR:
+value = riscv_has_ext(env, RVI) &&
+riscv_has_ext(env, RVM) &&
+riscv_has_ext(env, RVA) ?
+RISCV_HWPROBE_BASE_BEHAVIOR_IMA : 0;
+__put_user(value, &pair->value);
+break;
+case RISCV_HWPROBE_KEY_IMA_EXT_0:
+value = riscv_has_ext(env, RVF) &&
+riscv_has_ext(env, RVD) ?
+RISCV_HWPROBE_IMA_FD : 0;
+value |= riscv_has_ext(env, RVC) ?
+ RISCV_HWPROBE_IMA_C : pair->value;
+__put_user(value, &pair->value);
+break;
+case RISCV_HWPROBE_KEY_CPUPERF_0:
+__put_user(RISCV_HWPROBE_MISALIGNED_FAST, &pair->value);
+break;
+default:
+__put_user(-1, &pair->key);
+break;
+}
+}
+}
+
+static int cpu_set_valid(abi_long arg3, abi_long arg4)
+{
+int ret, i, tmp;
+size_t host_mask_size, target_mask_size;
+unsigned long *host_mask;
+
+/*
+ * cpu_set_t represent CPU masks as bit masks of type unsigned long *.
+ * arg3 contains the cpu count.
+ */
+tmp = (8 * sizeof(abi_ulong));
+target_mask_size = ((arg3 + tmp - 1) / tmp) * sizeof(abi_ulong);
+host_mask_size = (target_mask_size + (sizeof(*host_mask) - 1)) &
+ ~(sizeof(*host_mask) - 1);
+
+host_mask = alloca(host_mask_size);
+
+ret = target_to_host_cpu_mask(host_mask, host_mask_size,
+

Re: [RFC v3] linux-user/riscv: Add syscall riscv_hwprobe

Re: [RFC v3] linux-user/riscv: Add syscall riscv_hwprobe

[RFC v3] linux-user/riscv: Add syscall riscv_hwprobe

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