Re: [PATCH v4 12/16] aspeed/soc: Add AST2700 support
On 31/5/24 09:46, Cédric Le Goater wrote:
Hello Jamin,
I refer to versal_create_apu_gic function,
https://github.com/qemu/qemu/blob/master/hw/arm/xlnx-versal.c#L67
and updated aspeed_soc_ast2700_gic as following.
If you have any concerned about the new changes, please let me know.
Thanks-Jamin
static bool aspeed_soc_ast2700_gic(DeviceState *dev, Error **errp)
Please rename to aspeed_soc_ast2700_gic_realize()
{
Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
AspeedSoCState *s = ASPEED_SOC(dev);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
SysBusDevice *gicbusdev;
DeviceState *gicdev;
QList *redist_region_count;
int i;
object_initialize_child(OBJECT(a), "ast2700-gic", >gic,
gicv3_class_name());
and object_initialize_child() can be called in aspeed_soc_ast2700_init().
gicbusdev = SYS_BUS_DEVICE(>gic);
gicdev = DEVICE(>gic);
qdev_prop_set_uint32(gicdev, "revision", 3);
qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus);
qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ);
redist_region_count = qlist_new();
qlist_append_int(redist_region_count, sc->num_cpus);
qdev_prop_set_array(gicdev, "redist-region-count",
redist_region_count);
if (!sysbus_realize(gicbusdev, errp)) {
return false;
}
sysbus_mmio_map(gicbusdev, 0, sc->memmap[ASPEED_GIC_DIST]);
sysbus_mmio_map(gicbusdev, 1, sc->memmap[ASPEED_GIC_REDIST]);
for (i = 0; i < sc->num_cpus; i++) {
DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
Could we avoid qemu_get_cpu() and use the cpu array of the SoC instead ?
If it is too invasive, I might take care of it later when respinning
https://lore.kernel.org/qemu-devel/20231212162935.42910-1-phi...@linaro.org
RE: [PATCH v4 12/16] aspeed/soc: Add AST2700 support
Hi Cedric,
> From: Cédric Le Goater
> On 5/27/24 10:02, Jamin Lin wrote:
> > Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35
> CPU).
> >
> > AST2700 SOC and its interrupt controller are too complex to handle in
> > the common Aspeed SoC framework. We introduce a new ast2700 class with
> > instance_init and realize handlers.
> >
> > AST2700 is a 64 bits quad core cpus and support 8 watchdog.
> > Update maximum ASPEED_CPUS_NUM to 4 and ASPEED_WDTS_NUM to 8.
> > In addition, update AspeedSocState to support scuio, sli, sliio and intc.
> >
> > Add TYPE_ASPEED27X0_SOC machine type.
> >
> > The SDMC controller is unlocked at SPL stage.
> > At present, only supports to emulate booting start from u-boot stage.
> > Set SDMC controller unlocked by default.
> >
> > In INTC, each interrupt of INT 128 to INT 136 combines 32 interrupts.
> > It connect GICINT IRQ GPIO-OUTPUT pins to GIC device with irq 128 to 136.
> > And, if a device irq is 128 to 136, its irq GPIO-OUTPUT pin is
> > connected to GICINT or-gates instead of GIC device.
> >
> > Signed-off-by: Troy Lee
> > Signed-off-by: Jamin Lin
> > ---
> > hw/arm/aspeed_ast27x0.c | 563
>
> > hw/arm/meson.build | 1 +
> > include/hw/arm/aspeed_soc.h | 26 +-
> > 3 files changed, 588 insertions(+), 2 deletions(-)
> > create mode 100644 hw/arm/aspeed_ast27x0.c
> >
> > diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c new
> > file mode 100644 index 00..a3a03fc1ca
> > --- /dev/null
> > +++ b/hw/arm/aspeed_ast27x0.c
> > @@ -0,0 +1,563 @@
> > +/*
> > + * ASPEED SoC 27x0 family
> > + *
> > + * Copyright (C) 2024 ASPEED Technology Inc.
> > + *
> > + * This code is licensed under the GPL version 2 or later. See
> > + * the COPYING file in the top-level directory.
> > + *
> > + * Implementation extracted from the AST2600 and adapted for AST27x0.
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qapi/error.h"
> > +#include "hw/misc/unimp.h"
> > +#include "hw/arm/aspeed_soc.h"
> > +#include "qemu/module.h"
> > +#include "qemu/error-report.h"
> > +#include "hw/i2c/aspeed_i2c.h"
> > +#include "net/net.h"
> > +#include "sysemu/sysemu.h"
> > +#include "hw/intc/arm_gicv3.h"
> > +#include "qapi/qmp/qlist.h"
> > +
> > +static const hwaddr aspeed_soc_ast2700_memmap[] = {
> > +[ASPEED_DEV_SPI_BOOT] = 0x4,
> > +[ASPEED_DEV_SRAM] = 0x1000,
> > +[ASPEED_DEV_SDMC] = 0x12C0,
> > +[ASPEED_DEV_SCU] = 0x12C02000,
> > +[ASPEED_DEV_SCUIO] = 0x14C02000,
> > +[ASPEED_DEV_UART0] = 0X14C33000,
> > +[ASPEED_DEV_UART1] = 0X14C33100,
> > +[ASPEED_DEV_UART2] = 0X14C33200,
> > +[ASPEED_DEV_UART3] = 0X14C33300,
> > +[ASPEED_DEV_UART4] = 0X12C1A000,
> > +[ASPEED_DEV_UART5] = 0X14C33400,
> > +[ASPEED_DEV_UART6] = 0X14C33500,
> > +[ASPEED_DEV_UART7] = 0X14C33600,
> > +[ASPEED_DEV_UART8] = 0X14C33700,
> > +[ASPEED_DEV_UART9] = 0X14C33800,
> > +[ASPEED_DEV_UART10]= 0X14C33900,
> > +[ASPEED_DEV_UART11]= 0X14C33A00,
> > +[ASPEED_DEV_UART12]= 0X14C33B00,
> > +[ASPEED_DEV_WDT] = 0x14C37000,
> > +[ASPEED_DEV_VUART] = 0X14C3,
> > +[ASPEED_DEV_FMC] = 0x1400,
> > +[ASPEED_DEV_SPI0] = 0x1401,
> > +[ASPEED_DEV_SPI1] = 0x1402,
> > +[ASPEED_DEV_SPI2] = 0x1403,
> > +[ASPEED_DEV_SDRAM] = 0x4,
> > +[ASPEED_DEV_MII1] = 0x1404,
> > +[ASPEED_DEV_MII2] = 0x14040008,
> > +[ASPEED_DEV_MII3] = 0x14040010,
> > +[ASPEED_DEV_ETH1] = 0x1405,
> > +[ASPEED_DEV_ETH2] = 0x1406,
> > +[ASPEED_DEV_ETH3] = 0x1407,
> > +[ASPEED_DEV_EMMC] = 0x1209,
> > +[ASPEED_DEV_INTC] = 0x1210,
> > +[ASPEED_DEV_SLI] = 0x12C17000,
> > +[ASPEED_DEV_SLIIO] = 0x14C1E000,
> > +[ASPEED_GIC_DIST] = 0x1220,
> > +[ASPEED_GIC_REDIST]= 0x1228,
> > +};
> > +
> > +#define AST2700_MAX_IRQ 288
> > +
> > +/* Shared Peripheral Interrupt values below are offset by -32 from
> > +datasheet */ static const int aspeed_soc_ast2700_irqmap[] = {
> > +[ASPEED_DEV_UART0] = 132,
> > +[ASPEED_DEV_UART1] = 132,
> > +[ASPEED_DEV_UART2] = 132,
> > +[ASPEED_DEV_UART3] = 132,
> > +[ASPEED_DEV_UART4] = 8,
> > +[ASPEED_DEV_UART5] = 132,
> > +[ASPEED_DEV_UART6] = 132,
> > +[ASPEED_DEV_UART7] = 132,
> > +[ASPEED_DEV_UART8] = 132,
> > +[ASPEED_DEV_UART9] = 132,
> > +[ASPEED_DEV_UART10]= 132,
> > +[ASPEED_DEV_UART11]= 132,
> > +[ASPEED_DEV_UART12]= 132,
> > +[ASPEED_DEV_FMC] = 131,
> > +[ASPEED_DEV_SDMC] = 0,
> > +[ASPEED_DEV_SCU] = 12,
> > +[ASPEED_DEV_ADC] = 130,
> > +[ASPEED_DEV_XDMA] = 5,
> > +
RE: [PATCH v4 12/16] aspeed/soc: Add AST2700 support
Hi Cedric,
> From: Cédric Le Goater
> Subject: Re: [PATCH v4 12/16] aspeed/soc: Add AST2700 support
>
>
> Hello Jamin,
> > I refer to versal_create_apu_gic function,
> https://github.com/qemu/qemu/blob/master/hw/arm/xlnx-versal.c#L67
> > and updated aspeed_soc_ast2700_gic as following.
> > If you have any concerned about the new changes, please let me know.
> > Thanks-Jamin
> >
> > static bool aspeed_soc_ast2700_gic(DeviceState *dev, Error **errp)
>
> Please rename to aspeed_soc_ast2700_gic_realize()
Will fix in v5 patch
>
> > {
> > Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
> > AspeedSoCState *s = ASPEED_SOC(dev);
> > AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> > SysBusDevice *gicbusdev;
> > DeviceState *gicdev;
> > QList *redist_region_count;
> > int i;
> >
> > object_initialize_child(OBJECT(a), "ast2700-gic", >gic,
> > gicv3_class_name());
>
> and object_initialize_child() can be called in aspeed_soc_ast2700_init().
Will fix in v5 patch
My new changes as following,
static void aspeed_soc_ast2700_init(Object *obj) {
--
object_initialize_child(obj, "gic", >gic, gicv3_class_name());
--
}
>
> > gicbusdev = SYS_BUS_DEVICE(>gic);
> > gicdev = DEVICE(>gic);
> > qdev_prop_set_uint32(gicdev, "revision", 3);
> > qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus);
> > qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ);
> >
> > redist_region_count = qlist_new();
> > qlist_append_int(redist_region_count, sc->num_cpus);
> > qdev_prop_set_array(gicdev, "redist-region-count",
> redist_region_count);
> >
> > if (!sysbus_realize(gicbusdev, errp)) {
> > return false;
> > }
> > sysbus_mmio_map(gicbusdev, 0, sc->memmap[ASPEED_GIC_DIST]);
> > sysbus_mmio_map(gicbusdev, 1,
> sc->memmap[ASPEED_GIC_REDIST]);
> >
> > for (i = 0; i < sc->num_cpus; i++) {
> > DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
>
> Could we avoid qemu_get_cpu() and use the cpu array of the SoC instead ?
Yes, I can change it and my new changes as following.
DeviceState *cpudev = DEVICE(>cpu[i]);
Will fix in v5 patch.
Thanks for review.
Jamin
>
> > int NUM_IRQS = 256, ARCH_GIC_MAINT_IRQ = 9,
> VIRTUAL_PMU_IRQ = 7;
> > int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
> >
> > const int timer_irq[] = {
> > [GTIMER_PHYS] = 14,
> > [GTIMER_VIRT] = 11,
> > [GTIMER_HYP] = 10,
> > [GTIMER_SEC] = 13,
> > };
> > int j;
> >
> > for (j = 0; j < ARRAY_SIZE(timer_irq); j++) {
> > qdev_connect_gpio_out(cpudev, j,
> > qdev_get_gpio_in(gicdev, ppibase + timer_irq[j]));
> > }
> >
> > qemu_irq irq = qdev_get_gpio_in(gicdev,
> > ppibase +
> ARCH_GIC_MAINT_IRQ);
> > qdev_connect_gpio_out_named(cpudev,
> "gicv3-maintenance-interrupt",
> > 0, irq);
> > qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
> > qdev_get_gpio_in(gicdev, ppibase +
> VIRTUAL_PMU_IRQ));
> >
> > sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev,
> ARM_CPU_IRQ));
> > sysbus_connect_irq(gicbusdev, i + sc->num_cpus,
> > qdev_get_gpio_in(cpudev,
> ARM_CPU_FIQ));
> > sysbus_connect_irq(gicbusdev, i + 2 * sc->num_cpus,
> > qdev_get_gpio_in(cpudev,
> ARM_CPU_VIRQ));
> > sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus,
> > qdev_get_gpio_in(cpudev,
> ARM_CPU_VFIQ));
> > }
> >
> > return true;
> > }
> >
> > struct Aspeed27x0SoCState {
> > AspeedSoCState parent;
> >
> > ARMCPU cpu[ASPEED_CPUS_NUM];
> > AspeedINTCState intc;
> > GICv3State gic;
> > };
> >
> > #define TYPE_ASPEED27X0_SOC "aspeed27x0-soc"
> > OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SoCState, ASPEED27X0_SOC)
>
> Thanks,
>
> C.
>
>
Re: [PATCH v4 12/16] aspeed/soc: Add AST2700 support
Hello Jamin,
I refer to versal_create_apu_gic function,
https://github.com/qemu/qemu/blob/master/hw/arm/xlnx-versal.c#L67
and updated aspeed_soc_ast2700_gic as following.
If you have any concerned about the new changes, please let me know.
Thanks-Jamin
static bool aspeed_soc_ast2700_gic(DeviceState *dev, Error **errp)
Please rename to aspeed_soc_ast2700_gic_realize()
{
Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
AspeedSoCState *s = ASPEED_SOC(dev);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
SysBusDevice *gicbusdev;
DeviceState *gicdev;
QList *redist_region_count;
int i;
object_initialize_child(OBJECT(a), "ast2700-gic", >gic,
gicv3_class_name());
and object_initialize_child() can be called in aspeed_soc_ast2700_init().
gicbusdev = SYS_BUS_DEVICE(>gic);
gicdev = DEVICE(>gic);
qdev_prop_set_uint32(gicdev, "revision", 3);
qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus);
qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ);
redist_region_count = qlist_new();
qlist_append_int(redist_region_count, sc->num_cpus);
qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count);
if (!sysbus_realize(gicbusdev, errp)) {
return false;
}
sysbus_mmio_map(gicbusdev, 0, sc->memmap[ASPEED_GIC_DIST]);
sysbus_mmio_map(gicbusdev, 1, sc->memmap[ASPEED_GIC_REDIST]);
for (i = 0; i < sc->num_cpus; i++) {
DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
Could we avoid qemu_get_cpu() and use the cpu array of the SoC instead ?
int NUM_IRQS = 256, ARCH_GIC_MAINT_IRQ = 9, VIRTUAL_PMU_IRQ = 7;
int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
const int timer_irq[] = {
[GTIMER_PHYS] = 14,
[GTIMER_VIRT] = 11,
[GTIMER_HYP] = 10,
[GTIMER_SEC] = 13,
};
int j;
for (j = 0; j < ARRAY_SIZE(timer_irq); j++) {
qdev_connect_gpio_out(cpudev, j,
qdev_get_gpio_in(gicdev, ppibase + timer_irq[j]));
}
qemu_irq irq = qdev_get_gpio_in(gicdev,
ppibase + ARCH_GIC_MAINT_IRQ);
qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
0, irq);
qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
qdev_get_gpio_in(gicdev, ppibase + VIRTUAL_PMU_IRQ));
sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev,
ARM_CPU_IRQ));
sysbus_connect_irq(gicbusdev, i + sc->num_cpus,
qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
sysbus_connect_irq(gicbusdev, i + 2 * sc->num_cpus,
qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus,
qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
}
return true;
}
struct Aspeed27x0SoCState {
AspeedSoCState parent;
ARMCPU cpu[ASPEED_CPUS_NUM];
AspeedINTCState intc;
GICv3State gic;
};
#define TYPE_ASPEED27X0_SOC "aspeed27x0-soc"
OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SoCState, ASPEED27X0_SOC)
Thanks,
C.
RE: [PATCH v4 12/16] aspeed/soc: Add AST2700 support
Hi Cedric,
> From: Cédric Le Goater
> Subject: Re: [PATCH v4 12/16] aspeed/soc: Add AST2700 support
>
> On 5/27/24 10:02, Jamin Lin wrote:
> > Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35
> CPU).
> >
> > AST2700 SOC and its interrupt controller are too complex to handle in
> > the common Aspeed SoC framework. We introduce a new ast2700 class with
> > instance_init and realize handlers.
> >
> > AST2700 is a 64 bits quad core cpus and support 8 watchdog.
> > Update maximum ASPEED_CPUS_NUM to 4 and ASPEED_WDTS_NUM to 8.
> > In addition, update AspeedSocState to support scuio, sli, sliio and intc.
> >
> > Add TYPE_ASPEED27X0_SOC machine type.
> >
> > The SDMC controller is unlocked at SPL stage.
> > At present, only supports to emulate booting start from u-boot stage.
> > Set SDMC controller unlocked by default.
> >
> > In INTC, each interrupt of INT 128 to INT 136 combines 32 interrupts.
> > It connect GICINT IRQ GPIO-OUTPUT pins to GIC device with irq 128 to 136.
> > And, if a device irq is 128 to 136, its irq GPIO-OUTPUT pin is
> > connected to GICINT or-gates instead of GIC device.
> >
> > Signed-off-by: Troy Lee
> > Signed-off-by: Jamin Lin
> > ---
> > hw/arm/aspeed_ast27x0.c | 563
>
> > hw/arm/meson.build | 1 +
> > include/hw/arm/aspeed_soc.h | 26 +-
> > 3 files changed, 588 insertions(+), 2 deletions(-)
> > create mode 100644 hw/arm/aspeed_ast27x0.c
> >
> > diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c new
> > file mode 100644 index 00..a3a03fc1ca
> > --- /dev/null
> > +++ b/hw/arm/aspeed_ast27x0.c
> > @@ -0,0 +1,563 @@
> > +/*
> > + * ASPEED SoC 27x0 family
> > + *
> > + * Copyright (C) 2024 ASPEED Technology Inc.
> > + *
> > + * This code is licensed under the GPL version 2 or later. See
> > + * the COPYING file in the top-level directory.
> > + *
> > + * Implementation extracted from the AST2600 and adapted for AST27x0.
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qapi/error.h"
> > +#include "hw/misc/unimp.h"
> > +#include "hw/arm/aspeed_soc.h"
> > +#include "qemu/module.h"
> > +#include "qemu/error-report.h"
> > +#include "hw/i2c/aspeed_i2c.h"
> > +#include "net/net.h"
> > +#include "sysemu/sysemu.h"
> > +#include "hw/intc/arm_gicv3.h"
> > +#include "qapi/qmp/qlist.h"
> > +
> > +static const hwaddr aspeed_soc_ast2700_memmap[] = {
> > +[ASPEED_DEV_SPI_BOOT] = 0x4,
> > +[ASPEED_DEV_SRAM] = 0x1000,
> > +[ASPEED_DEV_SDMC] = 0x12C0,
> > +[ASPEED_DEV_SCU] = 0x12C02000,
> > +[ASPEED_DEV_SCUIO] = 0x14C02000,
> > +[ASPEED_DEV_UART0] = 0X14C33000,
> > +[ASPEED_DEV_UART1] = 0X14C33100,
> > +[ASPEED_DEV_UART2] = 0X14C33200,
> > +[ASPEED_DEV_UART3] = 0X14C33300,
> > +[ASPEED_DEV_UART4] = 0X12C1A000,
> > +[ASPEED_DEV_UART5] = 0X14C33400,
> > +[ASPEED_DEV_UART6] = 0X14C33500,
> > +[ASPEED_DEV_UART7] = 0X14C33600,
> > +[ASPEED_DEV_UART8] = 0X14C33700,
> > +[ASPEED_DEV_UART9] = 0X14C33800,
> > +[ASPEED_DEV_UART10]= 0X14C33900,
> > +[ASPEED_DEV_UART11]= 0X14C33A00,
> > +[ASPEED_DEV_UART12]= 0X14C33B00,
> > +[ASPEED_DEV_WDT] = 0x14C37000,
> > +[ASPEED_DEV_VUART] = 0X14C3,
> > +[ASPEED_DEV_FMC] = 0x1400,
> > +[ASPEED_DEV_SPI0] = 0x1401,
> > +[ASPEED_DEV_SPI1] = 0x1402,
> > +[ASPEED_DEV_SPI2] = 0x1403,
> > +[ASPEED_DEV_SDRAM] = 0x4,
> > +[ASPEED_DEV_MII1] = 0x1404,
> > +[ASPEED_DEV_MII2] = 0x14040008,
> > +[ASPEED_DEV_MII3] = 0x14040010,
> > +[ASPEED_DEV_ETH1] = 0x1405,
> > +[ASPEED_DEV_ETH2] = 0x1406,
> > +[ASPEED_DEV_ETH3] = 0x1407,
> > +[ASPEED_DEV_EMMC] = 0x1209,
> > +[ASPEED_DEV_INTC] = 0x1210,
> > +[ASPEED_DEV_SLI] = 0x12C17000,
> > +[ASPEED_DEV_SLIIO] = 0x14C1E000,
> > +[ASPEED_GIC_DIST] = 0x1220,
> > +[ASPEED_GIC_REDIST]= 0x1228,
> > +};
> > +
> > +#define AST2700_MAX_IRQ 288
> > +
> > +/* Shared Peripheral Interrupt values below
Re: [PATCH v4 12/16] aspeed/soc: Add AST2700 support
On 5/27/24 10:02, Jamin Lin wrote:
Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35 CPU).
AST2700 SOC and its interrupt controller are too complex to handle
in the common Aspeed SoC framework. We introduce a new ast2700
class with instance_init and realize handlers.
AST2700 is a 64 bits quad core cpus and support 8 watchdog.
Update maximum ASPEED_CPUS_NUM to 4 and ASPEED_WDTS_NUM to 8.
In addition, update AspeedSocState to support scuio, sli, sliio and intc.
Add TYPE_ASPEED27X0_SOC machine type.
The SDMC controller is unlocked at SPL stage.
At present, only supports to emulate booting
start from u-boot stage. Set SDMC controller
unlocked by default.
In INTC, each interrupt of INT 128 to INT 136 combines 32 interrupts.
It connect GICINT IRQ GPIO-OUTPUT pins to GIC device with irq 128 to 136.
And, if a device irq is 128 to 136, its irq GPIO-OUTPUT pin is connected to
GICINT or-gates instead of GIC device.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 563
hw/arm/meson.build | 1 +
include/hw/arm/aspeed_soc.h | 26 +-
3 files changed, 588 insertions(+), 2 deletions(-)
create mode 100644 hw/arm/aspeed_ast27x0.c
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
new file mode 100644
index 00..a3a03fc1ca
--- /dev/null
+++ b/hw/arm/aspeed_ast27x0.c
@@ -0,0 +1,563 @@
+/*
+ * ASPEED SoC 27x0 family
+ *
+ * Copyright (C) 2024 ASPEED Technology Inc.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ *
+ * Implementation extracted from the AST2600 and adapted for AST27x0.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/misc/unimp.h"
+#include "hw/arm/aspeed_soc.h"
+#include "qemu/module.h"
+#include "qemu/error-report.h"
+#include "hw/i2c/aspeed_i2c.h"
+#include "net/net.h"
+#include "sysemu/sysemu.h"
+#include "hw/intc/arm_gicv3.h"
+#include "qapi/qmp/qlist.h"
+
+static const hwaddr aspeed_soc_ast2700_memmap[] = {
+[ASPEED_DEV_SPI_BOOT] = 0x4,
+[ASPEED_DEV_SRAM] = 0x1000,
+[ASPEED_DEV_SDMC] = 0x12C0,
+[ASPEED_DEV_SCU] = 0x12C02000,
+[ASPEED_DEV_SCUIO] = 0x14C02000,
+[ASPEED_DEV_UART0] = 0X14C33000,
+[ASPEED_DEV_UART1] = 0X14C33100,
+[ASPEED_DEV_UART2] = 0X14C33200,
+[ASPEED_DEV_UART3] = 0X14C33300,
+[ASPEED_DEV_UART4] = 0X12C1A000,
+[ASPEED_DEV_UART5] = 0X14C33400,
+[ASPEED_DEV_UART6] = 0X14C33500,
+[ASPEED_DEV_UART7] = 0X14C33600,
+[ASPEED_DEV_UART8] = 0X14C33700,
+[ASPEED_DEV_UART9] = 0X14C33800,
+[ASPEED_DEV_UART10]= 0X14C33900,
+[ASPEED_DEV_UART11]= 0X14C33A00,
+[ASPEED_DEV_UART12]= 0X14C33B00,
+[ASPEED_DEV_WDT] = 0x14C37000,
+[ASPEED_DEV_VUART] = 0X14C3,
+[ASPEED_DEV_FMC] = 0x1400,
+[ASPEED_DEV_SPI0] = 0x1401,
+[ASPEED_DEV_SPI1] = 0x1402,
+[ASPEED_DEV_SPI2] = 0x1403,
+[ASPEED_DEV_SDRAM] = 0x4,
+[ASPEED_DEV_MII1] = 0x1404,
+[ASPEED_DEV_MII2] = 0x14040008,
+[ASPEED_DEV_MII3] = 0x14040010,
+[ASPEED_DEV_ETH1] = 0x1405,
+[ASPEED_DEV_ETH2] = 0x1406,
+[ASPEED_DEV_ETH3] = 0x1407,
+[ASPEED_DEV_EMMC] = 0x1209,
+[ASPEED_DEV_INTC] = 0x1210,
+[ASPEED_DEV_SLI] = 0x12C17000,
+[ASPEED_DEV_SLIIO] = 0x14C1E000,
+[ASPEED_GIC_DIST] = 0x1220,
+[ASPEED_GIC_REDIST]= 0x1228,
+};
+
+#define AST2700_MAX_IRQ 288
+
+/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
+static const int aspeed_soc_ast2700_irqmap[] = {
+[ASPEED_DEV_UART0] = 132,
+[ASPEED_DEV_UART1] = 132,
+[ASPEED_DEV_UART2] = 132,
+[ASPEED_DEV_UART3] = 132,
+[ASPEED_DEV_UART4] = 8,
+[ASPEED_DEV_UART5] = 132,
+[ASPEED_DEV_UART6] = 132,
+[ASPEED_DEV_UART7] = 132,
+[ASPEED_DEV_UART8] = 132,
+[ASPEED_DEV_UART9] = 132,
+[ASPEED_DEV_UART10]= 132,
+[ASPEED_DEV_UART11]= 132,
+[ASPEED_DEV_UART12]= 132,
+[ASPEED_DEV_FMC] = 131,
+[ASPEED_DEV_SDMC] = 0,
+[ASPEED_DEV_SCU] = 12,
+[ASPEED_DEV_ADC] = 130,
+[ASPEED_DEV_XDMA] = 5,
+[ASPEED_DEV_EMMC] = 15,
+[ASPEED_DEV_GPIO] = 11,
+[ASPEED_DEV_GPIO_1_8V] = 130,
+[ASPEED_DEV_RTC] = 13,
+[ASPEED_DEV_TIMER1]= 16,
+[ASPEED_DEV_TIMER2]= 17,
+[ASPEED_DEV_TIMER3]= 18,
+[ASPEED_DEV_TIMER4]= 19,
+[ASPEED_DEV_TIMER5]= 20,
+[ASPEED_DEV_TIMER6]= 21,
+[ASPEED_DEV_TIMER7]= 22,
+[ASPEED_DEV_TIMER8]= 23,
+[ASPEED_DEV_WDT] = 131,
+[ASPEED_DEV_PWM] = 131,
+[ASPEED_DEV_LPC] = 128,
+[ASPEED_DEV_IBT]
Re: [PATCH v4 12/16] aspeed/soc: Add AST2700 support
On 5/27/24 10:02, Jamin Lin wrote:
Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35 CPU).
AST2700 SOC and its interrupt controller are too complex to handle
in the common Aspeed SoC framework. We introduce a new ast2700
class with instance_init and realize handlers.
AST2700 is a 64 bits quad core cpus and support 8 watchdog.
Update maximum ASPEED_CPUS_NUM to 4 and ASPEED_WDTS_NUM to 8.
In addition, update AspeedSocState to support scuio, sli, sliio and intc.
Add TYPE_ASPEED27X0_SOC machine type.
The SDMC controller is unlocked at SPL stage.
At present, only supports to emulate booting
start from u-boot stage. Set SDMC controller
unlocked by default.
In INTC, each interrupt of INT 128 to INT 136 combines 32 interrupts.
It connect GICINT IRQ GPIO-OUTPUT pins to GIC device with irq 128 to 136.
And, if a device irq is 128 to 136, its irq GPIO-OUTPUT pin is connected to
GICINT or-gates instead of GIC device.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 563
hw/arm/meson.build | 1 +
include/hw/arm/aspeed_soc.h | 26 +-
3 files changed, 588 insertions(+), 2 deletions(-)
create mode 100644 hw/arm/aspeed_ast27x0.c
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
new file mode 100644
index 00..a3a03fc1ca
--- /dev/null
+++ b/hw/arm/aspeed_ast27x0.c
@@ -0,0 +1,563 @@
+/*
+ * ASPEED SoC 27x0 family
+ *
+ * Copyright (C) 2024 ASPEED Technology Inc.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ *
+ * Implementation extracted from the AST2600 and adapted for AST27x0.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/misc/unimp.h"
+#include "hw/arm/aspeed_soc.h"
+#include "qemu/module.h"
+#include "qemu/error-report.h"
+#include "hw/i2c/aspeed_i2c.h"
+#include "net/net.h"
+#include "sysemu/sysemu.h"
+#include "hw/intc/arm_gicv3.h"
+#include "qapi/qmp/qlist.h"
+
+static const hwaddr aspeed_soc_ast2700_memmap[] = {
+[ASPEED_DEV_SPI_BOOT] = 0x4,
+[ASPEED_DEV_SRAM] = 0x1000,
+[ASPEED_DEV_SDMC] = 0x12C0,
+[ASPEED_DEV_SCU] = 0x12C02000,
+[ASPEED_DEV_SCUIO] = 0x14C02000,
+[ASPEED_DEV_UART0] = 0X14C33000,
+[ASPEED_DEV_UART1] = 0X14C33100,
+[ASPEED_DEV_UART2] = 0X14C33200,
+[ASPEED_DEV_UART3] = 0X14C33300,
+[ASPEED_DEV_UART4] = 0X12C1A000,
+[ASPEED_DEV_UART5] = 0X14C33400,
+[ASPEED_DEV_UART6] = 0X14C33500,
+[ASPEED_DEV_UART7] = 0X14C33600,
+[ASPEED_DEV_UART8] = 0X14C33700,
+[ASPEED_DEV_UART9] = 0X14C33800,
+[ASPEED_DEV_UART10]= 0X14C33900,
+[ASPEED_DEV_UART11]= 0X14C33A00,
+[ASPEED_DEV_UART12]= 0X14C33B00,
+[ASPEED_DEV_WDT] = 0x14C37000,
+[ASPEED_DEV_VUART] = 0X14C3,
+[ASPEED_DEV_FMC] = 0x1400,
+[ASPEED_DEV_SPI0] = 0x1401,
+[ASPEED_DEV_SPI1] = 0x1402,
+[ASPEED_DEV_SPI2] = 0x1403,
+[ASPEED_DEV_SDRAM] = 0x4,
+[ASPEED_DEV_MII1] = 0x1404,
+[ASPEED_DEV_MII2] = 0x14040008,
+[ASPEED_DEV_MII3] = 0x14040010,
+[ASPEED_DEV_ETH1] = 0x1405,
+[ASPEED_DEV_ETH2] = 0x1406,
+[ASPEED_DEV_ETH3] = 0x1407,
+[ASPEED_DEV_EMMC] = 0x1209,
+[ASPEED_DEV_INTC] = 0x1210,
+[ASPEED_DEV_SLI] = 0x12C17000,
+[ASPEED_DEV_SLIIO] = 0x14C1E000,
+[ASPEED_GIC_DIST] = 0x1220,
+[ASPEED_GIC_REDIST]= 0x1228,
+};
+
+#define AST2700_MAX_IRQ 288
+
+/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
+static const int aspeed_soc_ast2700_irqmap[] = {
+[ASPEED_DEV_UART0] = 132,
+[ASPEED_DEV_UART1] = 132,
+[ASPEED_DEV_UART2] = 132,
+[ASPEED_DEV_UART3] = 132,
+[ASPEED_DEV_UART4] = 8,
+[ASPEED_DEV_UART5] = 132,
+[ASPEED_DEV_UART6] = 132,
+[ASPEED_DEV_UART7] = 132,
+[ASPEED_DEV_UART8] = 132,
+[ASPEED_DEV_UART9] = 132,
+[ASPEED_DEV_UART10]= 132,
+[ASPEED_DEV_UART11]= 132,
+[ASPEED_DEV_UART12]= 132,
+[ASPEED_DEV_FMC] = 131,
+[ASPEED_DEV_SDMC] = 0,
+[ASPEED_DEV_SCU] = 12,
+[ASPEED_DEV_ADC] = 130,
+[ASPEED_DEV_XDMA] = 5,
+[ASPEED_DEV_EMMC] = 15,
+[ASPEED_DEV_GPIO] = 11,
+[ASPEED_DEV_GPIO_1_8V] = 130,
+[ASPEED_DEV_RTC] = 13,
+[ASPEED_DEV_TIMER1]= 16,
+[ASPEED_DEV_TIMER2]= 17,
+[ASPEED_DEV_TIMER3]= 18,
+[ASPEED_DEV_TIMER4]= 19,
+[ASPEED_DEV_TIMER5]= 20,
+[ASPEED_DEV_TIMER6]= 21,
+[ASPEED_DEV_TIMER7]= 22,
+[ASPEED_DEV_TIMER8]= 23,
+[ASPEED_DEV_WDT] = 131,
+[ASPEED_DEV_PWM] = 131,
+[ASPEED_DEV_LPC] = 128,
+[ASPEED_DEV_IBT]
