Re: [RFC v3 2/3] acpi:pci-expender-bus: Add pxb support for arm

2020-02-21 Thread Michael S. Tsirkin
On Fri, Feb 21, 2020 at 02:35:11PM +0800, Yubo Miao wrote:
> From: miaoyubo 
> 
> Currently virt machine is not supported by pxb-pcie,
> and only one main host bridge described in ACPI tables.
> In this patch,PXB-PCIE is supproted by arm and certain
> resource is allocated for each pxb-pcie in acpi table.
> The resource for the main host bridge is also reallocated.
> 
> Signed-off-by: miaoyubo 
> ---
>  hw/arm/virt-acpi-build.c | 125 +++
>  hw/pci-host/gpex.c   |   4 ++
>  include/hw/arm/virt.h|   7 +++
>  3 files changed, 125 insertions(+), 11 deletions(-)
> 
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index 0540234b8a..2c1e0d2aaa 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -49,6 +49,8 @@
>  #include "kvm_arm.h"
>  #include "migration/vmstate.h"
>  
> +#include "hw/arm/virt.h"
> +#include "hw/pci/pci_bus.h"
>  #define ARM_SPI_BASE 32
>  
>  static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
> @@ -271,19 +273,117 @@ static void acpi_dsdt_add_pci_osc(Aml *dev, Aml *scope)
>  }
>  
>  static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
> -  uint32_t irq, bool use_highmem, bool 
> highmem_ecam)
> +  uint32_t irq, bool use_highmem, bool 
> highmem_ecam,
> +  VirtMachineState *vms)
>  {
>  int ecam_id = VIRT_ECAM_ID(highmem_ecam);
> -Aml *method, *crs;
> +Aml *method, *dev, *crs;
> +int count = 0;
>  hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base;
>  hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size;
>  hwaddr base_pio = memmap[VIRT_PCIE_PIO].base;
>  hwaddr size_pio = memmap[VIRT_PCIE_PIO].size;
>  hwaddr base_ecam = memmap[ecam_id].base;
>  hwaddr size_ecam = memmap[ecam_id].size;
> +/*
> + * 0x60 would be enough for pxb device
> + * if it is too small, there is no enough space
> + * for a pcie device plugged in a pcie-root port
> + */
> +hwaddr size_addr = 0x60;
> +hwaddr size_io = 0x4000;
>  int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
> +int root_bus_limit = 0xFF;

what's this?

> +PCIBus *bus = NULL;
> +bus = VIRT_MACHINE(vms)->bus;

So just move assignment as part of declaration.

> +
> +if (bus) {
> +QLIST_FOREACH(bus, &bus->child, sibling) {
> +uint8_t bus_num = pci_bus_num(bus);
> +uint8_t numa_node = pci_bus_numa_node(bus);
> +
> +if (!pci_bus_is_root(bus)) {
> +continue;
> +}
> +if (bus_num < root_bus_limit) {
> +root_bus_limit = bus_num - 1;

what is this doing? manually coded up MIN?

> +}
> +count++;
> +dev = aml_device("PC%.02X", bus_num);
> +aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
> +aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
> +aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
> +aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
> +aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
> +aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
> +aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
> +aml_append(dev, aml_name_decl("_STR", aml_unicode("pxb 
> Device")));
> +if (numa_node != NUMA_NODE_UNASSIGNED) {
> +method = aml_method("_PXM", 0, AML_NOTSERIALIZED);
> +aml_append(method, aml_return(aml_int(numa_node)));
> +aml_append(dev, method);
> +}
> +
> +acpi_dsdt_add_pci_route_table(dev, scope, nr_pcie_buses, irq);
> +
> +method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
> +aml_append(method, aml_return(aml_int(base_ecam)));
> +aml_append(dev, method);
> +
> +method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
> +Aml *rbuf = aml_resource_template();
> +aml_append(rbuf,
> +   aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED,
> +   AML_POS_DECODE, 0x,
> +   bus_num, bus_num + 1, 0x,
> +   2));
> +aml_append(rbuf,
> +   aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
> +AML_MAX_FIXED, AML_NON_CACHEABLE,
> +AML_READ_WRITE, 0x,
> +base_mmio + size_mmio -
> +size_addr * count,
> +base_mmio + size_mmio - 1 -
> +size_addr * (count - 1),
> +0x, size_addr));
> +aml_append(rbuf,
> +  

RE: [RFC v3 2/3] acpi:pci-expender-bus: Add pxb support for arm

2020-02-22 Thread miaoyubo


> -Original Message-
> From: Michael S. Tsirkin [mailto:m...@redhat.com]
> Sent: Friday, February 21, 2020 7:18 PM
> To: miaoyubo 
> Cc: peter.mayd...@linaro.org; shannon.zha...@gmail.com; Xiexiangyou
> ; imamm...@redhat.com;
> qemu-devel@nongnu.org
> Subject: Re: [RFC v3 2/3] acpi:pci-expender-bus: Add pxb support for arm
> 
> On Fri, Feb 21, 2020 at 02:35:11PM +0800, Yubo Miao wrote:
> > From: miaoyubo 
> >
> > Currently virt machine is not supported by pxb-pcie, and only one main
> > host bridge described in ACPI tables.
> > In this patch,PXB-PCIE is supproted by arm and certain resource is
> > allocated for each pxb-pcie in acpi table.
> > The resource for the main host bridge is also reallocated.
> >
> > Signed-off-by: miaoyubo 
> > ---
> >  hw/arm/virt-acpi-build.c | 125
> +++
> >  hw/pci-host/gpex.c   |   4 ++
> >  include/hw/arm/virt.h|   7 +++
> >  3 files changed, 125 insertions(+), 11 deletions(-)
> >
> > diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index
> > 0540234b8a..2c1e0d2aaa 100644
> > --- a/hw/arm/virt-acpi-build.c
> > +++ b/hw/arm/virt-acpi-build.c
> > @@ -49,6 +49,8 @@
> >  #include "kvm_arm.h"
> >  #include "migration/vmstate.h"
> >
> > +#include "hw/arm/virt.h"
> > +#include "hw/pci/pci_bus.h"
> >  #define ARM_SPI_BASE 32
> >
> >  static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) @@ -271,19
> > +273,117 @@ static void acpi_dsdt_add_pci_osc(Aml *dev, Aml *scope)  }
> >
> >  static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry
> *memmap,
> > -  uint32_t irq, bool use_highmem, bool
> highmem_ecam)
> > +  uint32_t irq, bool use_highmem, bool
> highmem_ecam,
> > +  VirtMachineState *vms)
> >  {
> >  int ecam_id = VIRT_ECAM_ID(highmem_ecam);
> > -Aml *method, *crs;
> > +Aml *method, *dev, *crs;
> > +int count = 0;
> >  hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base;
> >  hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size;
> >  hwaddr base_pio = memmap[VIRT_PCIE_PIO].base;
> >  hwaddr size_pio = memmap[VIRT_PCIE_PIO].size;
> >  hwaddr base_ecam = memmap[ecam_id].base;
> >  hwaddr size_ecam = memmap[ecam_id].size;
> > +/*
> > + * 0x60 would be enough for pxb device
> > + * if it is too small, there is no enough space
> > + * for a pcie device plugged in a pcie-root port
> > + */
> > +hwaddr size_addr = 0x60;
> > +hwaddr size_io = 0x4000;
> >  int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
> > +int root_bus_limit = 0xFF;
> 
> what's this?
> 

Thanks for replying.
This is used to define the bus numbers for the main host bridge, 
If no pxb-pcie is defined, the bus number for the main host bridge
would range form 0 to 255.

> > +PCIBus *bus = NULL;
> > +bus = VIRT_MACHINE(vms)->bus;
> 
> So just move assignment as part of declaration.
> 

Thanks for the suggestion!

> > +
> > +if (bus) {
> > +QLIST_FOREACH(bus, &bus->child, sibling) {
> > +uint8_t bus_num = pci_bus_num(bus);
> > +uint8_t numa_node = pci_bus_numa_node(bus);
> > +
> > +if (!pci_bus_is_root(bus)) {
> > +continue;
> > +}
> > +if (bus_num < root_bus_limit) {
> > +root_bus_limit = bus_num - 1;
> 
> what is this doing? manually coded up MIN?
> 

This coded up the MIN of busNr defined in pxb-pcie devices, 
and the Min busNr-1 would be the MAX bus Number for the main host bridge.
For example, if one pxb-pcie with busNr 128(which is 80) defined, 
The bus for the main host bridge would be 0-7F, and the bus for pxb-pcie
would be 80-81(just allocate two buses,keep the same with X86).
If pxb-pcie is not defined, the bus for main host bridge would be 0-FF.

> > +}
> > +count++;
> > +dev = aml_device("PC%.02X", bus_num);
> > +aml_append(dev, aml_name_decl("_HID",
> aml_string("PNP0A08")));
> > +aml_append(dev, aml_name_decl("_CID",
> aml_string("PNP0A03")));
> > +aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
> > +aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
> > +aml_append(dev, aml