Re: [PULL 00/31] target-arm queue

2022-04-21 Thread Richard Henderson

On 4/21/22 04:18, Peter Maydell wrote:

First arm pullreq for 7.1. The bulk of this is the qemu_split_irq
removal.

I have enough stuff in my to-review queue that I expect to do another
pullreq early next week, but 31 patches is enough to not hang on to.

thanks
-- PMM

The following changes since commit 9c125d17e9402c232c46610802e5931b3639d77b:

   Merge tag 'pull-tcg-20220420' of https://gitlab.com/rth7680/qemu into 
staging (2022-04-20 16:43:11 -0700)

are available in the Git repository at:

   https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20220421

for you to fetch changes up to 5b415dd61bdbf61fb4be0e9f1a7172b8bce682c6:

   hw/arm: Use bit fields for NPCM7XX PWRON STRAPs (2022-04-21 11:37:05 +0100)


target-arm queue:
  * hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF
  * versal: Add the Cortex-R5s in the Real-Time Processing Unit (RPU) subsystem
  * versal: model enough of the Clock/Reset Low-power domain (CRL) to allow 
control of the Cortex-R5s
  * xlnx-zynqmp: Connect 4 TTC timers
  * exynos4210: Refactor GIC/combiner code to stop using qemu_split_irq
  * realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
  * stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
  * hw/core/irq: remove unused 'qemu_irq_split' function
  * npcm7xx: use symbolic constants for PWRON STRAP bit fields
  * virt: document impact of gic-version on max CPUs


Applied, thanks.  Please update https://wiki.qemu.org/ChangeLog/7.1 as 
appropriate.


r~





Edgar E. Iglesias (6):
   timer: cadence_ttc: Break out header file to allow embedding
   hw/arm/xlnx-zynqmp: Connect 4 TTC timers
   hw/arm: versal: Create an APU CPU Cluster
   hw/arm: versal: Add the Cortex-R5Fs
   hw/misc: Add a model of the Xilinx Versal CRL
   hw/arm: versal: Connect the CRL

Hao Wu (2):
   hw/misc: Add PWRON STRAP bit fields in GCR module
   hw/arm: Use bit fields for NPCM7XX PWRON STRAPs

Heinrich Schuchardt (1):
   hw/arm/virt: impact of gic-version on max CPUs

Peter Maydell (19):
   hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF
   hw/arm/exynos4210: Use TYPE_OR_IRQ instead of custom OR-gate device
   hw/intc/exynos4210_gic: Remove unused TYPE_EXYNOS4210_IRQ_GATE
   hw/arm/exynos4210: Put a9mpcore device into state struct
   hw/arm/exynos4210: Drop int_gic_irq[] from Exynos4210Irq struct
   hw/arm/exynos4210: Coalesce board_irqs and irq_table
   hw/arm/exynos4210: Fix code style nit in combiner_grp_to_gic_id[]
   hw/arm/exynos4210: Move exynos4210_init_board_irqs() into exynos4210.c
   hw/arm/exynos4210: Put external GIC into state struct
   hw/arm/exynos4210: Drop ext_gic_irq[] from Exynos4210Irq struct
   hw/arm/exynos4210: Move exynos4210_combiner_get_gpioin() into 
exynos4210.c
   hw/arm/exynos4210: Delete unused macro definitions
   hw/arm/exynos4210: Use TYPE_SPLIT_IRQ in exynos4210_init_board_irqs()
   hw/arm/exynos4210: Fill in irq_table[] for internal-combiner-only IRQ 
lines
   hw/arm/exynos4210: Connect MCT_G0 and MCT_G1 to both combiners
   hw/arm/exynos4210: Don't connect multiple lines to external GIC inputs
   hw/arm/exynos4210: Fold combiner splits into exynos4210_init_board_irqs()
   hw/arm/exynos4210: Put combiners into state struct
   hw/arm/exynos4210: Drop Exynos4210Irq struct

Zongyuan Li (3):
   hw/arm/realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
   hw/arm/stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
   hw/core/irq: remove unused 'qemu_irq_split' function

  docs/system/arm/virt.rst  |   4 +-
  include/hw/arm/exynos4210.h   |  50 ++--
  include/hw/arm/xlnx-versal.h  |  16 ++
  include/hw/arm/xlnx-zynqmp.h  |   4 +
  include/hw/intc/exynos4210_combiner.h |  57 +
  include/hw/intc/exynos4210_gic.h  |  43 
  include/hw/irq.h  |   5 -
  include/hw/misc/npcm7xx_gcr.h |  30 +++
  include/hw/misc/xlnx-versal-crl.h | 235 +++
  include/hw/timer/cadence_ttc.h|  54 +
  hw/arm/exynos4210.c   | 430 ++
  hw/arm/npcm7xx_boards.c   |  24 +-
  hw/arm/realview.c |  33 ++-
  hw/arm/stellaris.c|  15 +-
  hw/arm/virt.c |   7 +
  hw/arm/xlnx-versal-virt.c |   6 +-
  hw/arm/xlnx-versal.c  |  99 +++-
  hw/arm/xlnx-zynqmp.c  |  22 ++
  hw/core/irq.c |  15 --
  hw/intc/exynos4210_combiner.c | 108 +
  hw/intc/exynos4210_gic.c  | 344 +--
  hw/misc/xlnx-versal-crl.c | 421 +
  hw/timer/cadence_ttc.c|  

Re: [PULL 00/31] target-arm queue

2020-04-30 Thread no-reply
Patchew URL: 
https://patchew.org/QEMU/20200430115142.13430-1-peter.mayd...@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Message-id: 20200430115142.13430-1-peter.mayd...@linaro.org
Subject: [PULL 00/31] target-arm queue
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
cc6c93a hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes
851a774 hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102
cb4770a device_tree: Constify compat in qemu_fdt_node_path()
a26ed36 device_tree: Allow name wildcards in qemu_fdt_node_path()
0c7b245 target/arm/cpu: Update coding style to make checkpatch.pl happy
6e87116 target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[]
ac5d9f2 target/arm: Make cpu_register() available for other files
1f8dbd1 target/arm: Restrict the Address Translate write operation to TCG accel
26c5aa2 hw/arm/virt: dt: add kaslr-seed property
256d88c hw/arm/virt: dt: move creation of /secure-chosen to create_fdt()
281ba0a target/arm: Vectorize integer comparison vs zero
d335551 net: cadence_gem: clear RX control descriptor
886d104 Cadence: gem: fix wraparound in 64bit descriptors
adab3ff hw/arm: versal: Setup the ADMA with 128bit bus-width
9ff65f3 qdev-monitor: print the device's clock with info qtree
ea507fb hw/arm/xilinx_zynq: connect uart clocks to slcr
abd4b39 hw/char/cadence_uart: add clock support
02a7d87 hw/misc/zynq_slcr: add clock generation for uarts
947bc22 docs/clocks: add device's clock documentation
49f9409 qdev-clock: introduce an init array to ease the device construction
6b7b97c qdev: add clock input support to devices.
62643a6 hw/core/clock-vmstate: define a vmstate entry for clock state
d7158be hw/core/clock: introduce clock object
de7c1af tests/boot_linux_console: Add ethernet test to SmartFusion2
2dd76b4 msf2: Add EMAC block to SmartFusion2 SoC
bf46971 hw/net: Add Smartfusion2 emac block
0af4051 Typo: Correct the name of CPU hotplug memory region
fb7f6b0 bugfix: Use gicr_typer in arm_gicv3_icc_reset
95a592a nrf51: Fix last GPIO CNF address
00478e2 dma/xlnx-zdma: Fix descriptor loading (REG) wrt endianness
7fec387 dma/xlnx-zdma: Fix descriptor loading (MEM) wrt endianness

=== OUTPUT BEGIN ===
1/31 Checking commit 7fec38768f4a (dma/xlnx-zdma: Fix descriptor loading (MEM) 
wrt endianness)
2/31 Checking commit 00478e21e556 (dma/xlnx-zdma: Fix descriptor loading (REG) 
wrt endianness)
3/31 Checking commit 95a592a9ca01 (nrf51: Fix last GPIO CNF address)
4/31 Checking commit fb7f6b03b3bd (bugfix: Use gicr_typer in 
arm_gicv3_icc_reset)
5/31 Checking commit 0af4051edd5b (Typo: Correct the name of CPU hotplug memory 
region)
6/31 Checking commit bf46971ba6f8 (hw/net: Add Smartfusion2 emac block)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41: 
new file mode 100644

total: 0 errors, 1 warnings, 654 lines checked

Patch 6/31 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
7/31 Checking commit 2dd76b4a530d (msf2: Add EMAC block to SmartFusion2 SoC)
8/31 Checking commit de7c1af6c5fa (tests/boot_linux_console: Add ethernet test 
to SmartFusion2)
9/31 Checking commit d7158be1a4b6 (hw/core/clock: introduce clock object)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42: 
new file mode 100644

total: 0 errors, 1 warnings, 363 lines checked

Patch 9/31 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/31 Checking commit 62643a6e45ee (hw/core/clock-vmstate: define a vmstate 
entry for clock state)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#29: 
new file mode 100644

total: 0 errors, 1 warnings, 47 lines checked

Patch 10/31 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/31 Checking commit 6b7b97c06fc4 (qdev: add clock input support to 
devices.)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#35: 
new file mode 100644

total: 0 errors, 1 warnings, 353 lines checked

Patch 11/31 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
12/31 Checking commit 49f9409e6aba (qdev-clock: introduce an init array to ease 
the device construction)
13/31 Checking commit 947bc2295320 (docs/clocks: add device's clock 
documentation)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#22: 
new file mode 100644

total: 0 errors, 1