Re: [Qemu-devel] [PATCH v3 6/6] tcg/mips: Support r6 SEL{NE, EQ}Z instead of MOVN/MOVZ
On Thu, Oct 08, 2015 at 06:31:32PM +0200, Aurelien Jarno wrote: > On 2015-10-02 13:24, James Hogan wrote: > > Extend MIPS movcond implementation to support the SELNEZ/SELEQZ > > instructions introduced in MIPS r6 (where MOVN/MOVZ have been removed). > > > > Whereas the "MOVN/MOVZ rd, rs, rt" instructions have the following > > semantics: > > rd = [!]rt ? rs : rd > > > > The "SELNEZ/SELEQZ rd, rs, rt" instructions are slightly different: > > rd = [!]rt ? rs : 0 > > > > First we ensure that if one of the movcond input values is zero that it > > comes last (we can swap the input arguments if we invert the condition). > > This is so that it can exactly match one of the SELNEZ/SELEQZ > > instructions and avoid the need to emit the other one. > > > > Otherwise we emit the opposite instruction first into a temporary > > register, and OR that into the result: > > SELNEZ/SELEQZ TMP1, v2, c1 > > SELEQZ/SELNEZ ret, v1, c1 > > OR ret, ret, TMP1 > > > > Which does the following: > > ret = cond ? v1 : v2 > > > > Signed-off-by: James Hogan > > Cc: Richard Henderson > > Cc: Aurelien Jarno > > --- > > Changes in v3: > > - Switch to using bool eqz to indicate whether to use SELEQZ / MOVZ > > instead of SELNEZ / MOVN (Richard). > > - Add tcg_debug_assert(v2 == ret) for pre-r6 case with comment to remind > > reader that it should be guaranteed via constraints (Richard). > > > > Changes in v2: > > - Combine with patch 6 from v1, and drop functional changes to movcond > > implementation pre-r6. We now provide different constraints for > > movcond depending on presence of r6. (thanks Richard for feedback). > > --- > > tcg/mips/tcg-target.c | 43 +-- > > 1 file changed, 37 insertions(+), 6 deletions(-) > > Reviewed-by: Aurelien Jarno Thanks for the reviews Aurelien! Cheers James signature.asc Description: Digital signature
Re: [Qemu-devel] [PATCH v3 6/6] tcg/mips: Support r6 SEL{NE, EQ}Z instead of MOVN/MOVZ
On 2015-10-02 13:24, James Hogan wrote: > Extend MIPS movcond implementation to support the SELNEZ/SELEQZ > instructions introduced in MIPS r6 (where MOVN/MOVZ have been removed). > > Whereas the "MOVN/MOVZ rd, rs, rt" instructions have the following > semantics: > rd = [!]rt ? rs : rd > > The "SELNEZ/SELEQZ rd, rs, rt" instructions are slightly different: > rd = [!]rt ? rs : 0 > > First we ensure that if one of the movcond input values is zero that it > comes last (we can swap the input arguments if we invert the condition). > This is so that it can exactly match one of the SELNEZ/SELEQZ > instructions and avoid the need to emit the other one. > > Otherwise we emit the opposite instruction first into a temporary > register, and OR that into the result: > SELNEZ/SELEQZ TMP1, v2, c1 > SELEQZ/SELNEZ ret, v1, c1 > OR ret, ret, TMP1 > > Which does the following: > ret = cond ? v1 : v2 > > Signed-off-by: James Hogan > Cc: Richard Henderson > Cc: Aurelien Jarno > --- > Changes in v3: > - Switch to using bool eqz to indicate whether to use SELEQZ / MOVZ > instead of SELNEZ / MOVN (Richard). > - Add tcg_debug_assert(v2 == ret) for pre-r6 case with comment to remind > reader that it should be guaranteed via constraints (Richard). > > Changes in v2: > - Combine with patch 6 from v1, and drop functional changes to movcond > implementation pre-r6. We now provide different constraints for > movcond depending on presence of r6. (thanks Richard for feedback). > --- > tcg/mips/tcg-target.c | 43 +-- > 1 file changed, 37 insertions(+), 6 deletions(-) Reviewed-by: Aurelien Jarno -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurel...@aurel32.net http://www.aurel32.net
Re: [Qemu-devel] [PATCH v3 6/6] tcg/mips: Support r6 SEL{NE, EQ}Z instead of MOVN/MOVZ
On 2015-10-07 12:47, Leon Alrae wrote: > On 07/10/15 10:46, Richard Henderson wrote: > > Leon, do you want to take this as a mips maintainer, or shall I as tcg > > maintainer? > > I thought this would go via Aurelien's mips tcg-backend queue. But if > Aurelien is busy, could you take them? (at the moment I don't have > anything handy to test the mips backend). Sorry I have been indeed a bit busy. I can send a pull request in the next days. As you prefer. -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurel...@aurel32.net http://www.aurel32.net
Re: [Qemu-devel] [PATCH v3 6/6] tcg/mips: Support r6 SEL{NE, EQ}Z instead of MOVN/MOVZ
On 10/07/2015 09:34 PM, James Hogan wrote:
{ INDEX_op_brcond_i32, { "rZ", "rZ" } },
+#if !use_mips32r6_instructions
{ INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rZ", "0" } },
+#else
+{ INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rZ", "rZ" } },
+#endif
The only thing I'd change is preferring positive tests to negative ones. So
swap the order of these lines, and the sense of the #if.
No problem. Shall I do a full resend for that, or can it be fixed up by
whoever applies?
No resend needed. I'll fix it when applying to my tcg queue.
r~
Re: [Qemu-devel] [PATCH v3 6/6] tcg/mips: Support r6 SEL{NE, EQ}Z instead of MOVN/MOVZ
On 07/10/15 10:46, Richard Henderson wrote: > Leon, do you want to take this as a mips maintainer, or shall I as tcg > maintainer? I thought this would go via Aurelien's mips tcg-backend queue. But if Aurelien is busy, could you take them? (at the moment I don't have anything handy to test the mips backend). Thanks, Leon
Re: [Qemu-devel] [PATCH v3 6/6] tcg/mips: Support r6 SEL{NE, EQ}Z instead of MOVN/MOVZ
On Wed, Oct 07, 2015 at 08:46:30PM +1100, Richard Henderson wrote:
> On 10/02/2015 10:24 PM, James Hogan wrote:
> > Extend MIPS movcond implementation to support the SELNEZ/SELEQZ
> > instructions introduced in MIPS r6 (where MOVN/MOVZ have been removed).
> >
> > Whereas the "MOVN/MOVZ rd, rs, rt" instructions have the following
> > semantics:
> > rd = [!]rt ? rs : rd
> >
> > The "SELNEZ/SELEQZ rd, rs, rt" instructions are slightly different:
> > rd = [!]rt ? rs : 0
> >
> > First we ensure that if one of the movcond input values is zero that it
> > comes last (we can swap the input arguments if we invert the condition).
> > This is so that it can exactly match one of the SELNEZ/SELEQZ
> > instructions and avoid the need to emit the other one.
> >
> > Otherwise we emit the opposite instruction first into a temporary
> > register, and OR that into the result:
> > SELNEZ/SELEQZ TMP1, v2, c1
> > SELEQZ/SELNEZ ret, v1, c1
> > OR ret, ret, TMP1
> >
> > Which does the following:
> > ret = cond ? v1 : v2
> >
> > Signed-off-by: James Hogan
> > Cc: Richard Henderson
> > Cc: Aurelien Jarno
>
> Reviewed-by: Richard Henderson
Thanks for the reviewing!
>
>
> > { INDEX_op_brcond_i32, { "rZ", "rZ" } },
> > +#if !use_mips32r6_instructions
> > { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rZ", "0" } },
> > +#else
> > +{ INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rZ", "rZ" } },
> > +#endif
>
>
> The only thing I'd change is preferring positive tests to negative ones. So
> swap the order of these lines, and the sense of the #if.
No problem. Shall I do a full resend for that, or can it be fixed up by
whoever applies?
Cheers
James
>
> Leon, do you want to take this as a mips maintainer, or shall I as tcg
> maintainer?
>
>
> r~
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Re: [Qemu-devel] [PATCH v3 6/6] tcg/mips: Support r6 SEL{NE, EQ}Z instead of MOVN/MOVZ
On 10/02/2015 10:24 PM, James Hogan wrote:
Extend MIPS movcond implementation to support the SELNEZ/SELEQZ
instructions introduced in MIPS r6 (where MOVN/MOVZ have been removed).
Whereas the "MOVN/MOVZ rd, rs, rt" instructions have the following
semantics:
rd = [!]rt ? rs : rd
The "SELNEZ/SELEQZ rd, rs, rt" instructions are slightly different:
rd = [!]rt ? rs : 0
First we ensure that if one of the movcond input values is zero that it
comes last (we can swap the input arguments if we invert the condition).
This is so that it can exactly match one of the SELNEZ/SELEQZ
instructions and avoid the need to emit the other one.
Otherwise we emit the opposite instruction first into a temporary
register, and OR that into the result:
SELNEZ/SELEQZ TMP1, v2, c1
SELEQZ/SELNEZ ret, v1, c1
OR ret, ret, TMP1
Which does the following:
ret = cond ? v1 : v2
Signed-off-by: James Hogan
Cc: Richard Henderson
Cc: Aurelien Jarno
Reviewed-by: Richard Henderson
{ INDEX_op_brcond_i32, { "rZ", "rZ" } },
+#if !use_mips32r6_instructions
{ INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rZ", "0" } },
+#else
+{ INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rZ", "rZ" } },
+#endif
The only thing I'd change is preferring positive tests to negative ones. So
swap the order of these lines, and the sense of the #if.
Leon, do you want to take this as a mips maintainer, or shall I as tcg
maintainer?
r~
