Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD Processor Cache Information

2018-03-27 Thread Moger, Babu 


> -Original Message-
> From: Eduardo Habkost <ehabk...@redhat.com>
> Sent: Wednesday, March 21, 2018 3:30 PM
> To: Moger, Babu <babu.mo...@amd.com>
> Cc: pbonz...@redhat.com; r...@twiddle.net; rkrc...@redhat.com;
> Lendacky, Thomas <thomas.lenda...@amd.com>; Singh, Brijesh
> <brijesh.si...@amd.com>; k...@vger.kernel.org; k...@tripleback.net;
> mtosa...@redhat.com; Hook, Gary <gary.h...@amd.com>; qemu-
> de...@nongnu.org
> Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> Processor Cache Information
> 
> On Wed, Mar 21, 2018 at 08:07:54PM +, Moger, Babu wrote:
> >
> > > -Original Message-
> > > From: Eduardo Habkost <ehabk...@redhat.com>
> > > Sent: Wednesday, March 21, 2018 1:15 PM
> > > To: Moger, Babu <babu.mo...@amd.com>
> > > Cc: pbonz...@redhat.com; r...@twiddle.net; rkrc...@redhat.com;
> > > Lendacky, Thomas <thomas.lenda...@amd.com>; Singh, Brijesh
> > > <brijesh.si...@amd.com>; k...@vger.kernel.org; k...@tripleback.net;
> > > mtosa...@redhat.com; Hook, Gary <gary.h...@amd.com>; qemu-
> > > de...@nongnu.org
> > > Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> > > Processor Cache Information
> > >
> > > On Wed, Mar 21, 2018 at 05:47:28PM +, Moger, Babu wrote:
> > > >
> > > >
> > > > > -Original Message-
> > > > > From: Eduardo Habkost <ehabk...@redhat.com>
> > > > > Sent: Wednesday, March 21, 2018 12:10 PM
> > > > > To: Moger, Babu <babu.mo...@amd.com>
> > > > > Cc: pbonz...@redhat.com; r...@twiddle.net; rkrc...@redhat.com;
> > > > > Lendacky, Thomas <thomas.lenda...@amd.com>; Singh, Brijesh
> > > > > <brijesh.si...@amd.com>; k...@vger.kernel.org;
> k...@tripleback.net;
> > > > > mtosa...@redhat.com; Hook, Gary <gary.h...@amd.com>; qemu-
> > > > > de...@nongnu.org
> > > > > Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> > > > > Processor Cache Information
> > > > >
> > > > > On Wed, Mar 21, 2018 at 03:58:41PM +, Moger, Babu wrote:
> > > > > > Hi Eduardo,
> > > > > >
> > > > > > > -Original Message-
> > > > > > > From: Eduardo Habkost <ehabk...@redhat.com>
> > > > > > > Sent: Tuesday, March 20, 2018 12:54 PM
> > > > > > > To: Moger, Babu <babu.mo...@amd.com>
> > > > > > > Cc: pbonz...@redhat.com; r...@twiddle.net;
> rkrc...@redhat.com;
> > > > > > > Lendacky, Thomas <thomas.lenda...@amd.com>; Singh, Brijesh
> > > > > > > <brijesh.si...@amd.com>; k...@vger.kernel.org;
> > > k...@tripleback.net;
> > > > > > > mtosa...@redhat.com; Hook, Gary <gary.h...@amd.com>;
> qemu-
> > > > > > > de...@nongnu.org
> > > > > > > Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate
> AMD
> > > > > > > Processor Cache Information
> > > > > > >
> > > > > > > On Tue, Mar 20, 2018 at 05:25:52PM +, Moger, Babu wrote:
> > > > > > > > Hi Eduardo, Thanks for the comments. Please see the response
> > > inline.
> > > > > > > >
> > > > > > > > > -Original Message-
> > > > > > > > > From: Eduardo Habkost <ehabk...@redhat.com>
> > > > > > > > > Sent: Friday, March 16, 2018 1:00 PM
> > > > > > > > > To: Moger, Babu <babu.mo...@amd.com>
> > > > > > > > > Cc: pbonz...@redhat.com; r...@twiddle.net;
> > > rkrc...@redhat.com;
> > > > > > > > > Lendacky, Thomas <thomas.lenda...@amd.com>; Singh,
> Brijesh
> > > > > > > > > <brijesh.si...@amd.com>; k...@vger.kernel.org;
> > > > > k...@tripleback.net;
> > > > > > > > > mtosa...@redhat.com; Hook, Gary <gary.h...@amd.com>;
> > > qemu-
> > > > > > > > > de...@nongnu.org
> > > > > > > > > Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386:
> Populate
> > > AMD
> > > > > > > > > Processor Cache Information
> > > > > > > > >
> > > > > > > > > On Mon, Ma

Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD Processor Cache Information

2018-03-21 Thread Eduardo Habkost 
On Wed, Mar 21, 2018 at 08:07:54PM +, Moger, Babu wrote:
> 
> > -Original Message-
> > From: Eduardo Habkost <ehabk...@redhat.com>
> > Sent: Wednesday, March 21, 2018 1:15 PM
> > To: Moger, Babu <babu.mo...@amd.com>
> > Cc: pbonz...@redhat.com; r...@twiddle.net; rkrc...@redhat.com;
> > Lendacky, Thomas <thomas.lenda...@amd.com>; Singh, Brijesh
> > <brijesh.si...@amd.com>; k...@vger.kernel.org; k...@tripleback.net;
> > mtosa...@redhat.com; Hook, Gary <gary.h...@amd.com>; qemu-
> > de...@nongnu.org
> > Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> > Processor Cache Information
> > 
> > On Wed, Mar 21, 2018 at 05:47:28PM +, Moger, Babu wrote:
> > >
> > >
> > > > -Original Message-
> > > > From: Eduardo Habkost <ehabk...@redhat.com>
> > > > Sent: Wednesday, March 21, 2018 12:10 PM
> > > > To: Moger, Babu <babu.mo...@amd.com>
> > > > Cc: pbonz...@redhat.com; r...@twiddle.net; rkrc...@redhat.com;
> > > > Lendacky, Thomas <thomas.lenda...@amd.com>; Singh, Brijesh
> > > > <brijesh.si...@amd.com>; k...@vger.kernel.org; k...@tripleback.net;
> > > > mtosa...@redhat.com; Hook, Gary <gary.h...@amd.com>; qemu-
> > > > de...@nongnu.org
> > > > Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> > > > Processor Cache Information
> > > >
> > > > On Wed, Mar 21, 2018 at 03:58:41PM +, Moger, Babu wrote:
> > > > > Hi Eduardo,
> > > > >
> > > > > > -Original Message-
> > > > > > From: Eduardo Habkost <ehabk...@redhat.com>
> > > > > > Sent: Tuesday, March 20, 2018 12:54 PM
> > > > > > To: Moger, Babu <babu.mo...@amd.com>
> > > > > > Cc: pbonz...@redhat.com; r...@twiddle.net; rkrc...@redhat.com;
> > > > > > Lendacky, Thomas <thomas.lenda...@amd.com>; Singh, Brijesh
> > > > > > <brijesh.si...@amd.com>; k...@vger.kernel.org;
> > k...@tripleback.net;
> > > > > > mtosa...@redhat.com; Hook, Gary <gary.h...@amd.com>; qemu-
> > > > > > de...@nongnu.org
> > > > > > Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> > > > > > Processor Cache Information
> > > > > >
> > > > > > On Tue, Mar 20, 2018 at 05:25:52PM +, Moger, Babu wrote:
> > > > > > > Hi Eduardo, Thanks for the comments. Please see the response
> > inline.
> > > > > > >
> > > > > > > > -Original Message-
> > > > > > > > From: Eduardo Habkost <ehabk...@redhat.com>
> > > > > > > > Sent: Friday, March 16, 2018 1:00 PM
> > > > > > > > To: Moger, Babu <babu.mo...@amd.com>
> > > > > > > > Cc: pbonz...@redhat.com; r...@twiddle.net;
> > rkrc...@redhat.com;
> > > > > > > > Lendacky, Thomas <thomas.lenda...@amd.com>; Singh, Brijesh
> > > > > > > > <brijesh.si...@amd.com>; k...@vger.kernel.org;
> > > > k...@tripleback.net;
> > > > > > > > mtosa...@redhat.com; Hook, Gary <gary.h...@amd.com>;
> > qemu-
> > > > > > > > de...@nongnu.org
> > > > > > > > Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate
> > AMD
> > > > > > > > Processor Cache Information
> > > > > > > >
> > > > > > > > On Mon, Mar 12, 2018 at 05:00:46PM -0400, Babu Moger wrote:
> > > > > > > > > From: Stanislav Lanci <p...@polepetko.eu>
> > > > > > > > >
> > > > > > > > > Add information for cpuid 0x801D leaf. Populate cache
> > topology
> > > > > > > > information
> > > > > > > > > for different cache types(Data Cache, Instruction Cache, L2 
> > > > > > > > > and
> > L3)
> > > > > > > > supported
> > > > > > > > > by 0x801D leaf. Please refer Processor Programming
> > Reference
> > > > > > (PPR)
> > > > > > > > for AMD
> > > > > > > > > Family 17h Model for more details.
> > > > > > > > >
> > > > > > > > > Signed-off-by: Stan

Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD Processor Cache Information

2018-03-21 Thread Moger, Babu 

> -Original Message-
> From: Eduardo Habkost <ehabk...@redhat.com>
> Sent: Wednesday, March 21, 2018 1:15 PM
> To: Moger, Babu <babu.mo...@amd.com>
> Cc: pbonz...@redhat.com; r...@twiddle.net; rkrc...@redhat.com;
> Lendacky, Thomas <thomas.lenda...@amd.com>; Singh, Brijesh
> <brijesh.si...@amd.com>; k...@vger.kernel.org; k...@tripleback.net;
> mtosa...@redhat.com; Hook, Gary <gary.h...@amd.com>; qemu-
> de...@nongnu.org
> Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> Processor Cache Information
> 
> On Wed, Mar 21, 2018 at 05:47:28PM +, Moger, Babu wrote:
> >
> >
> > > -Original Message-
> > > From: Eduardo Habkost <ehabk...@redhat.com>
> > > Sent: Wednesday, March 21, 2018 12:10 PM
> > > To: Moger, Babu <babu.mo...@amd.com>
> > > Cc: pbonz...@redhat.com; r...@twiddle.net; rkrc...@redhat.com;
> > > Lendacky, Thomas <thomas.lenda...@amd.com>; Singh, Brijesh
> > > <brijesh.si...@amd.com>; k...@vger.kernel.org; k...@tripleback.net;
> > > mtosa...@redhat.com; Hook, Gary <gary.h...@amd.com>; qemu-
> > > de...@nongnu.org
> > > Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> > > Processor Cache Information
> > >
> > > On Wed, Mar 21, 2018 at 03:58:41PM +, Moger, Babu wrote:
> > > > Hi Eduardo,
> > > >
> > > > > -Original Message-
> > > > > From: Eduardo Habkost <ehabk...@redhat.com>
> > > > > Sent: Tuesday, March 20, 2018 12:54 PM
> > > > > To: Moger, Babu <babu.mo...@amd.com>
> > > > > Cc: pbonz...@redhat.com; r...@twiddle.net; rkrc...@redhat.com;
> > > > > Lendacky, Thomas <thomas.lenda...@amd.com>; Singh, Brijesh
> > > > > <brijesh.si...@amd.com>; k...@vger.kernel.org;
> k...@tripleback.net;
> > > > > mtosa...@redhat.com; Hook, Gary <gary.h...@amd.com>; qemu-
> > > > > de...@nongnu.org
> > > > > Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> > > > > Processor Cache Information
> > > > >
> > > > > On Tue, Mar 20, 2018 at 05:25:52PM +, Moger, Babu wrote:
> > > > > > Hi Eduardo, Thanks for the comments. Please see the response
> inline.
> > > > > >
> > > > > > > -Original Message-
> > > > > > > From: Eduardo Habkost <ehabk...@redhat.com>
> > > > > > > Sent: Friday, March 16, 2018 1:00 PM
> > > > > > > To: Moger, Babu <babu.mo...@amd.com>
> > > > > > > Cc: pbonz...@redhat.com; r...@twiddle.net;
> rkrc...@redhat.com;
> > > > > > > Lendacky, Thomas <thomas.lenda...@amd.com>; Singh, Brijesh
> > > > > > > <brijesh.si...@amd.com>; k...@vger.kernel.org;
> > > k...@tripleback.net;
> > > > > > > mtosa...@redhat.com; Hook, Gary <gary.h...@amd.com>;
> qemu-
> > > > > > > de...@nongnu.org
> > > > > > > Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate
> AMD
> > > > > > > Processor Cache Information
> > > > > > >
> > > > > > > On Mon, Mar 12, 2018 at 05:00:46PM -0400, Babu Moger wrote:
> > > > > > > > From: Stanislav Lanci <p...@polepetko.eu>
> > > > > > > >
> > > > > > > > Add information for cpuid 0x801D leaf. Populate cache
> topology
> > > > > > > information
> > > > > > > > for different cache types(Data Cache, Instruction Cache, L2 and
> L3)
> > > > > > > supported
> > > > > > > > by 0x801D leaf. Please refer Processor Programming
> Reference
> > > > > (PPR)
> > > > > > > for AMD
> > > > > > > > Family 17h Model for more details.
> > > > > > > >
> > > > > > > > Signed-off-by: Stanislav Lanci <p...@polepetko.eu>
> > > > > > > > Signed-off-by: Babu Moger <babu.mo...@amd.com>
> > > > > > >
> > > > > > > The new CPUID leaves don't seem to match the existing AMD
> cache
> > > > > > > information
> > > > > > > leaves.  Is this intentional?  Why?
> > > > > >
> > > > > > It is not intentional. These values are from older family

Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD Processor Cache Information

2018-03-21 Thread Eduardo Habkost 
On Wed, Mar 21, 2018 at 05:47:28PM +, Moger, Babu wrote:
> 
> 
> > -Original Message-
> > From: Eduardo Habkost <ehabk...@redhat.com>
> > Sent: Wednesday, March 21, 2018 12:10 PM
> > To: Moger, Babu <babu.mo...@amd.com>
> > Cc: pbonz...@redhat.com; r...@twiddle.net; rkrc...@redhat.com;
> > Lendacky, Thomas <thomas.lenda...@amd.com>; Singh, Brijesh
> > <brijesh.si...@amd.com>; k...@vger.kernel.org; k...@tripleback.net;
> > mtosa...@redhat.com; Hook, Gary <gary.h...@amd.com>; qemu-
> > de...@nongnu.org
> > Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> > Processor Cache Information
> > 
> > On Wed, Mar 21, 2018 at 03:58:41PM +, Moger, Babu wrote:
> > > Hi Eduardo,
> > >
> > > > -Original Message-
> > > > From: Eduardo Habkost <ehabk...@redhat.com>
> > > > Sent: Tuesday, March 20, 2018 12:54 PM
> > > > To: Moger, Babu <babu.mo...@amd.com>
> > > > Cc: pbonz...@redhat.com; r...@twiddle.net; rkrc...@redhat.com;
> > > > Lendacky, Thomas <thomas.lenda...@amd.com>; Singh, Brijesh
> > > > <brijesh.si...@amd.com>; k...@vger.kernel.org; k...@tripleback.net;
> > > > mtosa...@redhat.com; Hook, Gary <gary.h...@amd.com>; qemu-
> > > > de...@nongnu.org
> > > > Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> > > > Processor Cache Information
> > > >
> > > > On Tue, Mar 20, 2018 at 05:25:52PM +, Moger, Babu wrote:
> > > > > Hi Eduardo, Thanks for the comments. Please see the response inline.
> > > > >
> > > > > > -Original Message-
> > > > > > From: Eduardo Habkost <ehabk...@redhat.com>
> > > > > > Sent: Friday, March 16, 2018 1:00 PM
> > > > > > To: Moger, Babu <babu.mo...@amd.com>
> > > > > > Cc: pbonz...@redhat.com; r...@twiddle.net; rkrc...@redhat.com;
> > > > > > Lendacky, Thomas <thomas.lenda...@amd.com>; Singh, Brijesh
> > > > > > <brijesh.si...@amd.com>; k...@vger.kernel.org;
> > k...@tripleback.net;
> > > > > > mtosa...@redhat.com; Hook, Gary <gary.h...@amd.com>; qemu-
> > > > > > de...@nongnu.org
> > > > > > Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> > > > > > Processor Cache Information
> > > > > >
> > > > > > On Mon, Mar 12, 2018 at 05:00:46PM -0400, Babu Moger wrote:
> > > > > > > From: Stanislav Lanci <p...@polepetko.eu>
> > > > > > >
> > > > > > > Add information for cpuid 0x801D leaf. Populate cache topology
> > > > > > information
> > > > > > > for different cache types(Data Cache, Instruction Cache, L2 and 
> > > > > > > L3)
> > > > > > supported
> > > > > > > by 0x801D leaf. Please refer Processor Programming Reference
> > > > (PPR)
> > > > > > for AMD
> > > > > > > Family 17h Model for more details.
> > > > > > >
> > > > > > > Signed-off-by: Stanislav Lanci <p...@polepetko.eu>
> > > > > > > Signed-off-by: Babu Moger <babu.mo...@amd.com>
> > > > > >
> > > > > > The new CPUID leaves don't seem to match the existing AMD cache
> > > > > > information
> > > > > > leaves.  Is this intentional?  Why?
> > > > >
> > > > > It is not intentional. These values are from older family of 
> > > > > processors.
> > > > These values have changed from Family 14  or later.
> > > > > The latest one is Family 17. You can see the differences here.
> > > > >  https://support.amd.com/TechDocs/41131.pdf
> > > > >
> > > >
> > https://support.amd.com/TechDocs/55072_AMD_Family_15h_Models_70h-
> > > > 7Fh_BKDG.pdf
> > > > >
> > > >
> > https://support.amd.com/TechDocs/54945_PPR_Family_17h_Models_00h-
> > > > 0Fh.pdf
> > > > >
> > > > > Some of these are bugs in our code. For some we need to add checks
> > for
> > > > the family and correct these values.
> > > > > You understand the code much better than me. Correct me if I missed
> > > > something.
> > > > >
> > > > > Note that o

Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD Processor Cache Information

2018-03-21 Thread Moger, Babu 


> -Original Message-
> From: Eduardo Habkost <ehabk...@redhat.com>
> Sent: Wednesday, March 21, 2018 12:10 PM
> To: Moger, Babu <babu.mo...@amd.com>
> Cc: pbonz...@redhat.com; r...@twiddle.net; rkrc...@redhat.com;
> Lendacky, Thomas <thomas.lenda...@amd.com>; Singh, Brijesh
> <brijesh.si...@amd.com>; k...@vger.kernel.org; k...@tripleback.net;
> mtosa...@redhat.com; Hook, Gary <gary.h...@amd.com>; qemu-
> de...@nongnu.org
> Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> Processor Cache Information
> 
> On Wed, Mar 21, 2018 at 03:58:41PM +, Moger, Babu wrote:
> > Hi Eduardo,
> >
> > > -Original Message-
> > > From: Eduardo Habkost <ehabk...@redhat.com>
> > > Sent: Tuesday, March 20, 2018 12:54 PM
> > > To: Moger, Babu <babu.mo...@amd.com>
> > > Cc: pbonz...@redhat.com; r...@twiddle.net; rkrc...@redhat.com;
> > > Lendacky, Thomas <thomas.lenda...@amd.com>; Singh, Brijesh
> > > <brijesh.si...@amd.com>; k...@vger.kernel.org; k...@tripleback.net;
> > > mtosa...@redhat.com; Hook, Gary <gary.h...@amd.com>; qemu-
> > > de...@nongnu.org
> > > Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> > > Processor Cache Information
> > >
> > > On Tue, Mar 20, 2018 at 05:25:52PM +, Moger, Babu wrote:
> > > > Hi Eduardo, Thanks for the comments. Please see the response inline.
> > > >
> > > > > -Original Message-
> > > > > From: Eduardo Habkost <ehabk...@redhat.com>
> > > > > Sent: Friday, March 16, 2018 1:00 PM
> > > > > To: Moger, Babu <babu.mo...@amd.com>
> > > > > Cc: pbonz...@redhat.com; r...@twiddle.net; rkrc...@redhat.com;
> > > > > Lendacky, Thomas <thomas.lenda...@amd.com>; Singh, Brijesh
> > > > > <brijesh.si...@amd.com>; k...@vger.kernel.org;
> k...@tripleback.net;
> > > > > mtosa...@redhat.com; Hook, Gary <gary.h...@amd.com>; qemu-
> > > > > de...@nongnu.org
> > > > > Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> > > > > Processor Cache Information
> > > > >
> > > > > On Mon, Mar 12, 2018 at 05:00:46PM -0400, Babu Moger wrote:
> > > > > > From: Stanislav Lanci <p...@polepetko.eu>
> > > > > >
> > > > > > Add information for cpuid 0x801D leaf. Populate cache topology
> > > > > information
> > > > > > for different cache types(Data Cache, Instruction Cache, L2 and L3)
> > > > > supported
> > > > > > by 0x801D leaf. Please refer Processor Programming Reference
> > > (PPR)
> > > > > for AMD
> > > > > > Family 17h Model for more details.
> > > > > >
> > > > > > Signed-off-by: Stanislav Lanci <p...@polepetko.eu>
> > > > > > Signed-off-by: Babu Moger <babu.mo...@amd.com>
> > > > >
> > > > > The new CPUID leaves don't seem to match the existing AMD cache
> > > > > information
> > > > > leaves.  Is this intentional?  Why?
> > > >
> > > > It is not intentional. These values are from older family of processors.
> > > These values have changed from Family 14  or later.
> > > > The latest one is Family 17. You can see the differences here.
> > > >  https://support.amd.com/TechDocs/41131.pdf
> > > >
> > >
> https://support.amd.com/TechDocs/55072_AMD_Family_15h_Models_70h-
> > > 7Fh_BKDG.pdf
> > > >
> > >
> https://support.amd.com/TechDocs/54945_PPR_Family_17h_Models_00h-
> > > 0Fh.pdf
> > > >
> > > > Some of these are bugs in our code. For some we need to add checks
> for
> > > the family and correct these values.
> > > > You understand the code much better than me. Correct me if I missed
> > > something.
> > > >
> > > > Note that older family of processors don't support topology extensions.
> > >
> > > If you want to make the cache size/topology look different
> > > depending on the CPU model/options, this would require more work,
> > > but it would be an interesting feature.
> > >
> > > The "i386: Helpers to encode cache information consistently"
> > > patch I sent last week might be a useful starting point for that.
> > >
> > > If you plan to implement that, please kee

Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD Processor Cache Information

2018-03-21 Thread Kash Pande 
On 2018-03-21 01:09 PM, Eduardo Habkost wrote:
> This makes sense if you want to change a CPU model to enable
> topoext by default.  But I suggest setting it for
> ("EPYC" "-" TYPE_X86_CPU) only, not TYPE_X86_CPU, as EPYC is the
> only CPU model affected by patch 4/5.


AIUI, all 17h CPUs have TOPOEXT and SMT support. I've been in contact
with Babu to have the patches extended to more general use case.



Kash




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Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD Processor Cache Information

2018-03-21 Thread Eduardo Habkost 
On Wed, Mar 21, 2018 at 03:58:41PM +, Moger, Babu wrote:
> Hi Eduardo,
> 
> > -Original Message-
> > From: Eduardo Habkost <ehabk...@redhat.com>
> > Sent: Tuesday, March 20, 2018 12:54 PM
> > To: Moger, Babu <babu.mo...@amd.com>
> > Cc: pbonz...@redhat.com; r...@twiddle.net; rkrc...@redhat.com;
> > Lendacky, Thomas <thomas.lenda...@amd.com>; Singh, Brijesh
> > <brijesh.si...@amd.com>; k...@vger.kernel.org; k...@tripleback.net;
> > mtosa...@redhat.com; Hook, Gary <gary.h...@amd.com>; qemu-
> > de...@nongnu.org
> > Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> > Processor Cache Information
> > 
> > On Tue, Mar 20, 2018 at 05:25:52PM +, Moger, Babu wrote:
> > > Hi Eduardo, Thanks for the comments. Please see the response inline.
> > >
> > > > -Original Message-
> > > > From: Eduardo Habkost <ehabk...@redhat.com>
> > > > Sent: Friday, March 16, 2018 1:00 PM
> > > > To: Moger, Babu <babu.mo...@amd.com>
> > > > Cc: pbonz...@redhat.com; r...@twiddle.net; rkrc...@redhat.com;
> > > > Lendacky, Thomas <thomas.lenda...@amd.com>; Singh, Brijesh
> > > > <brijesh.si...@amd.com>; k...@vger.kernel.org; k...@tripleback.net;
> > > > mtosa...@redhat.com; Hook, Gary <gary.h...@amd.com>; qemu-
> > > > de...@nongnu.org
> > > > Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> > > > Processor Cache Information
> > > >
> > > > On Mon, Mar 12, 2018 at 05:00:46PM -0400, Babu Moger wrote:
> > > > > From: Stanislav Lanci <p...@polepetko.eu>
> > > > >
> > > > > Add information for cpuid 0x801D leaf. Populate cache topology
> > > > information
> > > > > for different cache types(Data Cache, Instruction Cache, L2 and L3)
> > > > supported
> > > > > by 0x801D leaf. Please refer Processor Programming Reference
> > (PPR)
> > > > for AMD
> > > > > Family 17h Model for more details.
> > > > >
> > > > > Signed-off-by: Stanislav Lanci <p...@polepetko.eu>
> > > > > Signed-off-by: Babu Moger <babu.mo...@amd.com>
> > > >
> > > > The new CPUID leaves don't seem to match the existing AMD cache
> > > > information
> > > > leaves.  Is this intentional?  Why?
> > >
> > > It is not intentional. These values are from older family of processors.
> > These values have changed from Family 14  or later.
> > > The latest one is Family 17. You can see the differences here.
> > >  https://support.amd.com/TechDocs/41131.pdf
> > >
> > https://support.amd.com/TechDocs/55072_AMD_Family_15h_Models_70h-
> > 7Fh_BKDG.pdf
> > >
> > https://support.amd.com/TechDocs/54945_PPR_Family_17h_Models_00h-
> > 0Fh.pdf
> > >
> > > Some of these are bugs in our code. For some we need to add checks for
> > the family and correct these values.
> > > You understand the code much better than me. Correct me if I missed
> > something.
> > >
> > > Note that older family of processors don't support topology extensions.
> > 
> > If you want to make the cache size/topology look different
> > depending on the CPU model/options, this would require more work,
> > but it would be an interesting feature.
> > 
> > The "i386: Helpers to encode cache information consistently"
> > patch I sent last week might be a useful starting point for that.
> > 
> > If you plan to implement that, please keep in mind that existing
> > CPUID cache info needs to be kept on previous machine-types (this
> > is implemented by adding QOM properties that can be used to
> > enable the old behavior, and by setting them at
> > MachineClass::compat_props).
> 
> Wanted to get some confirmation what you meant by setting 
> MachineClass::compat_props.
> Here is the patch I created to add new property for cpu. Now, I can use 
> enable_topoext to display
> new  change properly based on family.  Is that what you meant ?  

If the only change you introduce in the defaults is enabling
topoext but keeping the same default cache sizes, the example
following would make sense (but see comments below about
implementation details).

But if you also want to change the default cache size, you will
also need properties that control the cache size.

(In theory, you could make the "topoext" property control the
cache size too, but I don't see why the cache size sh

Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD Processor Cache Information

2018-03-21 Thread Moger, Babu 
Hi Eduardo,

> -Original Message-
> From: Eduardo Habkost <ehabk...@redhat.com>
> Sent: Tuesday, March 20, 2018 12:54 PM
> To: Moger, Babu <babu.mo...@amd.com>
> Cc: pbonz...@redhat.com; r...@twiddle.net; rkrc...@redhat.com;
> Lendacky, Thomas <thomas.lenda...@amd.com>; Singh, Brijesh
> <brijesh.si...@amd.com>; k...@vger.kernel.org; k...@tripleback.net;
> mtosa...@redhat.com; Hook, Gary <gary.h...@amd.com>; qemu-
> de...@nongnu.org
> Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> Processor Cache Information
> 
> On Tue, Mar 20, 2018 at 05:25:52PM +, Moger, Babu wrote:
> > Hi Eduardo, Thanks for the comments. Please see the response inline.
> >
> > > -Original Message-
> > > From: Eduardo Habkost <ehabk...@redhat.com>
> > > Sent: Friday, March 16, 2018 1:00 PM
> > > To: Moger, Babu <babu.mo...@amd.com>
> > > Cc: pbonz...@redhat.com; r...@twiddle.net; rkrc...@redhat.com;
> > > Lendacky, Thomas <thomas.lenda...@amd.com>; Singh, Brijesh
> > > <brijesh.si...@amd.com>; k...@vger.kernel.org; k...@tripleback.net;
> > > mtosa...@redhat.com; Hook, Gary <gary.h...@amd.com>; qemu-
> > > de...@nongnu.org
> > > Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> > > Processor Cache Information
> > >
> > > On Mon, Mar 12, 2018 at 05:00:46PM -0400, Babu Moger wrote:
> > > > From: Stanislav Lanci <p...@polepetko.eu>
> > > >
> > > > Add information for cpuid 0x801D leaf. Populate cache topology
> > > information
> > > > for different cache types(Data Cache, Instruction Cache, L2 and L3)
> > > supported
> > > > by 0x801D leaf. Please refer Processor Programming Reference
> (PPR)
> > > for AMD
> > > > Family 17h Model for more details.
> > > >
> > > > Signed-off-by: Stanislav Lanci <p...@polepetko.eu>
> > > > Signed-off-by: Babu Moger <babu.mo...@amd.com>
> > >
> > > The new CPUID leaves don't seem to match the existing AMD cache
> > > information
> > > leaves.  Is this intentional?  Why?
> >
> > It is not intentional. These values are from older family of processors.
> These values have changed from Family 14  or later.
> > The latest one is Family 17. You can see the differences here.
> >  https://support.amd.com/TechDocs/41131.pdf
> >
> https://support.amd.com/TechDocs/55072_AMD_Family_15h_Models_70h-
> 7Fh_BKDG.pdf
> >
> https://support.amd.com/TechDocs/54945_PPR_Family_17h_Models_00h-
> 0Fh.pdf
> >
> > Some of these are bugs in our code. For some we need to add checks for
> the family and correct these values.
> > You understand the code much better than me. Correct me if I missed
> something.
> >
> > Note that older family of processors don't support topology extensions.
> 
> If you want to make the cache size/topology look different
> depending on the CPU model/options, this would require more work,
> but it would be an interesting feature.
> 
> The "i386: Helpers to encode cache information consistently"
> patch I sent last week might be a useful starting point for that.
> 
> If you plan to implement that, please keep in mind that existing
> CPUID cache info needs to be kept on previous machine-types (this
> is implemented by adding QOM properties that can be used to
> enable the old behavior, and by setting them at
> MachineClass::compat_props).

Wanted to get some confirmation what you meant by setting 
MachineClass::compat_props.
Here is the patch I created to add new property for cpu. Now, I can use 
enable_topoext to display
new  change properly based on family.  Is that what you meant ?  


diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index ffee841..d1ee053 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -369,6 +369,11 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
 HW_COMPAT_2_7 \
 {\
 .driver   = TYPE_X86_CPU,\
+.property = "topoext",\
+.value= "off",\
+},\
+{\
+.driver   = TYPE_X86_CPU,\
 .property = "l3-cache",\
 .value= "off",\
 },\
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 84d64de..557a2d6 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5080,6 +5080,7 @@ static Property x86_cpu_properties[] = {
  false),
 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
+DEFINE_PROP_BOOL("topoext", X86CPU, enable_topoext, true),

 /*
  * From "Requirements for Implementing the Microsoft
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 2e2bab5..3d3caa1 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1333,6 +1333,11 @@ struct X86CPU {
  */
 bool enable_l3_cache;

+/* Compatibility bits for old machine types.
+ * If true present the new cache topology information
+ */
+bool enable_topoext;
+
 /* Compatibility bits for old machine types: */
 bool enable_cpuid_0xb;



> 
> --
> Eduardo

Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD Processor Cache Information

2018-03-20 Thread Moger, Babu 


> -Original Message-
> From: Eduardo Habkost <ehabk...@redhat.com>
> Sent: Tuesday, March 20, 2018 12:54 PM
> To: Moger, Babu <babu.mo...@amd.com>
> Cc: pbonz...@redhat.com; r...@twiddle.net; rkrc...@redhat.com;
> Lendacky, Thomas <thomas.lenda...@amd.com>; Singh, Brijesh
> <brijesh.si...@amd.com>; k...@vger.kernel.org; k...@tripleback.net;
> mtosa...@redhat.com; Hook, Gary <gary.h...@amd.com>; qemu-
> de...@nongnu.org
> Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> Processor Cache Information
> 
> On Tue, Mar 20, 2018 at 05:25:52PM +, Moger, Babu wrote:
> > Hi Eduardo, Thanks for the comments. Please see the response inline.
> >
> > > -Original Message-
> > > From: Eduardo Habkost <ehabk...@redhat.com>
> > > Sent: Friday, March 16, 2018 1:00 PM
> > > To: Moger, Babu <babu.mo...@amd.com>
> > > Cc: pbonz...@redhat.com; r...@twiddle.net; rkrc...@redhat.com;
> > > Lendacky, Thomas <thomas.lenda...@amd.com>; Singh, Brijesh
> > > <brijesh.si...@amd.com>; k...@vger.kernel.org; k...@tripleback.net;
> > > mtosa...@redhat.com; Hook, Gary <gary.h...@amd.com>; qemu-
> > > de...@nongnu.org
> > > Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> > > Processor Cache Information
> > >
> > > On Mon, Mar 12, 2018 at 05:00:46PM -0400, Babu Moger wrote:
> > > > From: Stanislav Lanci <p...@polepetko.eu>
> > > >
> > > > Add information for cpuid 0x801D leaf. Populate cache topology
> > > information
> > > > for different cache types(Data Cache, Instruction Cache, L2 and L3)
> > > supported
> > > > by 0x801D leaf. Please refer Processor Programming Reference
> (PPR)
> > > for AMD
> > > > Family 17h Model for more details.
> > > >
> > > > Signed-off-by: Stanislav Lanci <p...@polepetko.eu>
> > > > Signed-off-by: Babu Moger <babu.mo...@amd.com>
> > >
> > > The new CPUID leaves don't seem to match the existing AMD cache
> > > information
> > > leaves.  Is this intentional?  Why?
> >
> > It is not intentional. These values are from older family of processors.
> These values have changed from Family 14  or later.
> > The latest one is Family 17. You can see the differences here.
> >  https://support.amd.com/TechDocs/41131.pdf
> >
> https://support.amd.com/TechDocs/55072_AMD_Family_15h_Models_70h-
> 7Fh_BKDG.pdf
> >
> https://support.amd.com/TechDocs/54945_PPR_Family_17h_Models_00h-
> 0Fh.pdf
> >
> > Some of these are bugs in our code. For some we need to add checks for
> the family and correct these values.
> > You understand the code much better than me. Correct me if I missed
> something.
> >
> > Note that older family of processors don't support topology extensions.
> 
> If you want to make the cache size/topology look different
> depending on the CPU model/options, this would require more work,
> but it would be an interesting feature.
> 
> The "i386: Helpers to encode cache information consistently"
> patch I sent last week might be a useful starting point for that.

Yes. Looking at your patch.
> 
> If you plan to implement that, please keep in mind that existing
> CPUID cache info needs to be kept on previous machine-types (this
> is implemented by adding QOM properties that can be used to
> enable the old behavior, and by setting them at
> MachineClass::compat_props).

Yes. Will look into it.  This code is new to me.  Let me take a look.
Thanks

> 
> --
> Eduardo

Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD Processor Cache Information

2018-03-20 Thread Eduardo Habkost 
On Tue, Mar 20, 2018 at 05:25:52PM +, Moger, Babu wrote:
> Hi Eduardo, Thanks for the comments. Please see the response inline.
> 
> > -Original Message-
> > From: Eduardo Habkost <ehabk...@redhat.com>
> > Sent: Friday, March 16, 2018 1:00 PM
> > To: Moger, Babu <babu.mo...@amd.com>
> > Cc: pbonz...@redhat.com; r...@twiddle.net; rkrc...@redhat.com;
> > Lendacky, Thomas <thomas.lenda...@amd.com>; Singh, Brijesh
> > <brijesh.si...@amd.com>; k...@vger.kernel.org; k...@tripleback.net;
> > mtosa...@redhat.com; Hook, Gary <gary.h...@amd.com>; qemu-
> > de...@nongnu.org
> > Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> > Processor Cache Information
> > 
> > On Mon, Mar 12, 2018 at 05:00:46PM -0400, Babu Moger wrote:
> > > From: Stanislav Lanci <p...@polepetko.eu>
> > >
> > > Add information for cpuid 0x801D leaf. Populate cache topology
> > information
> > > for different cache types(Data Cache, Instruction Cache, L2 and L3)
> > supported
> > > by 0x801D leaf. Please refer Processor Programming Reference (PPR)
> > for AMD
> > > Family 17h Model for more details.
> > >
> > > Signed-off-by: Stanislav Lanci <p...@polepetko.eu>
> > > Signed-off-by: Babu Moger <babu.mo...@amd.com>
> > 
> > The new CPUID leaves don't seem to match the existing AMD cache
> > information
> > leaves.  Is this intentional?  Why?
> 
> It is not intentional. These values are from older family of processors. 
> These values have changed from Family 14  or later.
> The latest one is Family 17. You can see the differences here.
>  https://support.amd.com/TechDocs/41131.pdf
> https://support.amd.com/TechDocs/55072_AMD_Family_15h_Models_70h-7Fh_BKDG.pdf
> https://support.amd.com/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf
> 
> Some of these are bugs in our code. For some we need to add checks for the 
> family and correct these values.
> You understand the code much better than me. Correct me if I missed 
> something. 
> 
> Note that older family of processors don't support topology extensions.  

If you want to make the cache size/topology look different
depending on the CPU model/options, this would require more work,
but it would be an interesting feature.

The "i386: Helpers to encode cache information consistently"
patch I sent last week might be a useful starting point for that.

If you plan to implement that, please keep in mind that existing
CPUID cache info needs to be kept on previous machine-types (this
is implemented by adding QOM properties that can be used to
enable the old behavior, and by setting them at
MachineClass::compat_props).

-- 
Eduardo

Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD Processor Cache Information

2018-03-20 Thread Moger, Babu 
Hi Eduardo, Thanks for the comments. Please see the response inline.

> -Original Message-
> From: Eduardo Habkost <ehabk...@redhat.com>
> Sent: Friday, March 16, 2018 1:00 PM
> To: Moger, Babu <babu.mo...@amd.com>
> Cc: pbonz...@redhat.com; r...@twiddle.net; rkrc...@redhat.com;
> Lendacky, Thomas <thomas.lenda...@amd.com>; Singh, Brijesh
> <brijesh.si...@amd.com>; k...@vger.kernel.org; k...@tripleback.net;
> mtosa...@redhat.com; Hook, Gary <gary.h...@amd.com>; qemu-
> de...@nongnu.org
> Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> Processor Cache Information
> 
> On Mon, Mar 12, 2018 at 05:00:46PM -0400, Babu Moger wrote:
> > From: Stanislav Lanci <p...@polepetko.eu>
> >
> > Add information for cpuid 0x801D leaf. Populate cache topology
> information
> > for different cache types(Data Cache, Instruction Cache, L2 and L3)
> supported
> > by 0x801D leaf. Please refer Processor Programming Reference (PPR)
> for AMD
> > Family 17h Model for more details.
> >
> > Signed-off-by: Stanislav Lanci <p...@polepetko.eu>
> > Signed-off-by: Babu Moger <babu.mo...@amd.com>
> 
> The new CPUID leaves don't seem to match the existing AMD cache
> information
> leaves.  Is this intentional?  Why?

It is not intentional. These values are from older family of processors. These 
values have changed from Family 14  or later.
The latest one is Family 17. You can see the differences here.
 https://support.amd.com/TechDocs/41131.pdf
https://support.amd.com/TechDocs/55072_AMD_Family_15h_Models_70h-7Fh_BKDG.pdf
https://support.amd.com/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf

Some of these are bugs in our code. For some we need to add checks for the 
family and correct these values.
You understand the code much better than me. Correct me if I missed something. 

Note that older family of processors don't support topology extensions.  

> 
> Details below:
> 
> > ---
> >  target/i386/cpu.c | 65
> +++
> >  target/i386/kvm.c | 29 ++---
> >  2 files changed, 91 insertions(+), 3 deletions(-)
> >
> > diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> > index 42dd381..5fdbedd 100644
> > --- a/target/i386/cpu.c
> > +++ b/target/i386/cpu.c
> [...]
> > @@ -3590,6 +3594,67 @@ void cpu_x86_cpuid(CPUX86State *env,
> uint32_t index, uint32_t count,
> >  *edx = 0;
> >  }
> >  break;
> > +case 0x801D: /* AMD TOPOEXT cache info */
> > +switch (count) {
> 
> Copying macro definitions here, for reference:
> 
> > /* L1 data cache: */
> > #define L1D_LINE_SIZE 64
> > #define L1D_ASSOCIATIVITY  8
> > #define L1D_SETS  64
> > #define L1D_PARTITIONS 1
> > /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
> > #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
> > /*FIXME: CPUID leaf 0x8005 is inconsistent with leaves 2 & 4 */
> > #define L1D_LINES_PER_TAG  1
> > #define L1D_SIZE_KB_AMD   64
> > #define L1D_ASSOCIATIVITY_AMD  2
> 
> So, we already have:
> 
> CPUID[2]: 32KB 8-way cache, 64-byte lines
> CPUID[4]: 8-way cache, 64-byte lines, 64 sets, 1 partition (32 KB)
> CPUID[0x8005]: 64 KB 2-way cache, 1 line per tag

64 KiB, 2-way are for the older family products. 
Newer one should be 8-way, 32KiB. Will need to add checks here.

> 
> 
> > +case 0: /* L1 dcache info */
> > +*eax |= TYPE_DCACHE | \
> > +CACHE_LEVEL(1) | \
> > +CACHE_SELF_INIT_LEVEL | \
> > +((cs->nr_threads - 1) << 14);
> > +*ebx = (L1D_LINE_SIZE - 1) | \
> > +   ((L1D_PARTITIONS - 1) << 12) | \
> > +   ((L1D_ASSOCIATIVITY - 1) << 22);
> > +*ecx = L1D_SETS - 1;
> > +*edx = 0;
> > +break;
> 
> This adds:
> CPUID[0x801D]: 8-way cache, 64-byte lines, 64 sets, 1 partition (32 KiB)

Should match after the above new check.

> 
> This agrees with CPUID[2] and CPUID[4] (Intel leaves, reserved on AMD), but
> not
> with CPUID[0x8005].
> 
> >
> >  /* L1 instruction cache: */
> >  #define L1I_LINE_SIZE 64
> >  #define L1I_ASSOCIATIVITY  8
> >  #define L1I_SETS  64
> > +#define L1I_SETS_AMD 256
> >  #define L1I_PARTITIONS 1
> >  /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
> >  #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_6

Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD Processor Cache Information

2018-03-16 Thread Eduardo Habkost 
On Mon, Mar 12, 2018 at 05:00:46PM -0400, Babu Moger wrote:
> From: Stanislav Lanci 
> 
> Add information for cpuid 0x801D leaf. Populate cache topology information
> for different cache types(Data Cache, Instruction Cache, L2 and L3) supported
> by 0x801D leaf. Please refer Processor Programming Reference (PPR) for AMD
> Family 17h Model for more details.
> 
> Signed-off-by: Stanislav Lanci 
> Signed-off-by: Babu Moger 

The new CPUID leaves don't seem to match the existing AMD cache information
leaves.  Is this intentional?  Why?

Details below:

> ---
>  target/i386/cpu.c | 65 
> +++
>  target/i386/kvm.c | 29 ++---
>  2 files changed, 91 insertions(+), 3 deletions(-)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 42dd381..5fdbedd 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
[...]
> @@ -3590,6 +3594,67 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, 
> uint32_t count,
>  *edx = 0;
>  }
>  break;
> +case 0x801D: /* AMD TOPOEXT cache info */
> +switch (count) {

Copying macro definitions here, for reference:

> /* L1 data cache: */
> #define L1D_LINE_SIZE 64
> #define L1D_ASSOCIATIVITY  8
> #define L1D_SETS  64
> #define L1D_PARTITIONS 1
> /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
> #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
> /*FIXME: CPUID leaf 0x8005 is inconsistent with leaves 2 & 4 */
> #define L1D_LINES_PER_TAG  1
> #define L1D_SIZE_KB_AMD   64
> #define L1D_ASSOCIATIVITY_AMD  2

So, we already have:

CPUID[2]: 32KB 8-way cache, 64-byte lines
CPUID[4]: 8-way cache, 64-byte lines, 64 sets, 1 partition (32 KB)
CPUID[0x8005]: 64 KB 2-way cache, 1 line per tag


> +case 0: /* L1 dcache info */
> +*eax |= TYPE_DCACHE | \
> +CACHE_LEVEL(1) | \
> +CACHE_SELF_INIT_LEVEL | \
> +((cs->nr_threads - 1) << 14);
> +*ebx = (L1D_LINE_SIZE - 1) | \
> +   ((L1D_PARTITIONS - 1) << 12) | \
> +   ((L1D_ASSOCIATIVITY - 1) << 22);
> +*ecx = L1D_SETS - 1;
> +*edx = 0;
> +break;

This adds:
CPUID[0x801D]: 8-way cache, 64-byte lines, 64 sets, 1 partition (32 KiB)

This agrees with CPUID[2] and CPUID[4] (Intel leaves, reserved on AMD), but not
with CPUID[0x8005].

>  
>  /* L1 instruction cache: */
>  #define L1I_LINE_SIZE 64
>  #define L1I_ASSOCIATIVITY  8
>  #define L1I_SETS  64
> +#define L1I_SETS_AMD 256
>  #define L1I_PARTITIONS 1
>  /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
>  #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
>  /*FIXME: CPUID leaf 0x8005 is inconsistent with leaves 2 & 4 */
>  #define L1I_LINES_PER_TAG  1
>  #define L1I_SIZE_KB_AMD   64
>  #define L1I_ASSOCIATIVITY_AMD  2

Currently we have:

CPUID[2]: 32KiB 8-way cache, 64-byte lines
CPUID[4]: 8-way cache, 64-byte lines, 64 sets, 1 partition (32 KiB)
CPUID[0x8005]: 64 KiB 2-way cache, 1 line per tag


>  
> +case 1: /* L1 icache info */
> +*eax |= TYPE_ICACHE | \
> +CACHE_LEVEL(1) | \
> +CACHE_SELF_INIT_LEVEL | \
> +((cs->nr_threads - 1) << 14);
> +*ebx = (L1I_LINE_SIZE - 1) | \
> +   ((L1I_PARTITIONS - 1) << 12) | \
> +   ((L1I_ASSOCIATIVITY_AMD - 1) << 22);
> +*ecx = L1I_SETS_AMD - 1;
> +*edx = 0;
> +break;

This adds:
CPUID[0x801D]: 2-way cache, 64-byte lines, 256 sets, 1 partition (32 KiB)

This doesn't match any of the existing leaves.


>  /* Level 2 unified cache: */
>  #define L2_LINE_SIZE  64
>  #define L2_ASSOCIATIVITY  16
> +#define L2_ASSOCIATIVITY_AMD   8
>  #define L2_SETS 4096
> +#define L2_SETS_AMD 1024
>  #define L2_PARTITIONS  1
>  /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
>  /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
>  #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
>  /*FIXME: CPUID leaf 0x8006 is inconsistent with leaves 2 & 4 */
>  #define L2_LINES_PER_TAG   1
>  #define L2_SIZE_KB_AMD   512

Currently we have:
CPUID[2]: 4MiB 8-way cache, 64-byte lines
CPUID[4]: 64-byte lines, 16-way, 1 partition, 4096 sets (4 MiB)
CPUID[0x8006]: 512 KiB, 16-way cache, 1 line per tag

>  
> +case 2: /* L2 cache info */
> +*eax |= TYPE_UNIFIED | \
> +CACHE_LEVEL(2) | \
> +CACHE_SELF_INIT_LEVEL | \
> +((cs->nr_threads - 1) << 14);
> +*ebx = (L2_LINE_SIZE - 1) | \
> +   ((L2_PARTITIONS - 1) << 12) | \
> +   ((L2_ASSOCIATIVITY_AMD - 1) << 22);

Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD Processor Cache Information

2018-03-15 Thread Eduardo Habkost 
Hi,

Sorry for not reviewing the previous versions of this series (and
making it miss soft freeze).


On Mon, Mar 12, 2018 at 05:00:46PM -0400, Babu Moger wrote:
> From: Stanislav Lanci 
> 
> Add information for cpuid 0x801D leaf. Populate cache topology information
> for different cache types(Data Cache, Instruction Cache, L2 and L3) supported
> by 0x801D leaf. Please refer Processor Programming Reference (PPR) for AMD
> Family 17h Model for more details.
> 
> Signed-off-by: Stanislav Lanci 
> Signed-off-by: Babu Moger 
> ---
>  target/i386/cpu.c | 65 
> +++
>  target/i386/kvm.c | 29 ++---
>  2 files changed, 91 insertions(+), 3 deletions(-)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 42dd381..5fdbedd 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -118,6 +118,7 @@
>  #define L1I_LINE_SIZE 64
>  #define L1I_ASSOCIATIVITY  8
>  #define L1I_SETS  64
> +#define L1I_SETS_AMD 256
>  #define L1I_PARTITIONS 1
>  /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
>  #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
> @@ -129,7 +130,9 @@
>  /* Level 2 unified cache: */
>  #define L2_LINE_SIZE  64
>  #define L2_ASSOCIATIVITY  16
> +#define L2_ASSOCIATIVITY_AMD   8
>  #define L2_SETS 4096
> +#define L2_SETS_AMD 1024
>  #define L2_PARTITIONS  1
>  /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
>  /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
> @@ -146,6 +149,7 @@
>  #define L3_N_LINE_SIZE 64
>  #define L3_N_ASSOCIATIVITY 16
>  #define L3_N_SETS   16384
> +#define L3_N_SETS_AMD8192
>  #define L3_N_PARTITIONS 1
>  #define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B
>  #define L3_N_LINES_PER_TAG  1

I wouldn't like to add even more inconsistencies between
different CPUID leaves.

If you really wish to have different defaults on AMD and Intel,
let's either hide Intel-specific CPUID leaves when using AMD
values, or make all of them agree (and choose the defaults based
on CPU model or vendor id).

-- 
Eduardo