Re: [Qemu-devel] [PATCH v5 10/14] pci: Add support for Designware IP block

2018-02-08 Thread Michael S. Tsirkin 
On Thu, Feb 08, 2018 at 12:43:03PM -0800, Andrey Smirnov wrote:
> On Thu, Feb 8, 2018 at 12:33 PM, Michael S. Tsirkin  wrote:
> > On Thu, Feb 08, 2018 at 12:22:53PM -0800, Andrey Smirnov wrote:
> >> On Thu, Feb 8, 2018 at 12:11 PM, Michael S. Tsirkin  
> >> wrote:
> >> > On Thu, Feb 08, 2018 at 12:03:04PM -0800, Andrey Smirnov wrote:
> >> >> >> +#define PCIE_PORT_LINK_CONTROL  0x710
> >> >> >> +
> >> >> >> +#define PCIE_PHY_DEBUG_R1   0x72C
> >> >> >> +#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP  BIT(4)
> >> >> >> +
> >> >> >> +#define PCIE_LINK_WIDTH_SPEED_CONTROL   0x80C
> >> >> >> +#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
> >> >> >> +
> >> >> >> +#define PCIE_MSI_ADDR_LO0x820
> >> >> >> +#define PCIE_MSI_ADDR_HI0x824
> >> >> >> +#define PCIE_MSI_INTR0_ENABLE   0x828
> >> >> >> +#define PCIE_MSI_INTR0_MASK 0x82C
> >> >> >> +#define PCIE_MSI_INTR0_STATUS   0x830
> >> >> >> +
> >> >> >> +#define PCIE_ATU_VIEWPORT   0x900
> >> >> >> +#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
> >> >> >> +#define PCIE_ATU_REGION_OUTBOUND(0x0 << 31)
> >> >> >> +#define PCIE_ATU_REGION_INDEX2  (0x2 << 0)
> >> >> >> +#define PCIE_ATU_REGION_INDEX1  (0x1 << 0)
> >> >> >> +#define PCIE_ATU_REGION_INDEX0  (0x0 << 0)
> >> >> >> +#define PCIE_ATU_CR10x904
> >> >> >> +#define PCIE_ATU_TYPE_MEM   (0x0 << 0)
> >> >> >> +#define PCIE_ATU_TYPE_IO(0x2 << 0)
> >> >> >> +#define PCIE_ATU_TYPE_CFG0  (0x4 << 0)
> >> >> >> +#define PCIE_ATU_TYPE_CFG1  (0x5 << 0)
> >> >> >> +#define PCIE_ATU_CR20x908
> >> >> >> +#define PCIE_ATU_ENABLE (0x1 << 31)
> >> >> >> +#define PCIE_ATU_BAR_MODE_ENABLE(0x1 << 30)
> >> >> >> +#define PCIE_ATU_LOWER_BASE 0x90C
> >> >> >> +#define PCIE_ATU_UPPER_BASE 0x910
> >> >> >> +#define PCIE_ATU_LIMIT  0x914
> >> >> >> +#define PCIE_ATU_LOWER_TARGET   0x918
> >> >> >> +#define PCIE_ATU_BUS(x) (((x) >> 24) & 0xff)
> >> >> >> +#define PCIE_ATU_DEVFN(x)   (((x) >> 16) & 0xff)
> >> >> >> +#define PCIE_ATU_UPPER_TARGET   0x91C
> >> >
> >> > Can you avoid a PCIE prefix for this btw?
> >> >
> >>
> >> That's how those constants were named in Linux kernel, but yeah, I'll
> >> add a prefix to them.
> >>
> >> Thanks,
> >> Andrey Smirnov
> >
> > In that case you should not copy it into your file.
> > Stuff from linux kernel should be imported into standard-headers.
> >
> 
> Just to be sure we are on the same page, this is the file I am talking about:
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/dwc/pcie-designware.h?h=v4.15
> 
> you want me to put it in standard-headers/linux and get those
> constants from there?
> 
> Thanks,
> Andrey Smirnov

Oh it's from a source file. I see. standard-headers/linux is for
files exported from include/uapi.

I take it back then but pls rename appropriately - and I guess
you should only copy what you actually use.

-- 
MST

Re: [Qemu-devel] [PATCH v5 10/14] pci: Add support for Designware IP block

2018-02-08 Thread Andrey Smirnov 
On Thu, Feb 8, 2018 at 12:33 PM, Michael S. Tsirkin  wrote:
> On Thu, Feb 08, 2018 at 12:22:53PM -0800, Andrey Smirnov wrote:
>> On Thu, Feb 8, 2018 at 12:11 PM, Michael S. Tsirkin  wrote:
>> > On Thu, Feb 08, 2018 at 12:03:04PM -0800, Andrey Smirnov wrote:
>> >> >> +#define PCIE_PORT_LINK_CONTROL  0x710
>> >> >> +
>> >> >> +#define PCIE_PHY_DEBUG_R1   0x72C
>> >> >> +#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP  BIT(4)
>> >> >> +
>> >> >> +#define PCIE_LINK_WIDTH_SPEED_CONTROL   0x80C
>> >> >> +#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
>> >> >> +
>> >> >> +#define PCIE_MSI_ADDR_LO0x820
>> >> >> +#define PCIE_MSI_ADDR_HI0x824
>> >> >> +#define PCIE_MSI_INTR0_ENABLE   0x828
>> >> >> +#define PCIE_MSI_INTR0_MASK 0x82C
>> >> >> +#define PCIE_MSI_INTR0_STATUS   0x830
>> >> >> +
>> >> >> +#define PCIE_ATU_VIEWPORT   0x900
>> >> >> +#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
>> >> >> +#define PCIE_ATU_REGION_OUTBOUND(0x0 << 31)
>> >> >> +#define PCIE_ATU_REGION_INDEX2  (0x2 << 0)
>> >> >> +#define PCIE_ATU_REGION_INDEX1  (0x1 << 0)
>> >> >> +#define PCIE_ATU_REGION_INDEX0  (0x0 << 0)
>> >> >> +#define PCIE_ATU_CR10x904
>> >> >> +#define PCIE_ATU_TYPE_MEM   (0x0 << 0)
>> >> >> +#define PCIE_ATU_TYPE_IO(0x2 << 0)
>> >> >> +#define PCIE_ATU_TYPE_CFG0  (0x4 << 0)
>> >> >> +#define PCIE_ATU_TYPE_CFG1  (0x5 << 0)
>> >> >> +#define PCIE_ATU_CR20x908
>> >> >> +#define PCIE_ATU_ENABLE (0x1 << 31)
>> >> >> +#define PCIE_ATU_BAR_MODE_ENABLE(0x1 << 30)
>> >> >> +#define PCIE_ATU_LOWER_BASE 0x90C
>> >> >> +#define PCIE_ATU_UPPER_BASE 0x910
>> >> >> +#define PCIE_ATU_LIMIT  0x914
>> >> >> +#define PCIE_ATU_LOWER_TARGET   0x918
>> >> >> +#define PCIE_ATU_BUS(x) (((x) >> 24) & 0xff)
>> >> >> +#define PCIE_ATU_DEVFN(x)   (((x) >> 16) & 0xff)
>> >> >> +#define PCIE_ATU_UPPER_TARGET   0x91C
>> >
>> > Can you avoid a PCIE prefix for this btw?
>> >
>>
>> That's how those constants were named in Linux kernel, but yeah, I'll
>> add a prefix to them.
>>
>> Thanks,
>> Andrey Smirnov
>
> In that case you should not copy it into your file.
> Stuff from linux kernel should be imported into standard-headers.
>

Just to be sure we are on the same page, this is the file I am talking about:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/dwc/pcie-designware.h?h=v4.15

you want me to put it in standard-headers/linux and get those
constants from there?

Thanks,
Andrey Smirnov

Re: [Qemu-devel] [PATCH v5 10/14] pci: Add support for Designware IP block

2018-02-08 Thread Michael S. Tsirkin 
On Thu, Feb 08, 2018 at 12:22:53PM -0800, Andrey Smirnov wrote:
> On Thu, Feb 8, 2018 at 12:11 PM, Michael S. Tsirkin  wrote:
> > On Thu, Feb 08, 2018 at 12:03:04PM -0800, Andrey Smirnov wrote:
> >> >> +#define PCIE_PORT_LINK_CONTROL  0x710
> >> >> +
> >> >> +#define PCIE_PHY_DEBUG_R1   0x72C
> >> >> +#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP  BIT(4)
> >> >> +
> >> >> +#define PCIE_LINK_WIDTH_SPEED_CONTROL   0x80C
> >> >> +#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
> >> >> +
> >> >> +#define PCIE_MSI_ADDR_LO0x820
> >> >> +#define PCIE_MSI_ADDR_HI0x824
> >> >> +#define PCIE_MSI_INTR0_ENABLE   0x828
> >> >> +#define PCIE_MSI_INTR0_MASK 0x82C
> >> >> +#define PCIE_MSI_INTR0_STATUS   0x830
> >> >> +
> >> >> +#define PCIE_ATU_VIEWPORT   0x900
> >> >> +#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
> >> >> +#define PCIE_ATU_REGION_OUTBOUND(0x0 << 31)
> >> >> +#define PCIE_ATU_REGION_INDEX2  (0x2 << 0)
> >> >> +#define PCIE_ATU_REGION_INDEX1  (0x1 << 0)
> >> >> +#define PCIE_ATU_REGION_INDEX0  (0x0 << 0)
> >> >> +#define PCIE_ATU_CR10x904
> >> >> +#define PCIE_ATU_TYPE_MEM   (0x0 << 0)
> >> >> +#define PCIE_ATU_TYPE_IO(0x2 << 0)
> >> >> +#define PCIE_ATU_TYPE_CFG0  (0x4 << 0)
> >> >> +#define PCIE_ATU_TYPE_CFG1  (0x5 << 0)
> >> >> +#define PCIE_ATU_CR20x908
> >> >> +#define PCIE_ATU_ENABLE (0x1 << 31)
> >> >> +#define PCIE_ATU_BAR_MODE_ENABLE(0x1 << 30)
> >> >> +#define PCIE_ATU_LOWER_BASE 0x90C
> >> >> +#define PCIE_ATU_UPPER_BASE 0x910
> >> >> +#define PCIE_ATU_LIMIT  0x914
> >> >> +#define PCIE_ATU_LOWER_TARGET   0x918
> >> >> +#define PCIE_ATU_BUS(x) (((x) >> 24) & 0xff)
> >> >> +#define PCIE_ATU_DEVFN(x)   (((x) >> 16) & 0xff)
> >> >> +#define PCIE_ATU_UPPER_TARGET   0x91C
> >
> > Can you avoid a PCIE prefix for this btw?
> >
> 
> That's how those constants were named in Linux kernel, but yeah, I'll
> add a prefix to them.
> 
> Thanks,
> Andrey Smirnov

In that case you should not copy it into your file.
Stuff from linux kernel should be imported into standard-headers.


-- 
MST

Re: [Qemu-devel] [PATCH v5 10/14] pci: Add support for Designware IP block

2018-02-08 Thread Michael S. Tsirkin 
On Thu, Feb 08, 2018 at 12:03:04PM -0800, Andrey Smirnov wrote:
> >> +#define PCIE_PORT_LINK_CONTROL  0x710
> >> +
> >> +#define PCIE_PHY_DEBUG_R1   0x72C
> >> +#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP  BIT(4)
> >> +
> >> +#define PCIE_LINK_WIDTH_SPEED_CONTROL   0x80C
> >> +#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
> >> +
> >> +#define PCIE_MSI_ADDR_LO0x820
> >> +#define PCIE_MSI_ADDR_HI0x824
> >> +#define PCIE_MSI_INTR0_ENABLE   0x828
> >> +#define PCIE_MSI_INTR0_MASK 0x82C
> >> +#define PCIE_MSI_INTR0_STATUS   0x830
> >> +
> >> +#define PCIE_ATU_VIEWPORT   0x900
> >> +#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
> >> +#define PCIE_ATU_REGION_OUTBOUND(0x0 << 31)
> >> +#define PCIE_ATU_REGION_INDEX2  (0x2 << 0)
> >> +#define PCIE_ATU_REGION_INDEX1  (0x1 << 0)
> >> +#define PCIE_ATU_REGION_INDEX0  (0x0 << 0)
> >> +#define PCIE_ATU_CR10x904
> >> +#define PCIE_ATU_TYPE_MEM   (0x0 << 0)
> >> +#define PCIE_ATU_TYPE_IO(0x2 << 0)
> >> +#define PCIE_ATU_TYPE_CFG0  (0x4 << 0)
> >> +#define PCIE_ATU_TYPE_CFG1  (0x5 << 0)
> >> +#define PCIE_ATU_CR20x908
> >> +#define PCIE_ATU_ENABLE (0x1 << 31)
> >> +#define PCIE_ATU_BAR_MODE_ENABLE(0x1 << 30)
> >> +#define PCIE_ATU_LOWER_BASE 0x90C
> >> +#define PCIE_ATU_UPPER_BASE 0x910
> >> +#define PCIE_ATU_LIMIT  0x914
> >> +#define PCIE_ATU_LOWER_TARGET   0x918
> >> +#define PCIE_ATU_BUS(x) (((x) >> 24) & 0xff)
> >> +#define PCIE_ATU_DEVFN(x)   (((x) >> 16) & 0xff)
> >> +#define PCIE_ATU_UPPER_TARGET   0x91C

Can you avoid a PCIE prefix for this btw?

Thaks!

Re: [Qemu-devel] [PATCH v5 10/14] pci: Add support for Designware IP block

2018-02-08 Thread Andrey Smirnov 
On Thu, Feb 8, 2018 at 12:11 PM, Michael S. Tsirkin  wrote:
> On Thu, Feb 08, 2018 at 12:03:04PM -0800, Andrey Smirnov wrote:
>> >> +#define PCIE_PORT_LINK_CONTROL  0x710
>> >> +
>> >> +#define PCIE_PHY_DEBUG_R1   0x72C
>> >> +#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP  BIT(4)
>> >> +
>> >> +#define PCIE_LINK_WIDTH_SPEED_CONTROL   0x80C
>> >> +#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
>> >> +
>> >> +#define PCIE_MSI_ADDR_LO0x820
>> >> +#define PCIE_MSI_ADDR_HI0x824
>> >> +#define PCIE_MSI_INTR0_ENABLE   0x828
>> >> +#define PCIE_MSI_INTR0_MASK 0x82C
>> >> +#define PCIE_MSI_INTR0_STATUS   0x830
>> >> +
>> >> +#define PCIE_ATU_VIEWPORT   0x900
>> >> +#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
>> >> +#define PCIE_ATU_REGION_OUTBOUND(0x0 << 31)
>> >> +#define PCIE_ATU_REGION_INDEX2  (0x2 << 0)
>> >> +#define PCIE_ATU_REGION_INDEX1  (0x1 << 0)
>> >> +#define PCIE_ATU_REGION_INDEX0  (0x0 << 0)
>> >> +#define PCIE_ATU_CR10x904
>> >> +#define PCIE_ATU_TYPE_MEM   (0x0 << 0)
>> >> +#define PCIE_ATU_TYPE_IO(0x2 << 0)
>> >> +#define PCIE_ATU_TYPE_CFG0  (0x4 << 0)
>> >> +#define PCIE_ATU_TYPE_CFG1  (0x5 << 0)
>> >> +#define PCIE_ATU_CR20x908
>> >> +#define PCIE_ATU_ENABLE (0x1 << 31)
>> >> +#define PCIE_ATU_BAR_MODE_ENABLE(0x1 << 30)
>> >> +#define PCIE_ATU_LOWER_BASE 0x90C
>> >> +#define PCIE_ATU_UPPER_BASE 0x910
>> >> +#define PCIE_ATU_LIMIT  0x914
>> >> +#define PCIE_ATU_LOWER_TARGET   0x918
>> >> +#define PCIE_ATU_BUS(x) (((x) >> 24) & 0xff)
>> >> +#define PCIE_ATU_DEVFN(x)   (((x) >> 16) & 0xff)
>> >> +#define PCIE_ATU_UPPER_TARGET   0x91C
>
> Can you avoid a PCIE prefix for this btw?
>

That's how those constants were named in Linux kernel, but yeah, I'll
add a prefix to them.

Thanks,
Andrey Smirnov

Re: [Qemu-devel] [PATCH v5 10/14] pci: Add support for Designware IP block

2018-02-08 Thread Andrey Smirnov 
On Thu, Feb 8, 2018 at 9:45 AM, Michael S. Tsirkin  wrote:
> On Tue, Feb 06, 2018 at 08:24:34PM -0800, Andrey Smirnov wrote:
>> Add code needed to get a functional PCI subsytem when using in
>> conjunction with upstream Linux guest (4.13+). Tested to work against
>> "e1000e" (network adapter, using MSI interrupts) as well as
>> "usb-ehci" (USB controller, using legacy PCI interrupts).
>>
>> Based on "i.MX6 Applications Processor Reference Manual" (Document
>> Number: IMX6DQRM Rev. 4) as well as corresponding dirver in Linux
>> kernel (circa 4.13 - 4.16 found in drivers/pci/dwc/*)
>>
>> Cc: Peter Maydell 
>> Cc: Jason Wang 
>> Cc: Philippe Mathieu-Daudé 
>> Cc: Marcel Apfelbaum 
>> Cc: Michael S. Tsirkin 
>> Cc: qemu-devel@nongnu.org
>> Cc: qemu-...@nongnu.org
>> Cc: yurov...@gmail.com
>> Signed-off-by: Andrey Smirnov 
>> ---
>>  default-configs/arm-softmmu.mak  |   2 +
>>  hw/pci-host/Makefile.objs|   2 +
>>  hw/pci-host/designware.c | 759 
>> +++
>>  include/hw/pci-host/designware.h |  97 +
>>  include/hw/pci/pci_ids.h |   2 +
>>  5 files changed, 862 insertions(+)
>>  create mode 100644 hw/pci-host/designware.c
>>  create mode 100644 include/hw/pci-host/designware.h
>>
>> diff --git a/default-configs/arm-softmmu.mak 
>> b/default-configs/arm-softmmu.mak
>> index b0d6e65038..0c5ae914ed 100644
>> --- a/default-configs/arm-softmmu.mak
>> +++ b/default-configs/arm-softmmu.mak
>> @@ -132,3 +132,5 @@ CONFIG_GPIO_KEY=y
>>  CONFIG_MSF2=y
>>  CONFIG_FW_CFG_DMA=y
>>  CONFIG_XILINX_AXI=y
>> +CONFIG_PCI_DESIGNWARE=y
>> +
>> diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs
>> index 4b69f737b5..6d6597c065 100644
>> --- a/hw/pci-host/Makefile.objs
>> +++ b/hw/pci-host/Makefile.objs
>> @@ -17,3 +17,5 @@ common-obj-$(CONFIG_PCI_PIIX) += piix.o
>>  common-obj-$(CONFIG_PCI_Q35) += q35.o
>>  common-obj-$(CONFIG_PCI_GENERIC) += gpex.o
>>  common-obj-$(CONFIG_PCI_XILINX) += xilinx-pcie.o
>> +
>> +common-obj-$(CONFIG_PCI_DESIGNWARE) += designware.o
>> diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
>> new file mode 100644
>> index 00..551a881af0
>> --- /dev/null
>> +++ b/hw/pci-host/designware.c
>> @@ -0,0 +1,759 @@
>> +/*
>> + * Copyright (c) 2018, Impinj, Inc.
>> + *
>> + * Designware PCIe IP block emulation
>> + *
>> + * This library is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU Lesser General Public
>> + * License as published by the Free Software Foundation; either
>> + * version 2 of the License, or (at your option) any later version.
>> + *
>> + * This library is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
>> + * Lesser General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU Lesser General Public
>> + * License along with this library; if not, see
>> + * .
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "qapi/error.h"
>> +#include "hw/pci/msi.h"
>> +#include "hw/pci/pci_bridge.h"
>> +#include "hw/pci/pci_host.h"
>> +#include "hw/pci/pcie_port.h"
>> +#include "hw/pci-host/designware.h"
>> +
>> +#define PCIE_PORT_LINK_CONTROL  0x710
>> +
>> +#define PCIE_PHY_DEBUG_R1   0x72C
>> +#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP  BIT(4)
>> +
>> +#define PCIE_LINK_WIDTH_SPEED_CONTROL   0x80C
>> +#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
>> +
>> +#define PCIE_MSI_ADDR_LO0x820
>> +#define PCIE_MSI_ADDR_HI0x824
>> +#define PCIE_MSI_INTR0_ENABLE   0x828
>> +#define PCIE_MSI_INTR0_MASK 0x82C
>> +#define PCIE_MSI_INTR0_STATUS   0x830
>> +
>> +#define PCIE_ATU_VIEWPORT   0x900
>> +#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
>> +#define PCIE_ATU_REGION_OUTBOUND(0x0 << 31)
>> +#define PCIE_ATU_REGION_INDEX2  (0x2 << 0)
>> +#define PCIE_ATU_REGION_INDEX1  (0x1 << 0)
>> +#define PCIE_ATU_REGION_INDEX0  (0x0 << 0)
>> +#define PCIE_ATU_CR10x904
>> +#define PCIE_ATU_TYPE_MEM   (0x0 << 0)
>> +#define PCIE_ATU_TYPE_IO(0x2 << 0)
>> +#define PCIE_ATU_TYPE_CFG0  (0x4 << 0)
>> +#define PCIE_ATU_TYPE_CFG1  (0x5 << 0)
>> +#define PCIE_ATU_CR20x908
>> +#define PCIE_ATU_ENABLE (0x1 << 31)
>> +#define PCIE_ATU_BAR_MODE_ENABLE(0x1 << 30)
>> +#define PCIE_ATU_LOWER_BASE 0x90C
>> +#define PCIE_ATU_UPPER_BASE 0x910
>> +#define PCIE_ATU_LIMIT  0x914
>> +#define PCIE_ATU_LOWER_TARGET   0x918
>> +#define PCIE_ATU_BUS(x) (((x) >>

Re: [Qemu-devel] [PATCH v5 10/14] pci: Add support for Designware IP block

2018-02-08 Thread Michael S. Tsirkin 
On Tue, Feb 06, 2018 at 08:24:34PM -0800, Andrey Smirnov wrote:
> Add code needed to get a functional PCI subsytem when using in
> conjunction with upstream Linux guest (4.13+). Tested to work against
> "e1000e" (network adapter, using MSI interrupts) as well as
> "usb-ehci" (USB controller, using legacy PCI interrupts).
> 
> Based on "i.MX6 Applications Processor Reference Manual" (Document
> Number: IMX6DQRM Rev. 4) as well as corresponding dirver in Linux
> kernel (circa 4.13 - 4.16 found in drivers/pci/dwc/*)
> 
> Cc: Peter Maydell 
> Cc: Jason Wang 
> Cc: Philippe Mathieu-Daudé 
> Cc: Marcel Apfelbaum 
> Cc: Michael S. Tsirkin 
> Cc: qemu-devel@nongnu.org
> Cc: qemu-...@nongnu.org
> Cc: yurov...@gmail.com
> Signed-off-by: Andrey Smirnov 
> ---
>  default-configs/arm-softmmu.mak  |   2 +
>  hw/pci-host/Makefile.objs|   2 +
>  hw/pci-host/designware.c | 759 
> +++
>  include/hw/pci-host/designware.h |  97 +
>  include/hw/pci/pci_ids.h |   2 +
>  5 files changed, 862 insertions(+)
>  create mode 100644 hw/pci-host/designware.c
>  create mode 100644 include/hw/pci-host/designware.h
> 
> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
> index b0d6e65038..0c5ae914ed 100644
> --- a/default-configs/arm-softmmu.mak
> +++ b/default-configs/arm-softmmu.mak
> @@ -132,3 +132,5 @@ CONFIG_GPIO_KEY=y
>  CONFIG_MSF2=y
>  CONFIG_FW_CFG_DMA=y
>  CONFIG_XILINX_AXI=y
> +CONFIG_PCI_DESIGNWARE=y
> +
> diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs
> index 4b69f737b5..6d6597c065 100644
> --- a/hw/pci-host/Makefile.objs
> +++ b/hw/pci-host/Makefile.objs
> @@ -17,3 +17,5 @@ common-obj-$(CONFIG_PCI_PIIX) += piix.o
>  common-obj-$(CONFIG_PCI_Q35) += q35.o
>  common-obj-$(CONFIG_PCI_GENERIC) += gpex.o
>  common-obj-$(CONFIG_PCI_XILINX) += xilinx-pcie.o
> +
> +common-obj-$(CONFIG_PCI_DESIGNWARE) += designware.o
> diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
> new file mode 100644
> index 00..551a881af0
> --- /dev/null
> +++ b/hw/pci-host/designware.c
> @@ -0,0 +1,759 @@
> +/*
> + * Copyright (c) 2018, Impinj, Inc.
> + *
> + * Designware PCIe IP block emulation
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see
> + * .
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "hw/pci/msi.h"
> +#include "hw/pci/pci_bridge.h"
> +#include "hw/pci/pci_host.h"
> +#include "hw/pci/pcie_port.h"
> +#include "hw/pci-host/designware.h"
> +
> +#define PCIE_PORT_LINK_CONTROL  0x710
> +
> +#define PCIE_PHY_DEBUG_R1   0x72C
> +#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP  BIT(4)
> +
> +#define PCIE_LINK_WIDTH_SPEED_CONTROL   0x80C
> +#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
> +
> +#define PCIE_MSI_ADDR_LO0x820
> +#define PCIE_MSI_ADDR_HI0x824
> +#define PCIE_MSI_INTR0_ENABLE   0x828
> +#define PCIE_MSI_INTR0_MASK 0x82C
> +#define PCIE_MSI_INTR0_STATUS   0x830
> +
> +#define PCIE_ATU_VIEWPORT   0x900
> +#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
> +#define PCIE_ATU_REGION_OUTBOUND(0x0 << 31)
> +#define PCIE_ATU_REGION_INDEX2  (0x2 << 0)
> +#define PCIE_ATU_REGION_INDEX1  (0x1 << 0)
> +#define PCIE_ATU_REGION_INDEX0  (0x0 << 0)
> +#define PCIE_ATU_CR10x904
> +#define PCIE_ATU_TYPE_MEM   (0x0 << 0)
> +#define PCIE_ATU_TYPE_IO(0x2 << 0)
> +#define PCIE_ATU_TYPE_CFG0  (0x4 << 0)
> +#define PCIE_ATU_TYPE_CFG1  (0x5 << 0)
> +#define PCIE_ATU_CR20x908
> +#define PCIE_ATU_ENABLE (0x1 << 31)
> +#define PCIE_ATU_BAR_MODE_ENABLE(0x1 << 30)
> +#define PCIE_ATU_LOWER_BASE 0x90C
> +#define PCIE_ATU_UPPER_BASE 0x910
> +#define PCIE_ATU_LIMIT  0x914
> +#define PCIE_ATU_LOWER_TARGET   0x918
> +#define PCIE_ATU_BUS(x) (((x) >> 24) & 0xff)
> +#define PCIE_ATU_DEVFN(x)   (((x) >> 16) & 0xff)
> +#define PCIE_ATU_UPPER_TARGET   0x91C
> +
> +static DesignwarePCIEHost *
>