Re: [PATCH v5 00/11] s390x/tcg: Implement Vector-Enhancements Facility 2
I'm playing catch up a bit here, as I was out sick for a few days.
It would be very much appreciated if you could do so, as I'm not
familiar with what is required.
Thanks
- David Miller
On Mon, Apr 25, 2022 at 3:51 AM David Hildenbrand wrote:
>
> On 25.04.22 09:43, Christian Borntraeger wrote:
> > Am 23.03.22 um 14:57 schrieb David Miller:
> >> Implement Vector-Enhancements Facility 2 for s390x
> >>
> >> resolves: https://gitlab.com/qemu-project/qemu/-/issues/738
> >>
> >> implements:
> >> VECTOR LOAD ELEMENTS REVERSED (VLER)
> >> VECTOR LOAD BYTE REVERSED ELEMENTS (VLBR)
> >> VECTOR LOAD BYTE REVERSED ELEMENT (VLEBRH, VLEBRF, VLEBRG)
> >> VECTOR LOAD BYTE REVERSED ELEMENT AND ZERO (VLLEBRZ)
> >> VECTOR LOAD BYTE REVERSED ELEMENT AND REPLICATE (VLBRREP)
> >> VECTOR STORE ELEMENTS REVERSED (VSTER)
> >> VECTOR STORE BYTE REVERSED ELEMENTS (VSTBR)
> >> VECTOR STORE BYTE REVERSED ELEMENTS (VSTEBRH, VSTEBRF,
> >> VSTEBRG)
> >> VECTOR SHIFT LEFT DOUBLE BY BIT (VSLD)
> >> VECTOR SHIFT RIGHT DOUBLE BY BIT(VSRD)
> >> VECTOR STRING SEARCH(VSTRS)
> >>
> >> modifies:
> >> VECTOR FP CONVERT FROM FIXED(VCFPS)
> >> VECTOR FP CONVERT FROM LOGICAL (VCFPL)
> >> VECTOR FP CONVERT TO FIXED (VCSFP)
> >> VECTOR FP CONVERT TO LOGICAL (VCLFP)
> >> VECTOR SHIFT LEFT (VSL)
> >> VECTOR SHIFT RIGHT ARITHMETIC (VSRA)
> >> VECTOR SHIFT RIGHT LOGICAL (VSRL)
> >>
> >>
> >> David Miller (9):
> >>tcg: Implement tcg_gen_{h,w}swap_{i32,i64}
> >>target/s390x: vxeh2: vector convert short/32b
> >>target/s390x: vxeh2: vector string search
> >>target/s390x: vxeh2: Update for changes to vector shifts
> >>target/s390x: vxeh2: vector shift double by bit
> >>target/s390x: vxeh2: vector {load, store} elements reversed
> >>target/s390x: vxeh2: vector {load, store} byte reversed elements
> >>target/s390x: vxeh2: vector {load, store} byte reversed element
> >>target/s390x: add S390_FEAT_VECTOR_ENH2 to qemu CPU model
> >>tests/tcg/s390x: Tests for Vector Enhancements Facility 2
> >>target/s390x: Fix writeback to v1 in helper_vstl
> >>
> >> Richard Henderson (2):
> >>tcg: Implement tcg_gen_{h,w}swap_{i32,i64}
> >>target/s390x: Fix writeback to v1 in helper_vstl
> >
> >
> > I guess we can now re-do this series against 7.1-devel (qemu/master) which
> > does
> > have the machine compat changes. Apart from that this should be ready now?
> >
>
> Yes, I think so. I can respin with the proper compat changes if requested.
>
> --
> Thanks,
>
> David / dhildenb
>
Re: [PATCH v6 00/13] s390x/tcg: Implement Vector-Enhancements Facility 2
There was also the patch that had them as .insn in the other series of emails. On Mon, May 2, 2022 at 11:52 AM David Hildenbrand wrote: > > On 02.05.22 09:20, Thomas Huth wrote: > > On 28/04/2022 11.46, David Hildenbrand wrote: > >> Implement Vector-Enhancements Facility 2 for s390x > >> > >> resolves: https://gitlab.com/qemu-project/qemu/-/issues/738 > >> > >> implements: > >> VECTOR LOAD ELEMENTS REVERSED (VLER) > >> VECTOR LOAD BYTE REVERSED ELEMENTS (VLBR) > >> VECTOR LOAD BYTE REVERSED ELEMENT (VLEBRH, VLEBRF, VLEBRG) > >> VECTOR LOAD BYTE REVERSED ELEMENT AND ZERO (VLLEBRZ) > >> VECTOR LOAD BYTE REVERSED ELEMENT AND REPLICATE (VLBRREP) > >> VECTOR STORE ELEMENTS REVERSED (VSTER) > >> VECTOR STORE BYTE REVERSED ELEMENTS (VSTBR) > >> VECTOR STORE BYTE REVERSED ELEMENTS (VSTEBRH, VSTEBRF, > >> VSTEBRG) > >> VECTOR SHIFT LEFT DOUBLE BY BIT (VSLD) > >> VECTOR SHIFT RIGHT DOUBLE BY BIT(VSRD) > >> VECTOR STRING SEARCH(VSTRS) > >> > >> modifies: > >> VECTOR FP CONVERT FROM FIXED(VCFPS) > >> VECTOR FP CONVERT FROM LOGICAL (VCFPL) > >> VECTOR FP CONVERT TO FIXED (VCSFP) > >> VECTOR FP CONVERT TO LOGICAL(VCLFP) > >> VECTOR SHIFT LEFT (VSL) > >> VECTOR SHIFT RIGHT ARITHMETIC (VSRA) > >> VECTOR SHIFT RIGHT LOGICAL (VSRL) > > > > Thanks, queued to my s390x-next branch now: > > > > https://gitlab.com/thuth/qemu/-/commits/s390x-next/ > > > Thanks for fixing up. At this point I would have suggested to exclude > the tests for now. > > -- > Thanks, > > David / dhildenb >
Re: [PATCH v6 00/13] s390x/tcg: Implement Vector-Enhancements Facility 2
Sorry, It was in the discussion for v4 patches, as an attachment .
mail thread:
[PATCH v4 10/11] tests/tcg/s390x: Tests for Vector Enhancements Facility 2
So it likely never made it to the mailing list.
I've reattached and will forward the patch (by itself) to the mailing list.
I think the other solution works just as well by ignoring if compiler
doesn't support z15.
I just thought I'd bring it back up as I saw discussion about it.
Thanks
- David Miller
On Tue, May 3, 2022 at 2:55 AM Thomas Huth wrote:
>
> Hi!
>
> On 02/05/2022 18.06, David Miller wrote:
> > There was also the patch that had them as .insn in the other series of
> > emails.
>
> Sorry, I missed that patch, could you please point me to the mail on
> https://lore.kernel.org/qemu-devel/ ? I remember that there was a discussion
> about the vri-d encoding, but I apparently missed the patch that came out of
> this discussion...
>
> Thomas
>
> > On Mon, May 2, 2022 at 11:52 AM David Hildenbrand wrote:
> >>
> >> On 02.05.22 09:20, Thomas Huth wrote:
> >>> On 28/04/2022 11.46, David Hildenbrand wrote:
> >>>> Implement Vector-Enhancements Facility 2 for s390x
> >>>>
> >>>> resolves: https://gitlab.com/qemu-project/qemu/-/issues/738
> >>>>
> >>>> implements:
> >>>> VECTOR LOAD ELEMENTS REVERSED (VLER)
> >>>> VECTOR LOAD BYTE REVERSED ELEMENTS (VLBR)
> >>>> VECTOR LOAD BYTE REVERSED ELEMENT (VLEBRH, VLEBRF,
> >>>> VLEBRG)
> >>>> VECTOR LOAD BYTE REVERSED ELEMENT AND ZERO (VLLEBRZ)
> >>>> VECTOR LOAD BYTE REVERSED ELEMENT AND REPLICATE (VLBRREP)
> >>>> VECTOR STORE ELEMENTS REVERSED (VSTER)
> >>>> VECTOR STORE BYTE REVERSED ELEMENTS (VSTBR)
> >>>> VECTOR STORE BYTE REVERSED ELEMENTS (VSTEBRH, VSTEBRF,
> >>>> VSTEBRG)
> >>>> VECTOR SHIFT LEFT DOUBLE BY BIT (VSLD)
> >>>> VECTOR SHIFT RIGHT DOUBLE BY BIT(VSRD)
> >>>> VECTOR STRING SEARCH(VSTRS)
> >>>>
> >>>> modifies:
> >>>> VECTOR FP CONVERT FROM FIXED(VCFPS)
> >>>> VECTOR FP CONVERT FROM LOGICAL (VCFPL)
> >>>> VECTOR FP CONVERT TO FIXED (VCSFP)
> >>>> VECTOR FP CONVERT TO LOGICAL(VCLFP)
> >>>> VECTOR SHIFT LEFT (VSL)
> >>>> VECTOR SHIFT RIGHT ARITHMETIC (VSRA)
> >>>> VECTOR SHIFT RIGHT LOGICAL (VSRL)
> >>>
> >>> Thanks, queued to my s390x-next branch now:
> >>>
> >>>https://gitlab.com/thuth/qemu/-/commits/s390x-next/
> >>>
> >> Thanks for fixing up. At this point I would have suggested to exclude
> >> the tests for now.
> >>
> >> --
> >> Thanks,
> >>
> >> David / dhildenb
> >>
> >
>
From bb6bf2f9529c4d76db9a9eff2ff7fa1235657103 Mon Sep 17 00:00:00 2001
From: David Miller
Date: Mon, 21 Mar 2022 16:58:57 -0400
Subject: [PATCH v5 10/11] tests/tcg/s390x: Tests for Vector Enhancements
Facility 2
Signed-off-by: David Miller
---
tests/tcg/s390x/Makefile.target | 8 ++
tests/tcg/s390x/vx.h| 19 +
tests/tcg/s390x/vxeh2_vcvt.c| 88
tests/tcg/s390x/vxeh2_vlstr.c | 139
tests/tcg/s390x/vxeh2_vs.c | 95 ++
5 files changed, 349 insertions(+)
create mode 100644 tests/tcg/s390x/vx.h
create mode 100644 tests/tcg/s390x/vxeh2_vcvt.c
create mode 100644 tests/tcg/s390x/vxeh2_vlstr.c
create mode 100644 tests/tcg/s390x/vxeh2_vs.c
diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.target
index 8c9b6a13ce..921a056dd1 100644
--- a/tests/tcg/s390x/Makefile.target
+++ b/tests/tcg/s390x/Makefile.target
@@ -16,6 +16,14 @@ TESTS+=shift
TESTS+=trap
TESTS+=signals-s390x
+VECTOR_TESTS=vxeh2_vs
+VECTOR_TESTS+=vxeh2_vcvt
+VECTOR_TESTS+=vxeh2_vlstr
+
+TESTS+=$(VECTOR_TESTS)
+
+$(VECTOR_TESTS): CFLAGS+=-march=z15 -O2
+
ifneq ($(HAVE_GDB_BIN),)
GDB_SCRIPT=$(SRC_PATH)/tests/guest-debug/run-test.py
diff --git a/tests/tcg/s390x/vx.h b/tests/tcg/s390x/vx.h
new file mode 100644
index 00..2e66f8b714
--- /dev/null
+++ b/tests/tcg/s390x/vx.h
@@ -0,0 +1,19 @@
+#ifndef QEMU_TESTS_S390X_VX_H
+#define QEMU_TESTS_S390X_VX_H
+
+typedef union S390Vector {
+uint64_t d[2]; /* doubleword */
+uint32_t w[4]; /* wo
Re: [PATCH v6 00/13] s390x/tcg: Implement Vector-Enhancements Facility 2
It looks like google killed allowing password access early, nothing makes it work anymore. They had plans to disable 'less secure app' in may, but it thought it was the end of the month. I'll try copy/paste as plain text as well though I Know it will likely screw it up.. On Tue, May 3, 2022 at 10:42 AM David Miller wrote: > > Sorry, It was in the discussion for v4 patches, as an attachment . > mail thread: > [PATCH v4 10/11] tests/tcg/s390x: Tests for Vector Enhancements Facility 2 > So it likely never made it to the mailing list. > > I've reattached and will forward the patch (by itself) to the mailing list. > > I think the other solution works just as well by ignoring if compiler > doesn't support z15. > > I just thought I'd bring it back up as I saw discussion about it. > > Thanks > - David Miller > > > > > > > On Tue, May 3, 2022 at 2:55 AM Thomas Huth wrote: > > > > Hi! > > > > On 02/05/2022 18.06, David Miller wrote: > > > There was also the patch that had them as .insn in the other series of > > > emails. > > > > Sorry, I missed that patch, could you please point me to the mail on > > https://lore.kernel.org/qemu-devel/ ? I remember that there was a discussion > > about the vri-d encoding, but I apparently missed the patch that came out of > > this discussion... > > > > Thomas > > > > > On Mon, May 2, 2022 at 11:52 AM David Hildenbrand > > > wrote: > > >> > > >> On 02.05.22 09:20, Thomas Huth wrote: > > >>> On 28/04/2022 11.46, David Hildenbrand wrote: > > >>>> Implement Vector-Enhancements Facility 2 for s390x > > >>>> > > >>>> resolves: https://gitlab.com/qemu-project/qemu/-/issues/738 > > >>>> > > >>>> implements: > > >>>> VECTOR LOAD ELEMENTS REVERSED (VLER) > > >>>> VECTOR LOAD BYTE REVERSED ELEMENTS (VLBR) > > >>>> VECTOR LOAD BYTE REVERSED ELEMENT (VLEBRH, VLEBRF, > > >>>> VLEBRG) > > >>>> VECTOR LOAD BYTE REVERSED ELEMENT AND ZERO (VLLEBRZ) > > >>>> VECTOR LOAD BYTE REVERSED ELEMENT AND REPLICATE (VLBRREP) > > >>>> VECTOR STORE ELEMENTS REVERSED (VSTER) > > >>>> VECTOR STORE BYTE REVERSED ELEMENTS (VSTBR) > > >>>> VECTOR STORE BYTE REVERSED ELEMENTS (VSTEBRH, VSTEBRF, > > >>>> VSTEBRG) > > >>>> VECTOR SHIFT LEFT DOUBLE BY BIT (VSLD) > > >>>> VECTOR SHIFT RIGHT DOUBLE BY BIT(VSRD) > > >>>> VECTOR STRING SEARCH(VSTRS) > > >>>> > > >>>> modifies: > > >>>> VECTOR FP CONVERT FROM FIXED(VCFPS) > > >>>> VECTOR FP CONVERT FROM LOGICAL (VCFPL) > > >>>> VECTOR FP CONVERT TO FIXED (VCSFP) > > >>>> VECTOR FP CONVERT TO LOGICAL(VCLFP) > > >>>> VECTOR SHIFT LEFT (VSL) > > >>>> VECTOR SHIFT RIGHT ARITHMETIC (VSRA) > > >>>> VECTOR SHIFT RIGHT LOGICAL (VSRL) > > >>> > > >>> Thanks, queued to my s390x-next branch now: > > >>> > > >>>https://gitlab.com/thuth/qemu/-/commits/s390x-next/ > > >>> > > >> Thanks for fixing up. At this point I would have suggested to exclude > > >> the tests for now. > > >> > > >> -- > > >> Thanks, > > >> > > >> David / dhildenb > > >> > > > > >
Re: [PATCH v6 00/13] s390x/tcg: Implement Vector-Enhancements Facility 2
>From bb6bf2f9529c4d76db9a9eff2ff7fa1235657103 Mon Sep 17 00:00:00 2001
From: David Miller
Date: Mon, 21 Mar 2022 16:58:57 -0400
Subject: [PATCH v5 10/11] tests/tcg/s390x: Tests for Vector Enhancements
Facility 2
Signed-off-by: David Miller
---
tests/tcg/s390x/Makefile.target | 8 ++
tests/tcg/s390x/vx.h| 19 +
tests/tcg/s390x/vxeh2_vcvt.c| 88
tests/tcg/s390x/vxeh2_vlstr.c | 139
tests/tcg/s390x/vxeh2_vs.c | 95 ++
5 files changed, 349 insertions(+)
create mode 100644 tests/tcg/s390x/vx.h
create mode 100644 tests/tcg/s390x/vxeh2_vcvt.c
create mode 100644 tests/tcg/s390x/vxeh2_vlstr.c
create mode 100644 tests/tcg/s390x/vxeh2_vs.c
diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.target
index 8c9b6a13ce..921a056dd1 100644
--- a/tests/tcg/s390x/Makefile.target
+++ b/tests/tcg/s390x/Makefile.target
@@ -16,6 +16,14 @@ TESTS+=shift
TESTS+=trap
TESTS+=signals-s390x
+VECTOR_TESTS=vxeh2_vs
+VECTOR_TESTS+=vxeh2_vcvt
+VECTOR_TESTS+=vxeh2_vlstr
+
+TESTS+=$(VECTOR_TESTS)
+
+$(VECTOR_TESTS): CFLAGS+=-march=z15 -O2
+
ifneq ($(HAVE_GDB_BIN),)
GDB_SCRIPT=$(SRC_PATH)/tests/guest-debug/run-test.py
diff --git a/tests/tcg/s390x/vx.h b/tests/tcg/s390x/vx.h
new file mode 100644
index 00..2e66f8b714
--- /dev/null
+++ b/tests/tcg/s390x/vx.h
@@ -0,0 +1,19 @@
+#ifndef QEMU_TESTS_S390X_VX_H
+#define QEMU_TESTS_S390X_VX_H
+
+typedef union S390Vector {
+uint64_t d[2]; /* doubleword */
+uint32_t w[4]; /* word */
+uint16_t h[8]; /* halfword */
+uint8_t b[16]; /* byte */
+floatf[4]; /* float32 */
+double fd[2]; /* float64 */
+__uint128_t v;
+} S390Vector;
+
+#define ES8 0
+#define ES16 1
+#define ES32 2
+#define ES64 3
+
+#endif
\ No newline at end of file
diff --git a/tests/tcg/s390x/vxeh2_vcvt.c b/tests/tcg/s390x/vxeh2_vcvt.c
new file mode 100644
index 00..2e46841ab5
--- /dev/null
+++ b/tests/tcg/s390x/vxeh2_vcvt.c
@@ -0,0 +1,88 @@
+/*
+ * vxeh2_vcvt: vector-enhancements facility 2 vector convert *
+ */
+#include
+#include "vx.h"
+
+#define M_S 8
+#define M4_XxC 4
+#define M4_def M4_XxC
+
+static inline void vcfps(S390Vector *v1, S390Vector *v2,
+const uint8_t m3, const uint8_t m4, const uint8_t m5)
+{
+asm volatile(".insn vrr, 0xE7C3, %[v1], %[v2], 0, %[m3],
%[m4], %[m5]\n"
+: [v1] "=v" (v1->v)
+: [v2] "v" (v2->v)
+, [m3] "i" (m3)
+, [m4] "i" (m4)
+, [m5] "i" (m5));
+}
+
+static inline void vcfpl(S390Vector *v1, S390Vector *v2,
+const uint8_t m3, const uint8_t m4, const uint8_t m5)
+{
+asm volatile(".insn vrr, 0xE7C1, %[v1], %[v2], 0, %[m3],
%[m4], %[m5]\n"
+: [v1] "=v" (v1->v)
+: [v2] "v" (v2->v)
+, [m3] "i" (m3)
+, [m4] "i" (m4)
+, [m5] "i" (m5));
+}
+
+static inline void vcsfp(S390Vector *v1, S390Vector *v2,
+const uint8_t m3, const uint8_t m4, const uint8_t m5)
+{
+asm volatile(".insn vrr, 0xE7C2, %[v1], %[v2], 0, %[m3],
%[m4], %[m5]\n"
+: [v1] "=v" (v1->v)
+: [v2] "v" (v2->v)
+, [m3] "i" (m3)
+, [m4] "i" (m4)
+, [m5] "i" (m5));
+}
+
+static inline void vclfp(S390Vector *v1, S390Vector *v2,
+const uint8_t m3, const uint8_t m4, const uint8_t m5)
+{
+asm volatile(".insn vrr, 0xE7C0, %[v1], %[v2], 0, %[m3],
%[m4], %[m5]\n"
+: [v1] "=v" (v1->v)
+: [v2] "v" (v2->v)
+, [m3] "i" (m3)
+, [m4] "i" (m4)
+, [m5] "i" (m5));
+}
+
+int main(int argc, char *argv[])
+{
+S390Vector vd;
+S390Vector vs_i32 = { .w[0] = 1, .w[1] = 64, .w[2] = 1024, .w[3] = -10 };
+S390Vector vs_u32 = { .w[0] = 2, .w[1] = 32, .w[2] = 4096, .w[3] = };
+S390Vector vs_f32 = { .f[0] = 3.987, .f[1] = 5.123,
+ .f[2] = 4.499, .f[3] = 0.512 };
+
+vd.d[0] = vd.d[1] = 0;
+vcfps(, _i32, 2, M4_def, 0);
+if (1 != vd.f[0] || 1024 != vd.f[2] || 64 != vd.f[1] || -10 != vd.f[3]) {
+return 1;
+}
+
+vd.d[0] = vd.d[1] = 0;
+vcfpl(, _u32, 2, M4_def, 0);
+if (2 != vd.f[0] || 4096 != vd.f[2] || 32 != vd.f[1] || != vd.f[3]) {
+return 1;
+}
+
+vd.d[0] = vd.d[1] = 0;
+vcsfp(, _f32, 2, M4_def, 0);
+if (4 != vd.w[0] || 4 != vd.w[2] || 5 != vd.w[1] || 1 != vd.w[3]) {
+return 1;
+}
+
+vd.d[0] = vd.d[1] = 0;
+vclfp(, _f32, 2, M4_def, 0);
+if (4 != vd.w[0] || 4 != vd.w[2] || 5 != vd.w[1] || 1 !=
