GitHub user gczsjdy opened a pull request:
https://github.com/apache/spark/pull/21022
Fpga acc
You can merge this pull request into a Git repository by running:
$ git pull https://github.com/gczsjdy/spark fpga_acc
Alternatively you can review and apply these changes as the patch at:
https://github.com/apache/spark/pull/21022.patch
To close this pull request, make a commit to your master/trunk branch
with (at least) the following in the commit message:
This closes #21022
commit 7610bf07c16a8ff6d0b25072c43cb1811525a0cc
Author: GuoChenzhao
Date: 2017-07-05T15:10:24Z
Add framework for FPGA projection
commit 9e9d2b10cc0274634873f5193580dad86a74c82f
Author: Guo
Date: 2017-07-05T17:24:08Z
Implement Row=>FPGABatch adapter
commit 5911f7451b8c7c6d028e4dbf40de603e2c3eec51
Author: GuoChenzhao
Date: 2017-07-06T05:10:11Z
Implement FPGABatch=>Row adapter
commit 7f858bac018dbeb0c33bd254058b50b642a1ddc4
Author: GuoChenzhao
Date: 2017-07-06T05:21:00Z
Sum all rows in the same partition to 1 ByteBuffer
commit e8d33622cec06ff61c0c6991de93b5f0be68658e
Author: GuoChenzhao
Date: 2017-07-07T03:46:36Z
Fix bugs and refactor
commit 77c0eba7de191146c837d9868583d6902333fb0a
Author: GuoChenzhao
Date: 2017-07-07T03:48:16Z
Add test cases
commit b349b428beb53b34efbb55e02e83b4afbb0ffbb1
Author: GuoChenzhao
Date: 2017-07-07T06:16:07Z
Not use RDD[ByteBuffer] as transfer
commit 8a1c5f456f17c7dd140ce0b5bda977c377120ecf
Author: GuoChenzhao
Date: 2017-07-07T06:19:53Z
Update test
commit 3057ed32d127afaa1709ab455518b4f7294743e9
Author: GuoChenzhao
Date: 2017-07-07T06:21:52Z
Refactor: split different process
commit 50b16f0b587f1f3bca052ff44b4f5af203492d98
Author: GuoChenzhao
Date: 2017-07-07T06:51:37Z
Add String null trans code and test
commit 981bc7d011fdbfc5e07f87f21455f144372ae8bd
Author: GuoChenzhao
Date: 2017-07-07T07:01:49Z
Add insert arbitrary bytes code for FPGA's need, comment it for future ease
of test
commit 0adf36f4e4c16a01f57a38c6d6b314fd7308f557
Author: GuoChenzhao
Date: 2017-07-07T07:42:08Z
Add CMCC output Schema
commit cc9166b58a745b5a90cb829e9f6a98c76e2f466a
Author: GuoChenzhao
Date: 2017-07-10T02:02:36Z
Load native SQL FPGA engine
commit 83609ebf11d57fb274ed526336ef072a9f7a9599
Author: GuoChenzhao
Date: 2017-07-10T07:02:23Z
Remove not used bug code
commit 6fb740f5bdecfe413df8c84080a17840d9996e20
Author: GuoChenzhao
Date: 2017-07-10T07:04:13Z
Cut off excess chars for FPGA
commit 986010251ca096986c67c4984ea1fc6e10749f9d
Author: GuoChenzhao
Date: 2017-07-10T07:09:41Z
Add Java class calling FPGA code, not doing anything in FPGA engine for the
ease of unit test
commit 3e97550bc6b2da7baedfdd7545335aeae6be3520
Author: GuoChenzhao
Date: 2017-07-13T08:19:07Z
Call FPGA mocker, replace testOutputSchema with real outputSchema
commit 2670c2cc91ec85944afe300e84c4068418fff3b6
Author: GuoChenzhao
Date: 2017-07-13T12:05:48Z
Refresh OutputSchema and add reserved bytes to FPGA output
commit 8d94f2d584fa45cbed10c1e9e6eee47b5ae2be00
Author: GuoChenzhao
Date: 2017-07-13T12:26:39Z
Refactor readBytesFrom buffer to be consistent with put
commit 56dbeab3a730a839b0743fdeb56946eeb60ec929
Author: GuoChenzhao
Date: 2017-07-14T01:40:44Z
Add CMCC test case, and convert to new parquet code
commit f8514c7149c22a3f3f3f7d578d16734c453792df
Author: GuoChenzhao
Date: 2017-07-14T05:05:42Z
Refresh test code
commit 87ecb423359a3d92ffd9c25ef2d85e2f1c3e4758
Author: GuoChenzhao
Date: 2017-07-14T05:06:10Z
Force FileScan read all columns
commit c137ab3ed84d1e1a1e0be4713363b460354bc400
Author: GuoChenzhao
Date: 2017-07-20T04:14:55Z
Reuse UnsafeRowWriter & BufferHolder
commit 3d272160581aa85399cb73cadf8015e3e8e18e24
Author: GuoChenzhao
Date: 2017-07-20T04:26:45Z
Reduce steps load string column in row to buffer
commit 7a90c4d39735a9516462e7c621d750c8559b91e2
Author: GuoChenzhao
Date: 2017-07-25T03:07:00Z
Return buffer to FPGA after use
commit 7a96f45f94c98d1e02fdb492198895c0535bbf98
Author: GuoChenzhao
Date: 2017-07-25T04:00:22Z
Update FPGA JNI wrapper
commit 8938726ba854d97cdd7f3edcc323c44739c84d25
Author: GuoChenzhao
Date: 2017-08-01T07:49:34Z
Force trigger buffer to rowIterator process so as to return ByteBuffer
without error
commit afec465cf1613c1f7bd71836a1f9196e506c410b
Author: GuoChenzhao
Date: 2017-08-01T08:35:07Z
Change to fair lock
commit 81303a0b6b95371964784a71f905f21606108871
Author: GuoChenzhao
Date: 2017-08-01T13:12:21Z
Tune Buffer -> Row process
commit a3efd3a92e6b5aea13bbe788f082e06c3aa8e42a
Author: GuoChenzhao
Date: 2017-08-01T13:21:23Z
Only lock FPGA projection process
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