Re: [SeaBIOS] [Qemu-devel] [QEMU PATCH 2/7] hw/apic.c: rename bit functions to not conflict with bitops.h

2012-07-15 Thread Gleb Natapov
On Sat, Jul 14, 2012 at 09:09:23AM +, Blue Swirl wrote:
> On Fri, Jul 13, 2012 at 6:07 PM, Eduardo Habkost  wrote:
> > On Thu, Jul 12, 2012 at 07:24:35PM +, Blue Swirl wrote:
> >> On Tue, Jul 10, 2012 at 8:22 PM, Eduardo Habkost  
> >> wrote:
> >> > Signed-off-by: Eduardo Habkost 
> >>
> >> Maybe the bitops functions should be renamed instead, for example
> >> prefixed by 'qemu_'. That may be safer if one day the kernel find
> >> their way to system headers too.
> >
> > Well, if there's any risk the kernel functions will conflict with the
> > QEMU function names, that would be an additional reason to rename the
> > apic.c functions too, so they don't conflict with the kernel functions
> > either.
> 
> Yes, that could be the case too.
> 
Than it would be Linux headers problem and will be fixed there.

> >
> > Personally, I would never sent a patch to rename the bitops.h functions,
> > as the current names work perfectly to me.
> >
> >>
> >> > ---
> >> >  hw/apic.c |   34 +-
> >> >  1 file changed, 17 insertions(+), 17 deletions(-)
> >> >
> >> > diff --git a/hw/apic.c b/hw/apic.c
> >> > index 60552df..d322fe3 100644
> >> > --- a/hw/apic.c
> >> > +++ b/hw/apic.c
> >> > @@ -50,7 +50,7 @@ static int ffs_bit(uint32_t value)
> >> >  return ctz32(value);
> >> >  }
> >> >
> >> > -static inline void set_bit(uint32_t *tab, int index)
> >> > +static inline void apic_set_bit(uint32_t *tab, int index)
> >> >  {
> >> >  int i, mask;
> >> >  i = index >> 5;
> >> > @@ -58,7 +58,7 @@ static inline void set_bit(uint32_t *tab, int index)
> >> >  tab[i] |= mask;
> >> >  }
> >> >
> >> > -static inline void reset_bit(uint32_t *tab, int index)
> >> > +static inline void apic_reset_bit(uint32_t *tab, int index)
> >> >  {
> >> >  int i, mask;
> >> >  i = index >> 5;
> >> > @@ -66,7 +66,7 @@ static inline void reset_bit(uint32_t *tab, int index)
> >> >  tab[i] &= ~mask;
> >> >  }
> >> >
> >> > -static inline int get_bit(uint32_t *tab, int index)
> >> > +static inline int apic_get_bit(uint32_t *tab, int index)
> >> >  {
> >> >  int i, mask;
> >> >  i = index >> 5;
> >> > @@ -183,7 +183,7 @@ void apic_deliver_pic_intr(DeviceState *d, int level)
> >> >  case APIC_DM_FIXED:
> >> >  if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
> >> >  break;
> >> > -reset_bit(s->irr, lvt & 0xff);
> >> > +apic_reset_bit(s->irr, lvt & 0xff);
> >> >  /* fall through */
> >> >  case APIC_DM_EXTINT:
> >> >  cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
> >> > @@ -379,13 +379,13 @@ void apic_poll_irq(DeviceState *d)
> >> >
> >> >  static void apic_set_irq(APICCommonState *s, int vector_num, int 
> >> > trigger_mode)
> >> >  {
> >> > -apic_report_irq_delivered(!get_bit(s->irr, vector_num));
> >> > +apic_report_irq_delivered(!apic_get_bit(s->irr, vector_num));
> >> >
> >> > -set_bit(s->irr, vector_num);
> >> > +apic_set_bit(s->irr, vector_num);
> >> >  if (trigger_mode)
> >> > -set_bit(s->tmr, vector_num);
> >> > +apic_set_bit(s->tmr, vector_num);
> >> >  else
> >> > -reset_bit(s->tmr, vector_num);
> >> > +apic_reset_bit(s->tmr, vector_num);
> >> >  if (s->vapic_paddr) {
> >> >  apic_sync_vapic(s, SYNC_ISR_IRR_TO_VAPIC);
> >> >  /*
> >> > @@ -405,8 +405,8 @@ static void apic_eoi(APICCommonState *s)
> >> >  isrv = get_highest_priority_int(s->isr);
> >> >  if (isrv < 0)
> >> >  return;
> >> > -reset_bit(s->isr, isrv);
> >> > -if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && get_bit(s->tmr, 
> >> > isrv)) {
> >> > +apic_reset_bit(s->isr, isrv);
> >> > +if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && 
> >> > apic_get_bit(s->tmr, isrv)) {
> >> >  ioapic_eoi_broadcast(isrv);
> >> >  }
> >> >  apic_sync_vapic(s, SYNC_FROM_VAPIC | SYNC_TO_VAPIC);
> >> > @@ -445,7 +445,7 @@ static void apic_get_delivery_bitmask(uint32_t 
> >> > *deliver_bitmask,
> >> >  int idx = apic_find_dest(dest);
> >> >  memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * 
> >> > sizeof(uint32_t));
> >> >  if (idx >= 0)
> >> > -set_bit(deliver_bitmask, idx);
> >> > +apic_set_bit(deliver_bitmask, idx);
> >> >  }
> >> >  } else {
> >> >  /* XXX: cluster mode */
> >> > @@ -455,11 +455,11 @@ static void apic_get_delivery_bitmask(uint32_t 
> >> > *deliver_bitmask,
> >> >  if (apic_iter) {
> >> >  if (apic_iter->dest_mode == 0xf) {
> >> >  if (dest & apic_iter->log_dest)
> >> > -set_bit(deliver_bitmask, i);
> >> > +apic_set_bit(deliver_bitmask, i);
> >> >  } else if (apic_iter->dest_mode == 0x0) {
> >> >  if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
> >> >  (dest & apic_iter->lo

Re: [SeaBIOS] Plan to add POST memory manager (PMM) support

2012-07-15 Thread Fred .
Good luck with it! :)

Hope to hear back soon how it goes with it, and patches contributed
back upstreams.

On Sun, Jul 15, 2012 at 6:14 AM, Darmawan Salihun
 wrote:
> Hi Fred,
>
> Yes, I need it to test something at work. It's not very urgent at the moment.
>
> Regards,
>
> Darmawan
>
> On 7/15/12, Fred .  wrote:
>> Darmawan, will you be implementing PnP support in SeaBIOS?
>>
>> On Sat, Jul 14, 2012 at 9:50 PM, Darmawan Salihun
>>  wrote:
>>> On 7/15/12, Kevin O'Connor  wrote:
 On Sun, Jul 15, 2012 at 02:20:42AM +0700, Darmawan Salihun wrote:
> First, I made a mistake, I was actually referring to the PnP support

 On Sat, Jul 14, 2012 at 10:57:00PM +0700, Darmawan Salihun wrote:
> Is there any plan to add this feature in the near future?
> I have a plan to add the feature if it's not there yet, but I want to
> know first whether
> there's already plan for that.

 I have no plans to implement PnP, and I have not heard of any plans
 from anyone else.  To the best of my knowledge, nothing really uses
 the PnP interface anymore.  The stubs are in SeaBIOS to make some
 option roms (namely gpxe) recognize that the BBS spec is supported.

 Feel free to send patches.

 -Kevin

>>>
>>> OK. Thanks for the info.
>>>
>>> Regards,
>>>
>>> Darmawan
>>>
>>> --
>>> 
>>> -= Human knowledge belongs to the world =-
>>>
>>> ___
>>> SeaBIOS mailing list
>>> SeaBIOS@seabios.org
>>> http://www.seabios.org/mailman/listinfo/seabios
>>
>
>
> --
> 
> -= Human knowledge belongs to the world =-

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