[SeaBIOS] [PATCH v2] q35: Add new PCI slot to irq routing function
q35/ich9 doesn't use the same interrupt mapping function as
i440fx/piix. PIRQA:D and PIRQE:H are programmed identically, but we
start at index 0, not index -1. Slots 25 through 31 are also
programmed independently.
When running qemu w/o this patch, a device at address 0:6.0 will have
its PCI interrupt line register programmed with irq 10 (as seen by
info pci), but it actually uses irq 11 (as reported the guest). Half
of the interrupt lines are misprogrammedi like this. Functionally, a
fully emulated qemu guest doesn't care much, but when we try to use
device assignment, we really need to know the correct irqs.
Signed-off-by: Alex Williamson
---
v2: separate the root bus slot for the switch statement, always 0-31
src/pciinit.c | 33 -
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/src/pciinit.c b/src/pciinit.c
index 857e8af..8675adb 100644
--- a/src/pciinit.c
+++ b/src/pciinit.c
@@ -91,8 +91,10 @@ const u8 pci_irqs[4] = {
10, 10, 11, 11
};
+static int (*pci_slot_get_irq)(struct pci_device *pci, int pin);
+
// Return the global irq number corresponding to a host bus device irq pin.
-static int pci_slot_get_irq(struct pci_device *pci, int pin)
+static int piix_pci_slot_get_irq(struct pci_device *pci, int pin)
{
int slot_addend = 0;
@@ -104,6 +106,31 @@ static int pci_slot_get_irq(struct pci_device *pci, int
pin)
return pci_irqs[(pin - 1 + slot_addend) & 3];
}
+static int mch_pci_slot_get_irq(struct pci_device *pci, int pin)
+{
+int irq, slot, pin_addend = 0;
+
+while (pci->parent != NULL) {
+pin_addend += pci_bdf_to_dev(pci->bdf);
+pci = pci->parent;
+}
+slot = pci_bdf_to_dev(pci->bdf);
+
+switch (slot) {
+/* Slots 0-24 rotate slot:pin mapping similar to piix above, but
+ with a different starting index - see q35-acpi-dsdt.dsl */
+case 0 ... 24:
+irq = pci_irqs[(pin - 1 + pin_addend + slot) & 3];
+break;
+/* Slots 25-31 all use LNKA mapping (or LNKE, but A:D = E:H) */
+case 25 ... 31:
+irq = pci_irqs[(pin - 1 + pin_addend) & 3];
+break;
+}
+
+return irq;
+}
+
/* PIIX3/PIIX4 PCI to ISA bridge */
static void piix_isa_bridge_init(struct pci_device *pci, void *arg)
{
@@ -292,6 +319,8 @@ void i440fx_mem_addr_init(struct pci_device *dev, void *arg)
pcimem_start = 0x8000;
else if (RamSize <= 0xc000)
pcimem_start = 0xc000;
+
+pci_slot_get_irq = piix_pci_slot_get_irq;
}
void mch_mem_addr_init(struct pci_device *dev, void *arg)
@@ -310,6 +339,8 @@ void mch_mem_addr_init(struct pci_device *dev, void *arg)
/* setup pci i/o window (above mmconfig) */
pcimem_start = addr + size;
+
+pci_slot_get_irq = mch_pci_slot_get_irq;
}
static const struct pci_device_id pci_platform_tbl[] = {
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Re: [SeaBIOS] [PATCH 2/2] q35: Add new PCI slot to irq routing function
On Tue, 2013-01-22 at 15:12 -0700, Alex Williamson wrote:
> q35/ich9 doesn't use the same interrupt mapping function as
> i440fx/piix. PIRQA:D and PIRQE:H are programmed identically, but we
> start at index 0, not index -1. Slots 25 through 31 are also
> programmed independently.
>
> When running qemu w/o this patch, a device at address 0:6.0 will have
> its PCI interrupt line register programmed with irq 10 (as seen by
> info pci), but it actually uses irq 11 (as reported the guest). Half
> of the interrupt lines are misprogrammedi like this. Functionally, a
> fully emulated qemu guest doesn't care much, but when we try to use
> device assignment, we really need to know the correct irqs.
>
> Signed-off-by: Alex Williamson
> ---
> src/pciinit.c | 35 ++-
> 1 file changed, 34 insertions(+), 1 deletion(-)
>
> diff --git a/src/pciinit.c b/src/pciinit.c
> index 857e8af..ddac7e7 100644
> --- a/src/pciinit.c
> +++ b/src/pciinit.c
> @@ -91,8 +91,10 @@ const u8 pci_irqs[4] = {
> 10, 10, 11, 11
> };
>
> +static int (*pci_slot_get_irq)(struct pci_device *pci, int pin);
> +
> // Return the global irq number corresponding to a host bus device irq pin.
> -static int pci_slot_get_irq(struct pci_device *pci, int pin)
> +static int piix_pci_slot_get_irq(struct pci_device *pci, int pin)
> {
> int slot_addend = 0;
>
> @@ -104,6 +106,33 @@ static int pci_slot_get_irq(struct pci_device *pci, int
> pin)
> return pci_irqs[(pin - 1 + slot_addend) & 3];
> }
>
> +static int mch_pci_slot_get_irq(struct pci_device *pci, int pin)
> +{
> +int irq, slot_addend = 0;
> +
> +while (pci->parent != NULL) {
> +slot_addend += pci_bdf_to_dev(pci->bdf);
> +pci = pci->parent;
> +}
> +slot_addend += pci_bdf_to_dev(pci->bdf);
> +
> +switch (slot_addend) {
Nak, I'm not accounting for the bridges properly here.
> +/* Slots 0-24 rotate slot:pin mapping similar to piix above, but
> + with a different starting index - see q35-acpi-dsdt.dsl */
> +case 0 ... 24:
> +irq = pci_irqs[(pin - 1 + slot_addend) & 3];
> +break;
> +/* Slots 25-31 all use LNKA mapping (or LNKE, but A:D = E:H) */
> +case 25 ... 31:
> +irq = pci_irqs[pin - 1];
> +break;
> +default:
> +irq = 0;
> +}
> +
> +return irq;
> +}
> +
> /* PIIX3/PIIX4 PCI to ISA bridge */
> static void piix_isa_bridge_init(struct pci_device *pci, void *arg)
> {
> @@ -292,6 +321,8 @@ void i440fx_mem_addr_init(struct pci_device *dev, void
> *arg)
> pcimem_start = 0x8000;
> else if (RamSize <= 0xc000)
> pcimem_start = 0xc000;
> +
> +pci_slot_get_irq = piix_pci_slot_get_irq;
> }
>
> void mch_mem_addr_init(struct pci_device *dev, void *arg)
> @@ -310,6 +341,8 @@ void mch_mem_addr_init(struct pci_device *dev, void *arg)
>
> /* setup pci i/o window (above mmconfig) */
> pcimem_start = addr + size;
> +
> +pci_slot_get_irq = mch_pci_slot_get_irq;
> }
>
> static const struct pci_device_id pci_platform_tbl[] = {
>
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[SeaBIOS] [PATCH 2/2] q35: Add new PCI slot to irq routing function
q35/ich9 doesn't use the same interrupt mapping function as
i440fx/piix. PIRQA:D and PIRQE:H are programmed identically, but we
start at index 0, not index -1. Slots 25 through 31 are also
programmed independently.
When running qemu w/o this patch, a device at address 0:6.0 will have
its PCI interrupt line register programmed with irq 10 (as seen by
info pci), but it actually uses irq 11 (as reported the guest). Half
of the interrupt lines are misprogrammedi like this. Functionally, a
fully emulated qemu guest doesn't care much, but when we try to use
device assignment, we really need to know the correct irqs.
Signed-off-by: Alex Williamson
---
src/pciinit.c | 35 ++-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/src/pciinit.c b/src/pciinit.c
index 857e8af..ddac7e7 100644
--- a/src/pciinit.c
+++ b/src/pciinit.c
@@ -91,8 +91,10 @@ const u8 pci_irqs[4] = {
10, 10, 11, 11
};
+static int (*pci_slot_get_irq)(struct pci_device *pci, int pin);
+
// Return the global irq number corresponding to a host bus device irq pin.
-static int pci_slot_get_irq(struct pci_device *pci, int pin)
+static int piix_pci_slot_get_irq(struct pci_device *pci, int pin)
{
int slot_addend = 0;
@@ -104,6 +106,33 @@ static int pci_slot_get_irq(struct pci_device *pci, int
pin)
return pci_irqs[(pin - 1 + slot_addend) & 3];
}
+static int mch_pci_slot_get_irq(struct pci_device *pci, int pin)
+{
+int irq, slot_addend = 0;
+
+while (pci->parent != NULL) {
+slot_addend += pci_bdf_to_dev(pci->bdf);
+pci = pci->parent;
+}
+slot_addend += pci_bdf_to_dev(pci->bdf);
+
+switch (slot_addend) {
+/* Slots 0-24 rotate slot:pin mapping similar to piix above, but
+ with a different starting index - see q35-acpi-dsdt.dsl */
+case 0 ... 24:
+irq = pci_irqs[(pin - 1 + slot_addend) & 3];
+break;
+/* Slots 25-31 all use LNKA mapping (or LNKE, but A:D = E:H) */
+case 25 ... 31:
+irq = pci_irqs[pin - 1];
+break;
+default:
+irq = 0;
+}
+
+return irq;
+}
+
/* PIIX3/PIIX4 PCI to ISA bridge */
static void piix_isa_bridge_init(struct pci_device *pci, void *arg)
{
@@ -292,6 +321,8 @@ void i440fx_mem_addr_init(struct pci_device *dev, void *arg)
pcimem_start = 0x8000;
else if (RamSize <= 0xc000)
pcimem_start = 0xc000;
+
+pci_slot_get_irq = piix_pci_slot_get_irq;
}
void mch_mem_addr_init(struct pci_device *dev, void *arg)
@@ -310,6 +341,8 @@ void mch_mem_addr_init(struct pci_device *dev, void *arg)
/* setup pci i/o window (above mmconfig) */
pcimem_start = addr + size;
+
+pci_slot_get_irq = mch_pci_slot_get_irq;
}
static const struct pci_device_id pci_platform_tbl[] = {
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[SeaBIOS] [PATCH 0/2] q35: Fix seabios IRQ mapping and setup
This seems like the easier approach from my RFC yesterday. Instead of trying to make ich9 interrupt mapping look like piix, just add a new slot-to-irq function so we can not only get bus 0 devices, but root ports fixed as well. The change from piix mapping is subtle, but required for device assignment. Additionally, fix the PIRQn initialization value, enabling the interrupts for boot ROMs. Thanks, Alex --- Alex Williamson (2): q35: Enable all PIRQn IRQs at startup q35: Add new PCI slot to irq routing function src/pciinit.c | 41 - 1 file changed, 36 insertions(+), 5 deletions(-) ___ SeaBIOS mailing list SeaBIOS@seabios.org http://www.seabios.org/mailman/listinfo/seabios
[SeaBIOS] [PATCH 1/2] q35: Enable all PIRQn IRQs at startup
We seem to use the IRQEN bit of the PIRQn registers interchangeably to select APIC mode or to disable an IRQ. I can't decide if we're intending to disable the IRQ or select APIC mode here, but in either case it prevents PIC mode assigned devices from working. When seabios writes IRQEN to these registers, qemu interprets that as APIC mode, so while the boot ROM driver is waiting for an interrupt on ISA compatible IRQ 10 or 11, KVM is injecting interrupts to APIC pins 16 - 23. Devices on the root bus use PIRQE:H while the root ports use PIRQA:D. Enable them all so we don't limit where we support boot ROMs. The guest will later disable unused IRQs with the ACPI _DIS method. Signed-off-by: Alex Williamson --- src/pciinit.c |6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/pciinit.c b/src/pciinit.c index a406bbd..857e8af 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -143,11 +143,9 @@ void mch_isa_bridge_init(struct pci_device *dev, void *arg) /* activate irq remapping in LPC */ /* PIRQ[A-D] routing */ -pci_config_writeb(bdf, ICH9_LPC_PIRQA_ROUT + i, - irq | ICH9_LPC_PIRQ_ROUT_IRQEN); +pci_config_writeb(bdf, ICH9_LPC_PIRQA_ROUT + i, irq); /* PIRQ[E-H] routing */ -pci_config_writeb(bdf, ICH9_LPC_PIRQE_ROUT + i, - irq | ICH9_LPC_PIRQ_ROUT_IRQEN); +pci_config_writeb(bdf, ICH9_LPC_PIRQE_ROUT + i, irq); } outb(elcr[0], ICH9_LPC_PORT_ELCR1); outb(elcr[1], ICH9_LPC_PORT_ELCR2); ___ SeaBIOS mailing list SeaBIOS@seabios.org http://www.seabios.org/mailman/listinfo/seabios
Re: [SeaBIOS] [Qemu-devel] [Qemu PATCH v2] add a boot option to do strict boot
Eric Blake writes:
> On 01/22/2013 08:52 AM, Amos Kong wrote:
>
Libvirt will need to expose an attribute that lets the user control
whether to use this new option; how do we probe via QMP whether the
new
-boot strict=on command-line option is available?
>>>
>>> Hi all,
>>>
>>> How about add new info/query command?
>>>
>>> (hmp) info strict-boot
>>> on
>>>
>>> (qmp) {"execute": "query-strict-boot"}
>>> {"return": {"state": true}}
>>
>> It might be not a good solution, I already updated qemu-options.hx,
>> we can check help message to know if this new option is added or not.
>
> Having libvirt probe the -help output is out of the question. We
> already declared that for qemu 1.3 and beyond, ALL command line behavior
> must ALSO be probe-able via QMP. I think Anthony had a trick for
> testing for existence of various command line options without needing to
> add a new query-strict-boot command, but I don't remember what that
> trick was.
We need a generic query-config-schema command.
Regards,
Anthony Liguori
>
> --
> Eric Blake eblake redhat com+1-919-301-3266
> Libvirt virtualization library http://libvirt.org
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Re: [SeaBIOS] [Qemu-devel] [Qemu PATCH v2] add a boot option to do strict boot
On 01/22/2013 08:52 AM, Amos Kong wrote:
>>>
>>> Libvirt will need to expose an attribute that lets the user control
>>> whether to use this new option; how do we probe via QMP whether the
>>> new
>>> -boot strict=on command-line option is available?
>>
>> Hi all,
>>
>> How about add new info/query command?
>>
>> (hmp) info strict-boot
>> on
>>
>> (qmp) {"execute": "query-strict-boot"}
>> {"return": {"state": true}}
>
> It might be not a good solution, I already updated qemu-options.hx,
> we can check help message to know if this new option is added or not.
Having libvirt probe the -help output is out of the question. We
already declared that for qemu 1.3 and beyond, ALL command line behavior
must ALSO be probe-able via QMP. I think Anthony had a trick for
testing for existence of various command line options without needing to
add a new query-strict-boot command, but I don't remember what that
trick was.
--
Eric Blake eblake redhat com+1-919-301-3266
Libvirt virtualization library http://libvirt.org
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Re: [SeaBIOS] [Qemu-devel] [Qemu PATCH v2] add a boot option to do strict boot
- Original Message -
> On 01/09/2013 01:39 AM, Amos Kong wrote:
> > Current seabios will try to boot from selected devices first,
> > if they are all failed, seabios will also try to boot from
> > un-selected devices.
> >
> > We need to make it configurable. I already posted a seabios
> > patch to add a new device type to halt booting. Qemu can add
> > "HALT" at the end of bootindex string, then seabios will halt
> > booting after trying to boot from selected devices.
> >
> > This option only effects when boot priority is changed by
> > bootindex options, the old style(-boot order=..) will still
> > try to boot from un-selected devices.
> >
> > v2: add HALT entry in get_boot_devices_list()
> > define boot_strict to bool
> >
> > Signed-off-by: Amos Kong
> > ---
>
> Libvirt will need to expose an attribute that lets the user control
> whether to use this new option; how do we probe via QMP whether the
> new
> -boot strict=on command-line option is available?
Hi all,
How about add new info/query command?
(hmp) info strict-boot
on
(qmp) {"execute": "query-strict-boot"}
{"return": {"state": true}}
> > +++ b/qemu-options.hx
> > @@ -376,14 +376,14 @@ ETEXI
> >
> > DEF("boot", HAS_ARG, QEMU_OPTION_boot,
> > "-boot [order=drives][,once=drives][,menu=on|off]\n"
> > -"
> > [,splash=sp_name][,splash-time=sp_time][,reboot-timeout=rb_time]\n"
> > +"
> >
> > [,splash=sp_name][,splash-time=sp_time][,reboot-timeout=rb_time][,strict=on|off]\n"
> > "'drives': floppy (a), hard disk (c), CD-ROM
> > (d), network (n)\n"
> > "'sp_name': the file's name that would be
> > passed to bios as logo picture, if menu=on\n"
> > "'sp_time': the period that splash picture
> > last if menu=on, unit is ms\n"
> > "'rb_timeout': the timeout before guest reboot
> > when boot failed, unit is ms\n",
>
> So if I understand correctly, -boot order=... is incompatible with
> -boot
> strict=on;
They are not incompatible, order will effect the priority,
strict decides if boot from un-selected device.
> even though you have listed both options under a single
> -boot
> entry in the -help. We've already declared that -help output is no
> longer guaranteed stable, so this doesn't really impact libvirt, but
> would it make any more sense to list this as two orthogonal entries,
> to
> make it clear that they don't mix?
>
> -boot order=drivers[,once=drives]...
> -boot strict=on|off[,menu=on|off]...
>
> But this is all bikeshedding, so it's not worth a v3 if you disagree.
>
> --
> Eric Blake eblake redhat com+1-919-301-3266
> Libvirt virtualization library http://libvirt.org
>
>
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Re: [SeaBIOS] [Qemu-devel] [Qemu PATCH v2] add a boot option to do strict boot
On Tue, Jan 22, 2013 at 10:23:32AM -0500, Amos Kong wrote:
> - Original Message -
> > On 01/09/2013 01:39 AM, Amos Kong wrote:
> > > Current seabios will try to boot from selected devices first,
> > > if they are all failed, seabios will also try to boot from
> > > un-selected devices.
> > >
> > > We need to make it configurable. I already posted a seabios
> > > patch to add a new device type to halt booting. Qemu can add
> > > "HALT" at the end of bootindex string, then seabios will halt
> > > booting after trying to boot from selected devices.
> > >
> > > This option only effects when boot priority is changed by
> > > bootindex options, the old style(-boot order=..) will still
> > > try to boot from un-selected devices.
> > >
> > > v2: add HALT entry in get_boot_devices_list()
> > > define boot_strict to bool
> > >
> > > Signed-off-by: Amos Kong
> > > ---
> >
> > Libvirt will need to expose an attribute that lets the user control
> > whether to use this new option; how do we probe via QMP whether the
> > new
> > -boot strict=on command-line option is available?
>
> Hi all,
>
> How about add new info/query command?
>
> (hmp) info strict-boot
> on
>
> (qmp) {"execute": "query-strict-boot"}
> {"return": {"state": true}}
It might be not a good solution, I already updated qemu-options.hx,
we can check help message to know if this new option is added or not.
Daniel, Laine, do you have some suggestion?
> > > +++ b/qemu-options.hx
> > > @@ -376,14 +376,14 @@ ETEXI
> > >
> > > DEF("boot", HAS_ARG, QEMU_OPTION_boot,
> > > "-boot [order=drives][,once=drives][,menu=on|off]\n"
> > > -"
> > > [,splash=sp_name][,splash-time=sp_time][,reboot-timeout=rb_time]\n"
> > > +"
> > >
> > > [,splash=sp_name][,splash-time=sp_time][,reboot-timeout=rb_time][,strict=on|off]\n"
> > > "'drives': floppy (a), hard disk (c), CD-ROM
> > > (d), network (n)\n"
> > > "'sp_name': the file's name that would be
> > > passed to bios as logo picture, if menu=on\n"
> > > "'sp_time': the period that splash picture
> > > last if menu=on, unit is ms\n"
> > > "'rb_timeout': the timeout before guest reboot
> > > when boot failed, unit is ms\n",
> >
> > So if I understand correctly, -boot order=... is incompatible with
> > -boot
> > strict=on;
>
> They are not incompatible, order will effect the priority,
> strict decides if boot from un-selected device.
>
> > even though you have listed both options under a single
> > -boot
> > entry in the -help. We've already declared that -help output is no
> > longer guaranteed stable, so this doesn't really impact libvirt, but
> > would it make any more sense to list this as two orthogonal entries,
> > to
> > make it clear that they don't mix?
> >
> > -boot order=drivers[,once=drives]...
> > -boot strict=on|off[,menu=on|off]...
> >
> > But this is all bikeshedding, so it's not worth a v3 if you disagree.
> >
> > --
> > Eric Blake eblake redhat com+1-919-301-3266
> > Libvirt virtualization library http://libvirt.org
> >
> >
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Re: [SeaBIOS] Problems booting FreeBSD9 under SeaBIOS as CSM
David Woodhouse wrote: > seems to *stop* before displaying the 'Autoboot in 9 seconds Sounds like a timer problem. The hardware interrupt somehow supports that theory. //Peter pgp2EGQXOpjLv.pgp Description: PGP signature ___ SeaBIOS mailing list SeaBIOS@seabios.org http://www.seabios.org/mailman/listinfo/seabios
[SeaBIOS] Problems booting FreeBSD9 under SeaBIOS as CSM
I'm probably going to have to chase this one down for myself, but before I do I figured I'd ask if anyone's seen anything similar before, and can give me some pointers... When booting FreeBSD 9 under real SeaBIOS, it all works fine. When SeaBIOS is invoked for a 'legacy' boot under EFI, the FreeBSD bootloader gets as far as displaying its main screen with the FreeBSD banner and the ASCII-art dæmon and the options, but then seems to *stop* before displaying the 'Autoboot in 9 seconds. Press [Space] to pause' message. The qemu log shows that it's in an endless stream of Servicing hardware INT=0x20 44024: v=20 cr0=0032 e= i=0 cpl=0 IP=f000:ffec pc=000fffec SP=:5d9c EAX= EAX= EBX=5dd0 ECX=ffea EDX= ESI=c350 EDI= EBP= ESP=5d9c EIP=ffec EFL=0202 [---] CPL=0 II=0 A20=1 SMM=0 HLT=0 ES =d500 000d5000 00cf9300 CS =f000 000f 9a00 SS = 00cf9300 DS = 00cf9300 FS = 00cff300 GS = 00cff300 LDT= 8200 TR =0038 5f98 2067 8900 GDT= 9590 003f IDT= 03ff CR0=0032 CR2= CR3=7fb36000 CR4=0648 DR0= DR1= DR2= DR3= DR6=0ff0 DR7=0400 CCS=0044 CCD= CCO=EFLAGS EFER= 44025: v=1c cr0=0032 e= i=1 cpl=0 IP=f000:f856 pc=000ff856 SP=:5d72 EAX= EAX= EBX= ECX= EDX= ESI= EDI= EBP= ESP=5d72 EIP=f856 EFL=0202 [---] CPL=0 II=0 A20=1 SMM=0 HLT=0 ES = 00cf9300 CS =f000 000f 9a00 SS = 00cf9300 DS = 00cf9300 FS = 00cff300 GS = 00cff300 LDT= 8200 TR =0038 5f98 2067 8900 GDT= 9590 003f IDT= 03ff CR0=0032 CR2= CR3=7fb36000 CR4=0648 DR0= DR1= DR2= DR3= DR6=0ff0 DR7=0400 CCS= CCD= CCO=EFLAGS EFER= Servicing hardware INT=0x20 -- dwmw2 smime.p7s Description: S/MIME cryptographic signature ___ SeaBIOS mailing list SeaBIOS@seabios.org http://www.seabios.org/mailman/listinfo/seabios
