[SeaBIOS] [PATCH] Update EFI_COMPATIBILITY16_TABLE to match 0.98 spec update

2013-12-02 Thread David Woodhouse 
We expect to use the space between the top of option ROMs and the bottom
of our own BIOS code as a stack. OVMF was previously marking the whole
region from 0xC to 0xF read-only before invoking our Legacy16Boot
method. Read-only stack considered harmful.

Version 0.98 of the CSM spec adds the UmaAddress and UmaSize fields, which
allow the CSM to specify a memory region that needs to be writable.

Signed-off-by: David Woodhouse david.woodho...@intel.com
---
The corresponding patch hasn't hit the OVMF/EDKII tree yet, but that
shouldn't stop us from applying it anyway. CSM support was completely
broken before this anyway — it required *some* way of hacking around
this problem. And this patch does not harm on its own either.

 src/fw/csm.c |  6 +-
 src/std/LegacyBios.h | 20 
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/src/fw/csm.c b/src/fw/csm.c
index afd7ffe..6fe3a1b 100644
--- a/src/fw/csm.c
+++ b/src/fw/csm.c
@@ -34,6 +34,8 @@ EFI_COMPATIBILITY16_TABLE csm_compat_table VARFSEG 
__aligned(16) = {
 .Compatibility16CallOffset = 0 /* Filled in by checkrom.py */,
 .OemIdStringPointer = (u32)SeaBIOS,
 .AcpiRsdPtrPointer = (u32)csm_rsdp,
+.UmaAddress = 0xe,
+.UmaSize = 0x1,
 };
 
 EFI_TO_COMPATIBILITY16_INIT_TABLE *csm_init_table;
@@ -46,9 +48,11 @@ extern void __csm_return(struct bregs *regs) __noreturn;
 static void
 csm_return(struct bregs *regs)
 {
-dprintf(3, handle_csm returning AX=%04x\n, regs-ax);
+u32 top = rom_get_max();
 
 PICMask = pic_irqmask_read();
+csm_compat_table.UmaAddress = top;
+csm_compat_table.UmaSize = 0xf - top;
 __csm_return(regs);
 }
 
diff --git a/src/std/LegacyBios.h b/src/std/LegacyBios.h
index cf0c3c5..5170c37 100644
--- a/src/std/LegacyBios.h
+++ b/src/std/LegacyBios.h
@@ -228,6 +228,26 @@ typedef struct {
   /// Maximum PCI bus number assigned.
   ///
   UINT8 LastPciBus;
+
+  ///
+  /// Start address of UMB RAM
+  ///
+  UINT32UmaAddress;
+
+  ///
+  /// Size of UMB RAM
+  ///
+  UINT32UmaSize;
+
+  ///
+  /// Start address of persistent allocation in high (1MiB) memory
+  ///
+  UINT32HiPermanentMemoryAddress;
+
+  ///
+  /// Size of persistent allocation in high (1MiB) memory
+  ///
+  UINT32HiPermanentMemorySize;
 } EFI_COMPATIBILITY16_TABLE;
 
 ///
-- 
1.8.3.1


-- 
David WoodhouseOpen Source Technology Centre
david.woodho...@intel.com  Intel Corporation


smime.p7s
Description: S/MIME cryptographic signature
___
SeaBIOS mailing list
SeaBIOS@seabios.org
http://www.seabios.org/mailman/listinfo/seabios

Re: [SeaBIOS] [PATCH] Update EFI_COMPATIBILITY16_TABLE to match 0.98 spec update

2013-12-02 Thread Kevin O'Connor 
On Mon, Dec 02, 2013 at 04:02:59PM +, David Woodhouse wrote:
 We expect to use the space between the top of option ROMs and the bottom
 of our own BIOS code as a stack. OVMF was previously marking the whole
 region from 0xC to 0xF read-only before invoking our Legacy16Boot
 method. Read-only stack considered harmful.
 
 Version 0.98 of the CSM spec adds the UmaAddress and UmaSize fields, which
 allow the CSM to specify a memory region that needs to be writable.

Excellent!

 --- a/src/fw/csm.c
 +++ b/src/fw/csm.c
 @@ -34,6 +34,8 @@ EFI_COMPATIBILITY16_TABLE csm_compat_table VARFSEG 
 __aligned(16) = {
  .Compatibility16CallOffset = 0 /* Filled in by checkrom.py */,
  .OemIdStringPointer = (u32)SeaBIOS,
  .AcpiRsdPtrPointer = (u32)csm_rsdp,
 +.UmaAddress = 0xe,
 +.UmaSize = 0x1,

I think we can be a little more accurate here.  See the incremental
patch (untested) below and let me know if I've missed anything.

-Kevin


diff --git a/src/fw/csm.c b/src/fw/csm.c
index b7a4211..ae3a786 100644
--- a/src/fw/csm.c
+++ b/src/fw/csm.c
@@ -34,8 +34,10 @@ EFI_COMPATIBILITY16_TABLE csm_compat_table VARFSEG 
__aligned(16) = {
 .Compatibility16CallOffset = 0 /* Filled in by checkrom.py */,
 .OemIdStringPointer = (u32)SeaBIOS,
 .AcpiRsdPtrPointer = (u32)csm_rsdp,
-.UmaAddress = 0xe,
+#if CONFIG_MALLOC_UPPERMEMORY
+.UmaAddress = (u32)zonelow_base,
 .UmaSize = 0x1,
+#endif
 };
 
 EFI_TO_COMPATIBILITY16_INIT_TABLE *csm_init_table;
@@ -48,11 +50,12 @@ extern void __csm_return(struct bregs *regs) __noreturn;
 static void
 csm_return(struct bregs *regs)
 {
-u32 top = rom_get_max();
-
 PICMask = pic_irqmask_read();
-csm_compat_table.UmaAddress = top;
-csm_compat_table.UmaSize = 0xf - top;
+if (CONFIG_MALLOC_UPPERMEMORY) {
+u32 top = rom_get_max();
+csm_compat_table.UmaAddress = top;
+csm_compat_table.UmaSize = (u32)zonelow_base + 0x1 - top;
+}
 __csm_return(regs);
 }
 

___
SeaBIOS mailing list
SeaBIOS@seabios.org
http://www.seabios.org/mailman/listinfo/seabios