Re: [SeaBIOS] [PATCHv2] smp: Replace QEMU SMP init assembler code with C; run only in 32bit mode.
Il 31/05/2014 18:18, Kevin O'Connor ha scritto:
Change the multi-processor init code to trampoline into 32bit mode on
each of the additional processors. Implement an atomic lock so that
each processor performs its initialization serially.
Signed-off-by: Kevin O'Connor ke...@koconnor.net
---
Changed since v2:
* Use lock btsl instead of lock cmpxchgl as suggested by Paolo.
* Enable CPU caching on the APs
* Report the apic_id in debug messages for each AP
Reviewed-by: Paolo Bonzini pbonz...@redhat.com
---
Makefile| 3 +-
src/config.h| 1 +
src/fw/smp.c| 102
src/romlayout.S | 20 +++
src/util.h | 1 -
5 files changed, 73 insertions(+), 54 deletions(-)
diff --git a/Makefile b/Makefile
index 78b598e..fb4e683 100644
--- a/Makefile
+++ b/Makefile
@@ -29,7 +29,6 @@ LD32BIT_FLAG:=-melf_i386
# Source files
SRCBOTH=misc.c stacks.c output.c string.c x86.c block.c cdrom.c mouse.c kbd.c \
serial.c clock.c resume.c pnpbios.c vgahooks.c pcibios.c apm.c \
-fw/smp.c \
hw/pci.c hw/timer.c hw/rtc.c hw/dma.c hw/pic.c hw/ps2port.c hw/serialio.c \
hw/usb.c hw/usb-uhci.c hw/usb-ohci.c hw/usb-ehci.c \
hw/usb-hid.c hw/usb-msc.c hw/usb-uas.c \
@@ -41,7 +40,7 @@ SRC32FLAT=$(SRCBOTH) post.c memmap.c malloc.c pmm.c romfile.c
optionroms.c \
boot.c bootsplash.c jpeg.c bmp.c \
hw/ahci.c hw/pvscsi.c hw/usb-xhci.c hw/usb-hub.c \
fw/coreboot.c fw/lzmadecode.c fw/csm.c fw/biostables.c \
-fw/paravirt.c fw/shadow.c fw/pciinit.c fw/smm.c fw/mtrr.c fw/xen.c \
+fw/paravirt.c fw/shadow.c fw/pciinit.c fw/smm.c fw/smp.c fw/mtrr.c
fw/xen.c \
fw/acpi.c fw/mptable.c fw/pirtable.c fw/smbios.c fw/romfile_loader.c
SRC32SEG=string.c output.c pcibios.c apm.c stacks.c hw/pci.c hw/serialio.c
DIRS=src src/hw src/fw vgasrc
diff --git a/src/config.h b/src/config.h
index 6f1a5b9..6da067d 100644
--- a/src/config.h
+++ b/src/config.h
@@ -95,6 +95,7 @@
#define DEBUG_ISR_hwpic1 5
#define DEBUG_ISR_hwpic2 5
#define DEBUG_HDL_smi 9
+#define DEBUG_HDL_smp 1
#define DEBUG_HDL_pnp 1
#define DEBUG_HDL_pmm 1
#define DEBUG_HDL_pcibios 9
diff --git a/src/fw/smp.c b/src/fw/smp.c
index 38fe383..51c0cae 100644
--- a/src/fw/smp.c
+++ b/src/fw/smp.c
@@ -1,4 +1,4 @@
-// CPU count detection
+// QEMU multi-CPU initialization code
//
// Copyright (C) 2008 Kevin O'Connor ke...@koconnor.net
// Copyright (C) 2006 Fabrice Bellard
@@ -20,8 +20,8 @@
#define APIC_ENABLED 0x0100
-struct { u32 ecx, eax, edx; } smp_mtrr[32] VARFSEG;
-u32 smp_mtrr_count VARFSEG;
+static struct { u32 index; u64 val; } smp_mtrr[32];
+static u32 smp_mtrr_count;
void
wrmsr_smp(u32 index, u64 val)
@@ -31,52 +31,40 @@ wrmsr_smp(u32 index, u64 val)
warn_noalloc();
return;
}
-smp_mtrr[smp_mtrr_count].ecx = index;
-smp_mtrr[smp_mtrr_count].eax = val;
-smp_mtrr[smp_mtrr_count].edx = val 32;
+smp_mtrr[smp_mtrr_count].index = index;
+smp_mtrr[smp_mtrr_count].val = val;
smp_mtrr_count++;
}
-u32 CountCPUs VARFSEG;
u32 MaxCountCPUs;
+static u32 CountCPUs;
+u32 SMPLock __VISIBLE;
+u32 SMPStack __VISIBLE;
// 256 bits for the found APIC IDs
-u32 FoundAPICIDs[256/32] VARFSEG;
-extern void smp_ap_boot_code(void);
-ASM16(
- .global smp_ap_boot_code\n
-smp_ap_boot_code:\n
+static u32 FoundAPICIDs[256/32];
-// Setup data segment
- movw $ __stringify(SEG_BIOS) , %ax\n
- movw %ax, %ds\n
+void VISIBLE32FLAT
+handle_smp(void)
+{
+// Enable CPU caching
+setcr0(getcr0() ~(CR0_CD|CR0_NW));
+
+// Detect apic_id
+u32 eax, ebx, ecx, cpuid_features;
+cpuid(1, eax, ebx, ecx, cpuid_features);
+u8 apic_id = ebx24;
+dprintf(DEBUG_HDL_smp, handle_smp: apic_id=%d\n, apic_id);
// MTRR setup
- movl $smp_mtrr, %esi\n
- movl smp_mtrr_count, %ebx\n
-1:testl %ebx, %ebx\n
- jz 2f\n
- movl 0(%esi), %ecx\n
- movl 4(%esi), %eax\n
- movl 8(%esi), %edx\n
- wrmsr\n
- addl $12, %esi\n
- decl %ebx\n
- jmp 1b\n
-2:\n
-
-// get apic ID on EBX, set bit on FoundAPICIDs
- movl $1, %eax\n
- cpuid\n
- shrl $24, %ebx\n
- lock btsl %ebx, FoundAPICIDs\n
-
-// Increment the cpu counter
- lock incl CountCPUs\n
-
-// Halt the processor.
-1:hlt\n
- jmp 1b\n
-);
+int i;
+for (i=0; ismp_mtrr_count; i++)
+wrmsr(smp_mtrr[i].index, smp_mtrr[i].val);
+
+// Set bit on FoundAPICIDs
+FoundAPICIDs[apic_id/32] |= (1 (apic_id % 32));
+
+CountCPUs++;
+}
int apic_id_is_present(u8 apic_id)
{
@@ -104,15 +92,14 @@ smp_setup(void)
// mark the BSP initial APIC ID as found, too:
u8 apic_id = ebx24;
FoundAPICIDs[apic_id/32] |= (1 (apic_id % 32));
-
-// Init the counter.
-writel(CountCPUs, 1);
+CountCPUs = 1;
// Setup jump trampoline to counter code.
u64 old = *(u64*)BUILD_AP_BOOT_ADDR;
-// ljmpw $SEG_BIOS, $(smp_ap_boot_code -
Re: [SeaBIOS] problem building from Windows using msys
On Mon, Jun 02, 2014 at 05:27:23PM -0500, Scott Duplichan wrote: Kevin O'Connor [mailto:ke...@koconnor.net] wrote: ]Unfortunately, this would break builds where one specifies an OUT ]build directory that isn't a sub-directory of the source code. (That ]is, a build with make OUT=/a/b/c.) ] ]I've never tried building under Windows, and I'm not really sure how ]to help here. Does passing the CURDIR via the command-line (as in the ]patch below) improve things? ] ]-Kevin Well sure enough, this patch solves the problem. Thanks. Does the patch below also work? -Kevin --- a/Makefile +++ b/Makefile @@ -112,8 +112,8 @@ endif # Do a whole file compile by textually including all C code. define whole-compile @echo Compiling whole program $3 -$(Q)printf '$(foreach i,$2,#include $(CURDIR)/$i\n)' $3.tmp.c -$(Q)$(CC) $1 $(CFLAGSWHOLE) -c $3.tmp.c -o $3 +$(Q)printf '$(foreach i,$2,#include $i\n)' $3.tmp.c +$(Q)$(CC) -I. $1 $(CFLAGSWHOLE) -c $3.tmp.c -o $3 endef %.strip.o: %.o ___ SeaBIOS mailing list SeaBIOS@seabios.org http://www.seabios.org/mailman/listinfo/seabios
[SeaBIOS] [PATCH 0/4] Reduce use of .code16gcc
This is a gratuitous GCC-ism. For C code actually compiled with GCC we should be using -m16 where it's available (GCC 4.9+). And where the only thing marked with .code16gcc is explicit assembler code, we should just use .code16 and avoid letting the compiler make any of the assumptions that the difference affects. Which, in fact, we already do. (Once upon a time with ancient versions of gas, we needed to use .code16gcc because some instructions just wouldn't compile otherwise. That hasn't been true for a while though.) It still doesn't actually build with clang after this, but it's a bit closer. -- dwmw2 smime.p7s Description: S/MIME cryptographic signature ___ SeaBIOS mailing list SeaBIOS@seabios.org http://www.seabios.org/mailman/listinfo/seabios
[SeaBIOS] [PATCH 1/4] build: use -m16 where available instead of asm(.code16gcc)
GCC 4.9 and clang 3.5 support the -m16 option on the command line which supersedes the hackish .code16gcc assembler directive. Use it where possible. Signed-off-by: David Woodhouse david.woodho...@intel.com --- Makefile | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 78b598e..4c42124 100644 --- a/Makefile +++ b/Makefile @@ -62,13 +62,15 @@ COMMONCFLAGS := -I$(OUT) -Isrc -Os -MD -g \ COMMONCFLAGS += $(call cc-option,$(CC),-nopie,) COMMONCFLAGS += $(call cc-option,$(CC),-fno-stack-protector,) COMMONCFLAGS += $(call cc-option,$(CC),-fno-stack-protector-all,) +COMMA := , CFLAGS32FLAT := $(COMMONCFLAGS) -DMODE16=0 -DMODESEGMENT=0 -fomit-frame-pointer CFLAGSSEG := $(COMMONCFLAGS) -DMODESEGMENT=1 -fno-defer-pop \ $(call cc-option,$(CC),-fno-jump-tables,-DMANUAL_NO_JUMP_TABLE) \ $(call cc-option,$(CC),-fno-tree-switch-conversion,) CFLAGS32SEG := $(CFLAGSSEG) -DMODE16=0 -fomit-frame-pointer -CFLAGS16INC := $(CFLAGSSEG) -DMODE16=1 -Wa,src/code16gcc.s \ +CFLAGS16INC := $(CFLAGSSEG) -DMODE16=1 \ +$(call cc-option,$(CC),-m16,-Wa$(COMMA)src/code16gcc.s) \ $(call cc-option,$(CC),--param large-stack-frame=4,-fno-inline) CFLAGS16 := $(CFLAGS16INC) -fomit-frame-pointer -- 1.9.3 -- David WoodhouseOpen Source Technology Centre david.woodho...@intel.com Intel Corporation smime.p7s Description: S/MIME cryptographic signature ___ SeaBIOS mailing list SeaBIOS@seabios.org http://www.seabios.org/mailman/listinfo/seabios
[SeaBIOS] [PATCH 3/4] romlayout: Use .code16 not .code16gcc
There's no need to use .code16gcc where we are writing assembler code explicitly. It only affects word-size-ambiguous instructions, and we should just be explicit. And we are. Signed-off-by: David Woodhouse david.woodho...@intel.com --- src/romlayout.S | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/romlayout.S b/src/romlayout.S index 57e8bcc..9c2719e 100644 --- a/src/romlayout.S +++ b/src/romlayout.S @@ -21,7 +21,7 @@ // %edx = return location (in 32bit mode) // Clobbers: ecx, flags, segment registers, cr0, idt/gdt DECLFUNC transition32 -.code16gcc +.code16 transition32: movl %eax, %ecx @@ -102,7 +102,7 @@ transition16big: ljmpw $SEG32_MODE16BIG_CS, $1f -.code16gcc +.code16 1: // Disable protected mode movl %cr0, %eax @@ -145,7 +145,7 @@ __call16big: jmp transition16big // Make call. -.code16gcc +.code16 1: movl $_zonelow_seg, %edx// Adjust %ds, %ss, and %esp movl %edx, %ds movzwl StackSeg, %edx @@ -177,7 +177,7 @@ __call16big: // Far call a 16bit function from 16bit mode with a specified cpu register state // %eax = address of struct bregs, %edx = segment of struct bregs // Clobbers: %e[bc]x, %e[ds]i, flags -.code16gcc +.code16 DECLFUNC __farcall16 __farcall16: // Save %edx/%eax, %ebp @@ -372,7 +372,7 @@ entry_pcibios32: popfl lretl -.code16gcc +.code16 DECLFUNC entry_pcibios16 entry_pcibios16: ENTRY_ARG handle_pcibios @@ -421,7 +421,7 @@ entry_elf: movl $BUILD_STACK_ADDR, %esp ljmpl $SEG32_MODE32_CS, $_cfunc32flat_handle_post -.code16gcc +.code16 // UEFI Compatibility Support Module (CSM) entry point EXPORTFUNC entry_csm @@ -453,7 +453,7 @@ entry_csm: __csm_return: movl $1f, %edx jmp transition16big -.code16gcc +.code16 // Switch back to original stack 1: movzwl BREGS_code+2(%eax), %edx -- 1.9.3 -- David WoodhouseOpen Source Technology Centre david.woodho...@intel.com Intel Corporation smime.p7s Description: S/MIME cryptographic signature ___ SeaBIOS mailing list SeaBIOS@seabios.org http://www.seabios.org/mailman/listinfo/seabios
[SeaBIOS] [PATCH 4/4] vgaentry: Use .code16 not .code16gcc
There's no need to use .code16gcc where we are writing assembler code explicitly. It only affects word-size-ambiguous instructions, and we should just be explicit. And we are. Signed-off-by: David Woodhouse david.woodho...@intel.com --- vgasrc/vgaentry.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vgasrc/vgaentry.S b/vgasrc/vgaentry.S index 11197f1..3c2c885 100644 --- a/vgasrc/vgaentry.S +++ b/vgasrc/vgaentry.S @@ -15,7 +15,7 @@ / .section .rom.header -.code16gcc +.code16 .global _rom_header, _rom_header_size, _rom_header_checksum _rom_header: .word 0xaa55 -- 1.9.3 -- David WoodhouseOpen Source Technology Centre david.woodho...@intel.com Intel Corporation smime.p7s Description: S/MIME cryptographic signature ___ SeaBIOS mailing list SeaBIOS@seabios.org http://www.seabios.org/mailman/listinfo/seabios
[SeaBIOS] [PATCH 2/4] smm: Use .code16 not .code16gcc
There's no need to use .code16gcc where we are writing assembler code explicitly. It only affects word-size-ambiguous instructions, and we should just be explicit. And we are. Signed-off-by: David Woodhouse david.woodho...@intel.com --- src/fw/smm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/fw/smm.c b/src/fw/smm.c index 0f59f20..77e1e63 100644 --- a/src/fw/smm.c +++ b/src/fw/smm.c @@ -19,7 +19,7 @@ extern u8 smm_relocation_start, smm_relocation_end; ASM32FLAT( .global smm_relocation_start, smm_relocation_end\n - .code16gcc\n + .code16\n /* code to relocate SMBASE to 0xa */ smm_relocation_start:\n @@ -46,7 +46,7 @@ ASM32FLAT( extern u8 smm_code_start, smm_code_end; ASM32FLAT( .global smm_code_start, smm_code_end\n - .code16gcc\n + .code16\n smm_code_start:\n rsm\n smm_code_end:\n -- 1.9.3 -- David WoodhouseOpen Source Technology Centre david.woodho...@intel.com Intel Corporation smime.p7s Description: S/MIME cryptographic signature ___ SeaBIOS mailing list SeaBIOS@seabios.org http://www.seabios.org/mailman/listinfo/seabios
[SeaBIOS] [PATCH] build: Avoid absolute paths during whole-program compiling.
The build currently does a textual include of all files in order to use the -fwhole-compile optimization. Update it to use relative file paths instead of absolute file paths. This makes the section names in the resulting binary more readable. It also makes the build easier on some Windows hosts. Signed-off-by: Kevin O'Connor ke...@koconnor.net --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 78b598e..7c2b33c 100644 --- a/Makefile +++ b/Makefile @@ -112,8 +112,8 @@ endif # Do a whole file compile by textually including all C code. define whole-compile @echo Compiling whole program $3 -$(Q)printf '$(foreach i,$2,#include $(CURDIR)/$i\n)' $3.tmp.c -$(Q)$(CC) $1 $(CFLAGSWHOLE) -c $3.tmp.c -o $3 +$(Q)printf '$(foreach i,$2,#include $i\n)' $3.tmp.c +$(Q)$(CC) -I. $1 $(CFLAGSWHOLE) -c $3.tmp.c -o $3 endef %.strip.o: %.o -- 1.9.3 ___ SeaBIOS mailing list SeaBIOS@seabios.org http://www.seabios.org/mailman/listinfo/seabios
Re: [SeaBIOS] [PATCH 0/4] Reduce use of .code16gcc
On Tue, Jun 03, 2014 at 05:25:57PM +0100, David Woodhouse wrote: This is a gratuitous GCC-ism. For C code actually compiled with GCC we should be using -m16 where it's available (GCC 4.9+). And where the only thing marked with .code16gcc is explicit assembler code, we should just use .code16 and avoid letting the compiler make any of the assumptions that the difference affects. Which, in fact, we already do. (Once upon a time with ancient versions of gas, we needed to use .code16gcc because some instructions just wouldn't compile otherwise. That hasn't been true for a while though.) It still doesn't actually build with clang after this, but it's a bit closer. Thanks. Looks good to me. I updated the series to apply on top of my pending patches and added it to my queue: https://github.com/KevinOConnor/seabios/commits/testing -Kevin ___ SeaBIOS mailing list SeaBIOS@seabios.org http://www.seabios.org/mailman/listinfo/seabios
