Re: [SeaBIOS] [RFC PATCH v4 00/30] ACPI memory hotplug
> > > > IIRC q35 supports memory hotplug natively (picked up in some > > discussion). Is that correct? > > > From previous discussion I also understand that q35 supports native hotplug. > Sections 5.1 and 5.2 of the spec describe the MCH registers but the native > memory hotplug specifics are not yet clear to me. Any pointers from the > spec are welcome. Ping. Could anyone who's familiar with the q35 spec provide some pointers on native memory hotplug details in the spec? I see pcie hotplug registers but can't find memory hotplug interface details. If I am not mistaken, the spec is here: http://www.intel.com/design/chipsets/datashts/316966.htm Is the q35 memory hotplug support supposed to be an shpc-like interface geared towards memory slots instead of pci slots? thanks, - Vasilis ___ SeaBIOS mailing list SeaBIOS@seabios.org http://www.seabios.org/mailman/listinfo/seabios
Re: [SeaBIOS] [RFC PATCH v4 00/30] ACPI memory hotplug
Hi, > correct, only the number of channels and ranks(dimms) per channel has been > emulated so far (2 channels of 4 dimms each). So it is still paravirtual > memory > hotplug, not native. Native support still needs to be worked on. Ok. >> I think the paravirtual memory hotplug controller should be a PCI device >> (which we then can add as function to the chipset). Having some fixed >> magic addresses is bad. > > ok, so in your opinion a pci-based hotplug controller sounds better than > adding > acpi ports to piix4 or ich9? > > Magic acpi_ich9 ports can be avoided if q35 native support is implemented. Yes. We should go that route for q35. > For > i440fx/piix4 it was discussed and more or less decided we would only support > a paravirtual way of memory hotplug. Sure, there is no other way to do it. It is probably a good idea to model piix4 paravirtual to work simliar to q35 native. > In the description. I meant "paravirtual memory bus" to describe a memory bus > with unlimited number of dimm devices. But the "hotplug control" has always > been acpi-based so far and not a pci device. It still can (and should) be acpi-based. It is just that: (a) Instead of using get_system_io() as parent memory region you use create a pci device and place the memory region in one of the PCI bars. (b) Instead of using OperationRegion($name, SystemIO, $magicaddress) you use OperationRegion($name, PciBarTarget, ...) to access the registers. cheers, Gerd ___ SeaBIOS mailing list SeaBIOS@seabios.org http://www.seabios.org/mailman/listinfo/seabios
Re: [SeaBIOS] [RFC PATCH v4 00/30] ACPI memory hotplug
Hi, On Wed, Dec 19, 2012 at 08:27:36AM +0100, Gerd Hoffmann wrote: > Hi, > > > - multiple memory buses can be registered. Memory buses of the real > > hw/chipset > > or a paravirtual memory bus can be added. > > IIRC q35 supports memory hotplug natively (picked up in some > discussion). Is that correct? > > What does the code emulate? It doesn't look like it emulates q35 memory > hotplug ... correct, only the number of channels and ranks(dimms) per channel has been emulated so far (2 channels of 4 dimms each). So it is still paravirtual memory hotplug, not native. Native support still needs to be worked on. >From previous discussion I also understand that q35 supports native hotplug. Sections 5.1 and 5.2 of the spec describe the MCH registers but the native acpi-memory hotplug specifics are not yet clear to me. Any pointers from the spec are welcome. > > I think the paravirtual memory hotplug controller should be a PCI device > (which we then can add as function to the chipset). Having some fixed > magic addresses is bad. ok, so in your opinion a pci-based hotplug controller sounds better than adding acpi ports to piix4 or ich9? Magic acpi_ich9 ports can be avoided if q35 native support is implemented. For i440fx/piix4 it was discussed and more or less decided we would only support a paravirtual way of memory hotplug. In the description. I meant "paravirtual memory bus" to describe a memory bus with unlimited number of dimm devices. But the "hotplug control" has always been acpi-based so far and not a pci device. thanks, - Vasilis ___ SeaBIOS mailing list SeaBIOS@seabios.org http://www.seabios.org/mailman/listinfo/seabios
Re: [SeaBIOS] [RFC PATCH v4 00/30] ACPI memory hotplug
Hi, > - multiple memory buses can be registered. Memory buses of the real hw/chipset > or a paravirtual memory bus can be added. IIRC q35 supports memory hotplug natively (picked up in some discussion). Is that correct? What does the code emulate? It doesn't look like it emulates q35 memory hotplug ... I think the paravirtual memory hotplug controller should be a PCI device (which we then can add as function to the chipset). Having some fixed magic addresses is bad. [ btw: same goes for ACPI PCI hotplug, that is hardly fixable without breaking compatibility though, for q35 we should be able to do better ]. cheers, Gerd ___ SeaBIOS mailing list SeaBIOS@seabios.org http://www.seabios.org/mailman/listinfo/seabios
