Re: mc13xxx-core, support for i2c, V4
Le samedi, 12 février 2011 09.40:35, Grant Likely a écrit : > On Tue, Jan 04, 2011 at 04:34:55PM +1100, Marc Reilly wrote: > > Hi, > > > > These patches add i2c support for the mc13xxx-core drive. For v4 I've > > tried to take in all previous comments, hopefully making it better to > > follow, and bisectable. > > This series looks okay to me. Since this is audio drivers, I expect > that it would best be taken via the ASoC tree? Have you sent it to > Mark Brown and the ALSA list for review? AFAIK the audio part of the mc13783 has still not been merged. Regards, Philippe -- The ultimate all-in-one performance toolkit: Intel(R) Parallel Studio XE: Pinpoint memory and threading errors before they happen. Find and fix more than 250 security defects in the development cycle. Locate bottlenecks in serial and parallel code that limit performance. http://p.sf.net/sfu/intel-dev2devfeb ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: mc13xxx-core, support for i2c, V4
On Mon, Feb 14, 2011 at 11:21:34AM +0100, Philippe R?tornaz wrote: > AFAIK the audio part of the mc13783 has still not been merged. No, it hasn't. Sacha posted something ages ago but it had a lot of problems and I've not seen any subsequent spins. -- The ultimate all-in-one performance toolkit: Intel(R) Parallel Studio XE: Pinpoint memory and threading errors before they happen. Find and fix more than 250 security defects in the development cycle. Locate bottlenecks in serial and parallel code that limit performance. http://p.sf.net/sfu/intel-dev2devfeb ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
RE: [PATCH 0/1] Adding intel_mid_ssp_spi driver : 01/27/2011
OK got it. Thanks. >-Original Message- >From: Grant Likely [mailto:glik...@secretlab.ca] On Behalf Of Grant >Likely >Sent: Saturday, February 12, 2011 1:19 AM >To: Gorby, Russ >Cc: David Brownell; open list:SPI SUBSYSTEM; open list >Subject: Re: [PATCH 0/1] Adding intel_mid_ssp_spi driver : 01/27/2011 > >On Wed, Feb 02, 2011 at 01:01:51PM -0800, Russ Gorby wrote: >> Hello SPI maintainers, >> I am sending a patch for the (new) intel_mid_ssp_spi driver for >> consideration for inclusion in the Linux Kernel. This is a SPI master >> controller driver that is being used for the intel MID platform >(Medfield). >> It uses the on-board Bulverde SSP controller configured for SPI >(spibus #3) >> running at 25Mhz. > >Hi Russ, > >Just for future reference, when you're only sending one patch, please >put your notes into the patch description itself, or immediately after >the --- line. No need for a cover letter like this one. > >Thanks, >g. -- The ultimate all-in-one performance toolkit: Intel(R) Parallel Studio XE: Pinpoint memory and threading errors before they happen. Find and fix more than 250 security defects in the development cycle. Locate bottlenecks in serial and parallel code that limit performance. http://p.sf.net/sfu/intel-dev2devfeb ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
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[PATCH] spi: add support for SuperH SPI
The SH7757 has SPI0 module. This patch supports it.
Signed-off-by: Yoshihiro Shimoda
---
drivers/spi/Kconfig |6 +
drivers/spi/Makefile |1 +
drivers/spi/spi_sh.c | 547 ++
3 files changed, 554 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/spi_sh.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index bb233a9..1532d2c 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -330,6 +330,12 @@ config SPI_SH_MSIOF
help
SPI driver for SuperH MSIOF blocks.
+config SPI_SH
+ tristate "SuperH SPI controller"
+ depends on SUPERH
+ help
+ SPI driver for SuperH SPI blocks.
+
config SPI_SH_SCI
tristate "SuperH SCI SPI controller"
depends on SUPERH
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 86d1b5f..068465f 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_SPI_TXX9)+= spi_txx9.o
obj-$(CONFIG_SPI_XILINX) += xilinx_spi.o
obj-$(CONFIG_SPI_SH_SCI) += spi_sh_sci.o
obj-$(CONFIG_SPI_SH_MSIOF) += spi_sh_msiof.o
+obj-$(CONFIG_SPI_SH) += spi_sh.o
obj-$(CONFIG_SPI_STMP3XXX) += spi_stmp.o
obj-$(CONFIG_SPI_NUC900) += spi_nuc900.o
diff --git a/drivers/spi/spi_sh.c b/drivers/spi/spi_sh.c
new file mode 100644
index 000..247ef0b
--- /dev/null
+++ b/drivers/spi/spi_sh.c
@@ -0,0 +1,547 @@
+/*
+ * SH SPI bus driver
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ *
+ * Based on pxa2xx_spi.c:
+ * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DRIVER_VERSION "2011-02-02"
+
+#define SPI_SH_TBR 0x00
+#define SPI_SH_RBR 0x00
+#define SPI_SH_CR1 0x08
+#define SPI_SH_CR2 0x10
+#define SPI_SH_CR3 0x18
+#define SPI_SH_CR4 0x20
+#define SPI_SH_CR5 0x28
+
+/* CR1 */
+#define SPI_SH_TBE 0x80
+#define SPI_SH_TBF 0x40
+#define SPI_SH_RBE 0x20
+#define SPI_SH_RBF 0x10
+#define SPI_SH_PFONRD 0x08
+#define SPI_SH_SSDB0x04
+#define SPI_SH_SSD 0x02
+#define SPI_SH_SSA 0x01
+
+/* CR2 */
+#define SPI_SH_RSTF0x80
+#define SPI_SH_LOOPBK 0x40
+#define SPI_SH_CPOL0x20
+#define SPI_SH_CPHA0x10
+#define SPI_SH_L1M00x08
+
+/* CR3 */
+#define SPI_SH_MAX_BYTE0xFF
+
+/* CR4 */
+#define SPI_SH_TBEI0x80
+#define SPI_SH_TBFI0x40
+#define SPI_SH_RBEI0x20
+#define SPI_SH_RBFI0x10
+#define SPI_SH_WPABRT 0x04
+#define SPI_SH_SSS 0x01
+
+/* CR8 */
+#define SPI_SH_P1L00x80
+#define SPI_SH_PP1L0 0x40
+#define SPI_SH_MUXI0x20
+#define SPI_SH_MUXIRQ 0x10
+
+#define SPI_SH_FIFO_SIZE 32
+#define SPI_SH_SEND_TIMEOUT(3 * HZ)
+#define SPI_SH_RECEIVE_TIMEOUT (HZ >> 3)
+
+#undef DEBUG
+
+struct spi_sh_data {
+ void __iomem *addr;
+ int irq;
+ struct spi_master *master;
+ struct list_head queue;
+ struct workqueue_struct *workqueue;
+ struct work_struct ws;
+ unsigned long cr1;
+ wait_queue_head_t wait;
+ spinlock_t lock;
+};
+
+static void spi_sh_write(struct spi_sh_data *ss, unsigned long data,
+unsigned long offset)
+{
+ writel(data, ss->addr + offset);
+}
+
+static unsigned long spi_sh_read(struct spi_sh_data *ss, unsigned long offset)
+{
+ return readl(ss->addr + offset);
+}
+
+static void spi_sh_set_bit(struct spi_sh_data *ss, unsigned long val,
+ unsigned long offset)
+{
+ unsigned long tmp;
+
+ tmp = spi_sh_read(ss, offset);
+ tmp |= val;
+ spi_sh_write(ss, tmp, offset);
+}
+
+static void spi_sh_clear_bit(struct spi_sh_data *ss, unsigned long val,
+ unsigned long offset)
+{
+ unsigned long tmp;
+
+ tmp = spi_sh_read(ss, offset);
+ tmp &= ~val;
+ spi_sh_write
Re: [PATCH 1/8] Intel SPI master controller driver for the Medfield platform
On Wed, Feb 09, 2011 at 10:07:02AM +, Alan Cox wrote:
> From: Russ Gorby
>
> SPI master controller driver for the Intel MID platform Medfield
> This driver uses the Penwell SSP controller and configures it to
> be a SPI device (spibus 3). This bus supports a single device -
> the 3G SPI modem that can operate up to 25Mhz.
>
> Signed-off-by: Russ Gorby
> Signed-off-by: Alan Cox
Heh, I think I should have replied to this one instead of my earlier
patch, but I'll reply here too for completeness. On brief glance it
looks like some of my comments no longer apply in this version. Also,
I'm not being as thorough, so most of the comments now will probably
be pretty surface issues.
g.
> ---
>
> drivers/spi/Kconfig |7
> drivers/spi/Makefile|1
> drivers/spi/intel_mid_ssp_spi.c | 1507
> +++
> drivers/spi/intel_mid_ssp_spi_def.h | 139 +++
Please rename to spi_intel_mid_ssp.c. I'm asking for all new spi
drivers to use spi_ as a prefix.
> 4 files changed, 1654 insertions(+), 0 deletions(-)
> create mode 100644 drivers/spi/intel_mid_ssp_spi.c
> create mode 100644 drivers/spi/intel_mid_ssp_spi_def.h
>
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index bb233a9..60ba339 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -178,6 +178,13 @@ config SPI_IMX
> This enables using the Freescale i.MX SPI controllers in master
> mode.
>
> +config SPI_INTEL_MID_SSP
> + tristate "SSP SPI controller driver for Intel Medfield platform"
> + depends on SPI_MASTER && INTEL_MID_DMAC
> + help
> + This is the SPI master controller driver for the Intel
> + Medfield MID platform.
> +
> config SPI_LM70_LLP
> tristate "Parallel port adapter for LM70 eval board (DEVELOPMENT)"
> depends on PARPORT && EXPERIMENTAL
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 86d1b5f..c64deb9 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -50,6 +50,7 @@ obj-$(CONFIG_SPI_SH_SCI)+= spi_sh_sci.o
> obj-$(CONFIG_SPI_SH_MSIOF) += spi_sh_msiof.o
> obj-$(CONFIG_SPI_STMP3XXX) += spi_stmp.o
> obj-$(CONFIG_SPI_NUC900) += spi_nuc900.o
> +obj-$(CONFIG_SPI_INTEL_MID_SSP) += intel_mid_ssp_spi.o
>
> # special build for s3c24xx spi driver with fiq support
> spi_s3c24xx_hw-y := spi_s3c24xx.o
> diff --git a/drivers/spi/intel_mid_ssp_spi.c b/drivers/spi/intel_mid_ssp_spi.c
> new file mode 100644
> index 000..19c62bc
> --- /dev/null
> +++ b/drivers/spi/intel_mid_ssp_spi.c
> @@ -0,0 +1,1507 @@
> +/*
> + * intel_mid_ssp_spi.c - Penwell SPI master controller driver
> + * based on pxa2xx.c
> + *
> + * Copyright (C) Intel 2010
> + * Ken Mills
> + * Russ Gorby
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
> + * USA
> + *
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include "intel_mid_ssp_spi_def.h"
No need for the separate include since there are no other users. Just
roll the contents of the header into the .c file.
> +
> +#define DRIVER_NAME "intel_mid_ssp_spi"
> +#define PCI_DMAC_MAXDI 2047
> +#define PCI_DMAC_ID 0x0827
> +/* PM QoS define */
> +#define MIN_EXIT_LATENCY 20
> +
> +#define TESTMODE_COMMON_MASK 0x00ff
> +#define TESTMODE_PRIV_MASK 0xff00
> +#define TESTMODE_ENABLE_DMA 0x01
> +#define TESTMODE_ENABLE_POLL 0x02
> +#define TESTMODE_ENABLE_LOOPBACK 0x04
> +#define TESTMODE_ENABLE_INTR 0x08
> +#define TESTMODE(x) (testmode & x)
> +static unsigned int testmode = (TESTMODE_ENABLE_DMA | TESTMODE_ENABLE_POLL);
> +
> +module_param(testmode, uint, S_IRUGO|S_IWUSR);
> +MODULE_PARM_DESC(testmode, "supply test mode bits");
> +
> +MODULE_AUTHOR("Intel");
> +MODULE_DESCRIPTION("Penwell SPI3 Master Contoller");
> +MODULE_LICENSE("GPL");
> +
> +#define RX_THRESH_DFLT 8
> +#define TX_THRESH_DFLT 8
> +#define TIMOUT_DFLT 1000
> +
> +/*
> + * For testing SSCR1 changes that require SSP restart, basically
> + * everything except the service and interrupt enables
> + */
> +
> +#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
> +
Re: [PATCH 2/8] intel_mid_ssp_spi: Re-introduce quirks fields
On Wed, Feb 09, 2011 at 10:07:30AM +, Alan Cox wrote:
> From: Alan Cox
>
> This adds the quirks field to the driver and the flags. We don't yet
> implement any of them so we don't confuse the driver.
>
> Signed-off-by: Alan Cox
Other than minor point, looks fine. Looks like it should be squashed
into patch #1.
g.
> ---
>
> drivers/spi/intel_mid_ssp_spi.c | 11 ++-
> 1 files changed, 10 insertions(+), 1 deletions(-)
>
>
> diff --git a/drivers/spi/intel_mid_ssp_spi.c b/drivers/spi/intel_mid_ssp_spi.c
> index 19c62bc..f201edd 100644
> --- a/drivers/spi/intel_mid_ssp_spi.c
> +++ b/drivers/spi/intel_mid_ssp_spi.c
> @@ -125,6 +125,15 @@ struct driver_data {
> /* SPI framework hookup */
> struct spi_master *master;
>
> + /* Chip specific quirks */
> + int quirks;
> +#define QUIRKS_PLATFORM_MRST 1
> +#define QUIRKS_SRAM_ADDITIONAL_CPY 2
> +#define QUIRKS_USE_PM_QOS4
> +#define QUIRKS_BIT_BANGING 8
> +#define QUIRKS_SPI_SLAVE_CLOCK_MODE 16
> +#define QUIRKS_PLATFORM_MDFL 32
> +
> /* SSP register addresses */
> unsigned long paddr;
> void __iomem *ioaddr;
> @@ -137,7 +146,6 @@ struct driver_data {
> u32 clear_sr;
> u32 mask_sr;
>
> -
unrelated whitespace change.
> /* Current message transfer state info */
> struct tasklet_struct poll_transfer;
> struct spi_message *cur_msg;
> @@ -1163,6 +1171,7 @@ static int intel_mid_ssp_spi_probe(struct pci_dev *pdev,
> }
>
> drv_data = spi_master_get_devdata(master);
> + drv_data->quirks = ent->driver_data;
> drv_data->master = master;
> drv_data->pdev = pdev;
> drv_data->pwrstate = PWRSTATE_ON;
>
--
The ultimate all-in-one performance toolkit: Intel(R) Parallel Studio XE:
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Find and fix more than 250 security defects in the development cycle.
Locate bottlenecks in serial and parallel code that limit performance.
http://p.sf.net/sfu/intel-dev2devfeb
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Re: [PATCH v9] spi: New driver for Altera SPI
Dear Ryan,
On 02/14/2011 10:20 AM, Ryan Mallon wrote:
> On 02/14/2011 03:10 PM, Thomas Chou wrote:
>> This patch adds a new SPI driver to support the Altera SOPC Builder
>> SPI component. It uses the bitbanging library.
>>
>> Signed-off-by: Thomas Chou
>> ---
>
>> +struct altera_spi {
>> +/* bitbang has to be first */
>> +struct spi_bitbang bitbang;
>
> Is this still true? I had a quick look and can't see anything which
> relies on spi_bitbang being the first entry. Things like this should be
> using container_of so that position in the struct is irrelevant.
>
> ~Ryan
>
Yes, sadly true. This is due to the implementation of the bitbanging
library, spi_bitbang.c, which assumes the struct spi_bitbang is the
first of drvdata. Though it could be changed in the future (beyond this
little driver), every bitbanging library user has to follow this for now.
Best regards,
Thomas
--
The ultimate all-in-one performance toolkit: Intel(R) Parallel Studio XE:
Pinpoint memory and threading errors before they happen.
Find and fix more than 250 security defects in the development cycle.
Locate bottlenecks in serial and parallel code that limit performance.
http://p.sf.net/sfu/intel-dev2devfeb
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