Re: [PATCH v3] SPI: add CSR SiRFprimaII SPI controller driver
On Thu, Feb 09, 2012 at 12:10:46AM +0800, Barry Song wrote:
> From: Zhiwu Song
>
> CSR SiRFprimaII has two SPIs (SPI0 and SPI1). Features:
> * Master and slave modes
> * 8-/12-/16-/32-bit data unit
> * 256 bytes receive data FIFO and 256 bytes transmit data FIFO
> * Multi-unit frame
> * Configurable SPI_EN (chip select pin) active state
> * Configurable SPI_CLK polarity
> * Configurable SPI_CLK phase
> * Configurable MSB/LSB first
>
> Signed-off-by: Zhiwu Song
> Signed-off-by: Barry Song
> ---
> -v3:
> add missed SIRFSOC_SPI_ prefix before macros for registers;
> move writel/readl into tx/rx word functions;
> fix some other coding styles Grant pointed out;
> add missed device tree binding file.
>
> Documentation/devicetree/bindings/spi/spi_sirf.txt | 14 +
> drivers/spi/Kconfig|7 +
> drivers/spi/Makefile |1 +
> drivers/spi/spi-sirf.c | 665
>
> include/linux/spi/spi-sirf.h | 27 +
> 5 files changed, 714 insertions(+), 0 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/spi/spi_sirf.txt
> create mode 100644 drivers/spi/spi-sirf.c
> create mode 100644 include/linux/spi/spi-sirf.h
>
> diff --git a/Documentation/devicetree/bindings/spi/spi_sirf.txt
> b/Documentation/devicetree/bindings/spi/spi_sirf.txt
> new file mode 100644
> index 000..f7a58aa
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/spi_sirf.txt
> @@ -0,0 +1,14 @@
> +* CSR SiRFprimaII Serial Peripheral Interface
> +
> +Required properties:
> +- compatible : Should be "sirf,prima2-spi"
> +- reg : Offset and length of the register set for the device
> +- interrupts : Should contain SPI interrupt
> +
> +Example:
> +
> +spi0: spi@b00d {
> + compatible = "sirf,prima2-spi";
> + reg = <0xb00d 0x1>;
> + interrupts = <15>;
> +};
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index 3f9a47e..8311cc2 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -324,6 +324,13 @@ config SPI_SH_SCI
> help
> SPI driver for SuperH SCI blocks.
>
> +config SPI_SIRF
> +tristate "CSR SiRFprimaII SPI controller"
> + depends on ARCH_PRIMA2
> + select SPI_BITBANG
> + help
> + SPI driver for CSR SiRFprimaII SoCs
> +
> config SPI_STMP3XXX
> tristate "Freescale STMP37xx/378x SPI/SSP controller"
> depends on ARCH_STMP3XXX && SPI_MASTER
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 61c3261..e919846 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -51,6 +51,7 @@ obj-$(CONFIG_SPI_S3C64XX) += spi-s3c64xx.o
> obj-$(CONFIG_SPI_SH) += spi-sh.o
> obj-$(CONFIG_SPI_SH_MSIOF) += spi-sh-msiof.o
> obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o
> +obj-$(CONFIG_SPI_SIRF) += spi-sirf.o
> obj-$(CONFIG_SPI_STMP3XXX) += spi-stmp.o
> obj-$(CONFIG_SPI_TEGRA) += spi-tegra.o
> obj-$(CONFIG_SPI_TI_SSP) += spi-ti-ssp.o
> diff --git a/drivers/spi/spi-sirf.c b/drivers/spi/spi-sirf.c
> new file mode 100644
> index 000..6f326cb
> --- /dev/null
> +++ b/drivers/spi/spi-sirf.c
> @@ -0,0 +1,665 @@
> +/*
> + * SPI bus driver for CSR SiRFprimaII
> + *
> + * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group
> company.
> + *
> + * Licensed under GPLv2 or later.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define DRIVER_NAME "sirfsoc_spi"
> +
> +#define SIRFSOC_SPI_CTRL 0x
> +#define SIRFSOC_SPI_CMD 0x0004
> +#define SIRFSOC_SPI_TX_RX_EN 0x0008
> +#define SIRFSOC_SPI_INT_EN 0x000C
> +#define SIRFSOC_SPI_INT_STATUS 0x0010
> +#define SIRFSOC_SPI_TX_DMA_IO_CTRL 0x0100
> +#define SIRFSOC_SPI_TX_DMA_IO_LEN0x0104
> +#define SIRFSOC_SPI_TXFIFO_CTRL 0x0108
> +#define SIRFSOC_SPI_TXFIFO_LEVEL_CHK 0x010C
> +#define SIRFSOC_SPI_TXFIFO_OP0x0110
> +#define SIRFSOC_SPI_TXFIFO_STATUS0x0114
> +#define SIRFSOC_SPI_TXFIFO_DATA 0x0118
> +#define SIRFSOC_SPI_RX_DMA_IO_CTRL 0x0120
> +#define SIRFSOC_SPI_RX_DMA_IO_LEN0x0124
> +#define SIRFSOC_SPI_RXFIFO_CTRL 0x0128
> +#define SIRFSOC_SPI_RXFIFO_LEVEL_CHK 0x012C
> +#define SIRFSOC_SPI_RXFIFO_OP0x0130
> +#define SIRFSOC_SPI_RXFIFO_STATUS0x0134
> +#define SIRFSOC_SPI_RXFIFO_DATA 0x0138
> +#define SIRFSOC_SPI_DUMMY_DELAY_CTL 0x0144
> +
> +/* SPI CTRL register defines */
> +#define SIRFSOC_SPI_SLV_MODE BIT(16)
> +#define SIRFSOC_SPI_CMD_MODE BIT(17)
> +#define SIRFSOC_SPI_CS_IO_OUTBIT(18)
> +#define SIRFSOC_SPI_CS_IO_MODE BIT(19)
> +#define SIRFSOC_SPI_CLK_IDLE_
Re: [PATCH RESEND] intel_mid_ssp_spi: Moorestown and Medfield SPI for SSP devices
On Wed, Feb 08, 2012 at 10:41:10AM +, Alan Cox wrote:
> From: Mathieu SOULARD
>
> This driver is a fusion of various internal drivers into a single
> driver for the SPI slave/master on the Intel Moorestown and Medfield
> SSP devices.
>
> Signed-off-by: Mathieu SOULARD
> [Queueing and runtime pm added]
> Signed-off-by: Kristen Carlson Accardi
> [Ported to the -next tree DMA engine]
> Signed-off-by: Alan Cox
> ---
>
> drivers/spi/Kconfig |8
> drivers/spi/Makefile|2
> drivers/spi/spi-intel-mid-ssp.c | 1426
> +++
> drivers/spi/spi-intel-mid-ssp.h | 308
If this is merging several of the drivers, what is the plan for the existing
SPI_DESIGNWARE and SPI_TOPCLIFF_PCH drivers? Or are those for different
devices?
...
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 61c3261..e81757a 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -58,4 +58,4 @@ obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x0.o
> obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o
> obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
> obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o
> -
> +obj-$(CONFIG_SPI_INTEL_MID_SSP) += spi-intel-mid-ssp.o
I'm trying to keep this list alphabetized.
...
> +#ifdef DUMP_RX
> +static void dump_trailer(const struct device *dev, char *buf, int len, int
> sz)
> +{
> + int tlen1 = (len < sz ? len : sz);
> + int tlen2 = ((len - sz) > sz) ? sz : (len - sz);
> + unsigned char *p;
> + static char msg[MAX_SPI_TRANSFER_SIZE];
> +
> + memset(msg, '\0', sizeof(msg));
> + p = buf;
> + while (p < buf + tlen1)
> + sprintf(msg, "%s%02x", msg, (unsigned int)*p++);
> +
> + if (tlen2 > 0) {
> + sprintf(msg, "%s .", msg);
> + p = (buf+len) - tlen2;
> + while (p < buf + len)
> + sprintf(msg, "%s%02x", msg, (unsigned int)*p++);
> + }
> +
> + dev_info(dev, "DUMP: %p[0:%d ... %d:%d]:%s", buf, tlen1 - 1,
> +len-tlen2, len - 1, msg);
> +}
> +#endif
Yet another hex dump debug utility function? What about lib/hexdump.c?
...
> diff --git a/drivers/spi/spi-intel-mid-ssp.h b/drivers/spi/spi-intel-mid-ssp.h
> new file mode 100644
> index 000..11fad57
> --- /dev/null
> +++ b/drivers/spi/spi-intel-mid-ssp.h
How much of this stuff is actually needed in a .h file? If it is only used
by the .c file, then I want it moved there.
> @@ -0,0 +1,308 @@
> +/*
> + * Copyright (C) Intel 2009
> + * Ken Mills
> + * Sylvain Centelles
> + *
> + * ~~
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
> + *
> + * ~~
> + *
> + */
> +#ifndef SPI_INTEL_MID_SSP_H_
> +#define SPI_INTEL_MID_SSP_H_
> +
> +#define PCI_MRST_DMAC1_ID0x0814
> +#define PCI_MDFL_DMAC1_ID0x0827
> +
> +#define SSP_NOT_SYNC 0x40
> +#define MAX_SPI_TRANSFER_SIZE 8192
> +#define MAX_BITBANGING_LOOP 1
> +#define SPI_FIFO_SIZE 16
> +
> +/* PM QoS define */
> +#define MIN_EXIT_LATENCY 20
> +
> +/* SSP assignement configuration from PCI config */
> +#define SSP_CFG_GET_MODE(ssp_cfg)((ssp_cfg) & 0x07)
> +#define SSP_CFG_GET_SPI_BUS_NB(ssp_cfg) (((ssp_cfg) >> 3) & 0x07)
> +#define SSP_CFG_IS_SPI_SLAVE(ssp_cfg)((ssp_cfg) & 0x40)
> +#define SSP_CFG_SPI_MODE_ID 1
> +/* adid field offset is 6 inside the vendor specific capability */
> +#define VNDR_CAPABILITY_ADID_OFFSET 6
> +
> +/* Driver's quirk flags */
> +/* This workarround bufferizes data in the audio fabric SDRAM from */
> +/* where the DMA transfers will operate. Should be enabled only for */
> +/* SPI slave mode. */
> +#define QUIRKS_DMA_USE_NO_TRAIL 2
> +/* If set, the driver will use PM_QOS to reduce the latency */
> +/* introduced by the deeper C-states which may produce over/under */
> +/* run issues. Must be used in slave mode. In master mode, the */
> +/* latency is not critical, but setting this workarround may */
> +/* improve the SPI throughput.
[PATCH 3/3] spi/atmel: add DT support
the atmel_spi use only gpio for chip select
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
Cc: devicetree-disc...@lists.ozlabs.org
Cc: spi-devel-general@lists.sourceforge.net
---
.../devicetree/bindings/spi/spi_atmel.txt |6 ++
drivers/spi/spi-atmel.c| 12 +++-
2 files changed, 17 insertions(+), 1 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/spi_atmel.txt
diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt
b/Documentation/devicetree/bindings/spi/spi_atmel.txt
new file mode 100644
index 000..7ec3d8d
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi_atmel.txt
@@ -0,0 +1,6 @@
+Atmel SPI device
+
+Required properties:
+- compatible : should be "atmel,at91rm9200-spi".
+- reg: Address and length of the register set for the device
+- interrupts: Should contain macb interrupt
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 16d6a83..7bcd11f 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
#include
#include
@@ -938,7 +939,7 @@ static int __devinit atmel_spi_probe(struct platform_device
*pdev)
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
master->bus_num = pdev->id;
- master->num_chipselect = 4;
+ master->num_chipselect = master->dev.of_node ? 0 : 4;
master->setup = atmel_spi_setup;
master->transfer = atmel_spi_transfer;
master->cleanup = atmel_spi_cleanup;
@@ -1064,11 +1065,20 @@ static int atmel_spi_resume(struct platform_device
*pdev)
#defineatmel_spi_resumeNULL
#endif
+#if defined(CONFIG_OF)
+static const struct of_device_id atmel_spi_dt_ids[] = {
+ { .compatible = "atmel,at91rm9200-spi" },
+ { /* sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
+#endif
static struct platform_driver atmel_spi_driver = {
.driver = {
.name = "atmel_spi",
.owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(atmel_spi_dt_ids),
},
.suspend= atmel_spi_suspend,
.resume = atmel_spi_resume,
--
1.7.7
--
Virtualization & Cloud Management Using Capacity Planning
Cloud computing makes use of virtualization - but cloud computing
also focuses on allowing computing to be delivered as a service.
http://www.accelacomm.com/jaw/sfnl/114/51521223/
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH 1/3] spi: move master of_node init to spi_alloc_master
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
Cc: devicetree-disc...@lists.ozlabs.org
Cc: spi-devel-general@lists.sourceforge.net
---
drivers/spi/spi-altera.c |3 ---
drivers/spi/spi-fsl-lib.c |1 -
drivers/spi/spi-imx.c |1 -
drivers/spi/spi-mpc512x-psc.c |1 -
drivers/spi/spi-mpc52xx-psc.c |1 -
drivers/spi/spi-mpc52xx.c |1 -
drivers/spi/spi-oc-tiny.c |1 -
drivers/spi/spi-ppc4xx.c |1 -
drivers/spi/spi-pxa2xx-pci.c |1 -
drivers/spi/spi-pxa2xx.c |1 -
drivers/spi/spi-tegra.c |1 -
drivers/spi/spi-xilinx.c |1 -
drivers/spi/spi.c |1 +
13 files changed, 1 insertions(+), 14 deletions(-)
diff --git a/drivers/spi/spi-altera.c b/drivers/spi/spi-altera.c
index c00d00e..ac6badc 100644
--- a/drivers/spi/spi-altera.c
+++ b/drivers/spi/spi-altera.c
@@ -270,9 +270,6 @@ static int __devinit altera_spi_probe(struct
platform_device *pdev)
if (err)
goto exit;
}
- /* find platform data */
- if (!platp)
- hw->bitbang.master->dev.of_node = pdev->dev.of_node;
/* register our spi controller */
err = spi_bitbang_start(&hw->bitbang);
diff --git a/drivers/spi/spi-fsl-lib.c b/drivers/spi/spi-fsl-lib.c
index 2674fad..810aa01 100644
--- a/drivers/spi/spi-fsl-lib.c
+++ b/drivers/spi/spi-fsl-lib.c
@@ -133,7 +133,6 @@ int mpc8xxx_spi_probe(struct device *dev, struct resource
*mem,
master->transfer = mpc8xxx_spi_transfer;
master->cleanup = mpc8xxx_spi_cleanup;
- master->dev.of_node = dev->of_node;
mpc8xxx_spi = spi_master_get_devdata(master);
mpc8xxx_spi->dev = dev;
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index c6e697f..bebcd01 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -860,7 +860,6 @@ static int __devinit spi_imx_probe(struct platform_device
*pdev)
spi_imx->devtype_data->intctrl(spi_imx, 0);
- master->dev.of_node = pdev->dev.of_node;
ret = spi_bitbang_start(&spi_imx->bitbang);
if (ret) {
dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c
index 4c63f77..583d0c5 100644
--- a/drivers/spi/spi-mpc512x-psc.c
+++ b/drivers/spi/spi-mpc512x-psc.c
@@ -441,7 +441,6 @@ static int __devinit mpc512x_psc_spi_do_probe(struct device
*dev, u32 regaddr,
master->setup = mpc512x_psc_spi_setup;
master->transfer = mpc512x_psc_spi_transfer;
master->cleanup = mpc512x_psc_spi_cleanup;
- master->dev.of_node = dev->of_node;
tempp = ioremap(regaddr, size);
if (!tempp) {
diff --git a/drivers/spi/spi-mpc52xx-psc.c b/drivers/spi/spi-mpc52xx-psc.c
index 6604715..502c953 100644
--- a/drivers/spi/spi-mpc52xx-psc.c
+++ b/drivers/spi/spi-mpc52xx-psc.c
@@ -398,7 +398,6 @@ static int __devinit mpc52xx_psc_spi_do_probe(struct device
*dev, u32 regaddr,
master->setup = mpc52xx_psc_spi_setup;
master->transfer = mpc52xx_psc_spi_transfer;
master->cleanup = mpc52xx_psc_spi_cleanup;
- master->dev.of_node = dev->of_node;
mps->psc = ioremap(regaddr, size);
if (!mps->psc) {
diff --git a/drivers/spi/spi-mpc52xx.c b/drivers/spi/spi-mpc52xx.c
index 57633d9..1a099f8 100644
--- a/drivers/spi/spi-mpc52xx.c
+++ b/drivers/spi/spi-mpc52xx.c
@@ -437,7 +437,6 @@ static int __devinit mpc52xx_spi_probe(struct
platform_device *op)
master->setup = mpc52xx_spi_setup;
master->transfer = mpc52xx_spi_transfer;
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
- master->dev.of_node = op->dev.of_node;
dev_set_drvdata(&op->dev, master);
diff --git a/drivers/spi/spi-oc-tiny.c b/drivers/spi/spi-oc-tiny.c
index 698018f..d030857 100644
--- a/drivers/spi/spi-oc-tiny.c
+++ b/drivers/spi/spi-oc-tiny.c
@@ -266,7 +266,6 @@ static int __devinit tiny_spi_of_probe(struct
platform_device *pdev)
if (hw->gpio_cs[i] < 0)
return -ENODEV;
}
- hw->bitbang.master->dev.of_node = pdev->dev.of_node;
val = of_get_property(pdev->dev.of_node,
"clock-frequency", &len);
if (val && len >= sizeof(__be32))
diff --git a/drivers/spi/spi-ppc4xx.c b/drivers/spi/spi-ppc4xx.c
index 98ec532..1aa8b33 100644
--- a/drivers/spi/spi-ppc4xx.c
+++ b/drivers/spi/spi-ppc4xx.c
@@ -406,7 +406,6 @@ static int __init spi_ppc4xx_of_probe(struct
platform_device *op)
master = spi_alloc_master(dev, sizeof *hw);
if (master == NULL)
return -ENOMEM;
- master->dev.of_node = np;
dev_set_drvdata(dev, master);
hw = spi_master_get_devdata(master);
hw->master = spi_master_get(master);
diff --git a/drivers/spi/spi-pxa2xx-pci.c b/drivers/spi/spi-pxa2xx-pci.c
index 8caa07d..5012979 100644
--- a/drivers/spi/spi-pxa2xx-pci.c
+++ b/drivers/sp
[PATCH 2/3] of_spi: add generic binding support to specify ncs gpio
This will allow to use gpio for chip select with no modification in the
driver binding
When use the ncs-gpios, the gpio number will be passed via the controller_data
and the number of chip select will automatically increased.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
Cc: devicetree-disc...@lists.ozlabs.org
Cc: spi-devel-general@lists.sourceforge.net
---
Documentation/devicetree/bindings/spi/spi-bus.txt |6 +++
drivers/of/of_spi.c | 27 ---
drivers/spi/spi.c | 51 +++-
include/linux/spi/spi.h |5 ++
4 files changed, 78 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt
b/Documentation/devicetree/bindings/spi/spi-bus.txt
index e782add..5a24729 100644
--- a/Documentation/devicetree/bindings/spi/spi-bus.txt
+++ b/Documentation/devicetree/bindings/spi/spi-bus.txt
@@ -12,6 +12,7 @@ The SPI master node requires the following properties:
- #size-cells - should be zero.
- compatible - name of SPI bus controller following generic names
recommended practice.
+- ncs-gpios - (optional) gpios chip select.
No other properties are required in the SPI bus node. It is assumed
that a driver for an SPI bus device will understand that it is an SPI bus.
However, the binding does not attempt to define the specific method for
@@ -21,6 +22,8 @@ assumption that board specific platform code will be used to
manage
chip selects. Individual drivers can define additional properties to
support describing the chip select layout.
+If ncs-gpios is used the number of chip select will automatically increased.
+
SPI slave nodes must be children of the SPI master node and can
contain the following properties.
- reg - (required) chip select address of device.
@@ -34,6 +37,9 @@ contain the following properties.
- spi-cs-high - (optional) Empty property indicating device requires
chip select active high
+If a gpio chipselect is used for the SPI slave the gpio number will be passed
+via the controller_data
+
SPI example for an MPC5200 SPI bus:
spi@f00 {
#address-cells = <1>;
diff --git a/drivers/of/of_spi.c b/drivers/of/of_spi.c
index 6dbc074..0d41407 100644
--- a/drivers/of/of_spi.c
+++ b/drivers/of/of_spi.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
/**
* of_register_spi_devices - Register child devices onto the SPI bus
@@ -27,6 +28,7 @@ void of_register_spi_devices(struct spi_master *master)
const __be32 *prop;
int rc;
int len;
+ int ncs_pin;
if (!master->dev.of_node)
return;
@@ -50,15 +52,24 @@ void of_register_spi_devices(struct spi_master *master)
continue;
}
- /* Device address */
- prop = of_get_property(nc, "reg", &len);
- if (!prop || len < sizeof(*prop)) {
- dev_err(&master->dev, "%s has no 'reg' property\n",
- nc->full_name);
- spi_dev_put(spi);
- continue;
+ /* ncs gpio */
+ ncs_pin = of_get_named_gpio(nc, "ncs-gpio", 0);
+
+ if (gpio_is_valid(ncs_pin)) {
+ spi->controller_data = (void *)ncs_pin;
+ spi->chip_select = master->num_chipselect;
+ master->num_chipselect++;
+ } else {
+ /* Device address */
+ prop = of_get_property(nc, "reg", &len);
+ if (!prop || len < sizeof(*prop)) {
+ dev_err(&master->dev, "%s has no 'reg'
property\n",
+ nc->full_name);
+ spi_dev_put(spi);
+ continue;
+ }
+ spi->chip_select = be32_to_cpup(prop);
}
- spi->chip_select = be32_to_cpup(prop);
/* Mode (clock phase/polarity/etc.) */
if (of_find_property(nc, "spi-cpha", NULL))
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index e2f4ca0..1f5ffa6 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -28,6 +28,7 @@
#include
#include
#include
+#include
#include
#include
@@ -339,15 +340,16 @@ EXPORT_SYMBOL_GPL(spi_alloc_device);
int spi_add_device(struct spi_device *spi)
{
static DEFINE_MUTEX(spi_add_lock);
- struct device *dev = spi->master->dev.parent;
+ struct spi_master *master = spi->master;
+ struct device *dev = master->dev.parent;
struct device *d;
int status;
/* Chipselects are numbered 0..max; validate. */
- if (spi->chip_select >= spi->master->num_chipselect) {
+ if (spi->chip_select >= master->num_chipselect) {
[PATCH RFC] spi/gpio: start with CS non-active
The chip select line was configured as output with the initial value being active explicitly. It was later deasserted during spi_bitbang_setup() without any clock activity in between. So it makes no sense to activate the device at all and the chip select line can better start non-active. Signed-off-by: Uwe Kleine-König --- Hello, I'm not sure if an active chip select line without any clock activity can confuse a device. If so, this patch might qualify as fix. But with my limited knowledge about spi it's also possible that I just miss why the active chip select is important. For the devices I have it doesn't seem to make a difference. Best regards Uwe drivers/spi/spi-gpio.c |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/drivers/spi/spi-gpio.c b/drivers/spi/spi-gpio.c index 0094c64..0b56cfc 100644 --- a/drivers/spi/spi-gpio.c +++ b/drivers/spi/spi-gpio.c @@ -235,7 +235,8 @@ static int spi_gpio_setup(struct spi_device *spi) status = gpio_request(cs, dev_name(&spi->dev)); if (status) return status; - status = gpio_direction_output(cs, spi->mode & SPI_CS_HIGH); + status = gpio_direction_output(cs, + !(spi->mode & SPI_CS_HIGH)); } } if (!status) -- 1.7.9 -- Virtualization & Cloud Management Using Capacity Planning Cloud computing makes use of virtualization - but cloud computing also focuses on allowing computing to be delivered as a service. http://www.accelacomm.com/jaw/sfnl/114/51521223/ ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH RESEND] intel_mid_ssp_spi: Moorestown and Medfield SPI for SSP devices
Hi Grant, On Thu, 9 Feb 2012 07:31:21 -0800 Grant Likely wrote: > On Wed, Feb 08, 2012 at 10:41:10AM +, Alan Cox wrote: > > From: Mathieu SOULARD > > > > This driver is a fusion of various internal drivers into a single > > driver for the SPI slave/master on the Intel Moorestown and Medfield > > SSP devices. > > > > Signed-off-by: Mathieu SOULARD > > [Queueing and runtime pm added] > > Signed-off-by: Kristen Carlson Accardi > > [Ported to the -next tree DMA engine] > > Signed-off-by: Alan Cox > > --- > > > > drivers/spi/Kconfig |8 > > drivers/spi/Makefile|2 > > drivers/spi/spi-intel-mid-ssp.c | 1426 > > +++ drivers/spi/spi-intel-mid-ssp.h | > > 308 > > If this is merging several of the drivers, what is the plan for the existing > SPI_DESIGNWARE and SPI_TOPCLIFF_PCH drivers? Or are those for different > devices? The DESIGNWARE controller has a different HW IP core, so the 2 drivers can't be merged. And for the TOPCLIFF one, seems it also use a different HW IP than this one, so I guess it can't be merged either. Thanks, Feng -- Virtualization & Cloud Management Using Capacity Planning Cloud computing makes use of virtualization - but cloud computing also focuses on allowing computing to be delivered as a service. http://www.accelacomm.com/jaw/sfnl/114/51521223/ ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
RE: [PATCH v3] SPI: add CSR SiRFprimaII SPI controller driver
Hi Grant,
> > +
> > +struct sirfsoc_spi {
> > + struct spi_bitbang bitbang;
> > + struct completion done;
> > +
> > + u32 irq;
>
> irq is set once and never used outside the probe function. Doesn't need
> to be here.
ok
>
> > + void __iomem *base;
> > + u32 ctrl_freq; /* SPI controller clock speed */
> > + struct clk *clk;
> > + int bus_num;
>
> bus_num is unused
Ok.
> > +
> > +static void spi_sirfsoc_tasklet_tx(unsigned long arg)
> > +{
> > + struct sirfsoc_spi *sspi = (struct sirfsoc_spi *)arg;
> > +
> > + /* Fill Tx FIFO while there are left words to be transmitted */
> > + while (!((readl(sspi->base + SIRFSOC_SPI_TXFIFO_STATUS) &
> > + SIRFSOC_SPI_FIFO_FULL)) &&
> > + sspi->left_tx_cnt)
> > + sspi->tx_word(sspi);
>
> Potential problem: if for any reason the device stalls and the FULL bit
> doesn't get cleared, then this function will be stuck in a tight loop. This
> may not be an issue, but it should be considered.
Might timeout check.
> > +
> > +static void spi_sirfsoc_chipselect(struct spi_device *spi, int value)
> > +{
> > + struct sirfsoc_spi *sspi = spi_master_get_devdata(spi->master);
> > + struct sirfsoc_spi_ctrldata *ctl_data = spi->controller_data;
>
> Where does controller_data come from? It is not set in the driver, and it is
> *not* something that the spi_device driver or the board code is allowed to
> set.
>
> If the driver needs controller_data, then it needs to be added to each spi
> device by the spi controller driver when the slave device is registered.
>
The controller_data is mainly for various kinds of chip selection. We might
have a CS pin, a GPIO from prima2, or a GPIO from an extended MCU side by side
with prima2.
It seems like you think this driver should handle all different kinds of chip
selection support and implement those callbacks in it? And every spi client use
DT to describe the CS pin?
-barry
Member of the CSR plc group of companies. CSR plc registered in England and
Wales, registered number 4187346, registered office Churchill House, Cambridge
Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at
http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog
--
Virtualization & Cloud Management Using Capacity Planning
Cloud computing makes use of virtualization - but cloud computing
also focuses on allowing computing to be delivered as a service.
http://www.accelacomm.com/jaw/sfnl/114/51521223/
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Promo exclusive, -10% sur toutes les têtes de lit
Pour voir le message, veuillez utiliser un lecteur de mail compatible HTML Lien miroir : http://mail.mc10.fr/mc10_m/YT0yNyZiPTYxODAmYz0yMzY0MzcmZD0yMDEyLTAyLTEwIDA3OjQwOjAxJmU9MSZoPTYxNzkmZj02MTgwJmc9NjE4MA== Lien de désinscription : http://mail.mc10.fr/mc10_unsub/YT0yNyZiPTYxODAmYz0yMzY0MzcmZD0yMDEyLTAyLTEwIDA3OjQwOjAxJmU9MSZoPTYxNzkmZj02MTgwJmc9NjE4MA== -- Virtualization & Cloud Management Using Capacity Planning Cloud computing makes use of virtualization - but cloud computing also focuses on allowing computing to be delivered as a service. http://www.accelacomm.com/jaw/sfnl/114/51521223/ ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Toupies Beyblade et Rapidity en stock !
Pour consulter la version en ligne, cliquez ici mydestock.com Toupies Beyblade TOUPIES BEYBLADE ET RAPIDITYPrix d*fiant toute concurrence Alors que toute l'Europe est en rupture de stock, Mydestock.com vous propose de vous livrer en 72H vos beyblades tant r*clam*es par vos enfants! En savoir plus Vous recevez cet e-mail de la part de Zabaloc. Vous avez la possibilit* de vous retirer de notre liste d'envoi de mails par l'intermediaire de ce raccourci. -- Virtualization & Cloud Management Using Capacity Planning Cloud computing makes use of virtualization - but cloud computing also focuses on allowing computing to be delivered as a service. http://www.accelacomm.com/jaw/sfnl/114/51521223/ ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
