Re: [PATCH 1/3] spi: spi-xilinx: Remove ISR race condition

[Shubhrajyoti Datta]

>
>>
>> =
>> spi: xilinx - minimize iomem reads
>>
>> If this IP core is accessed through bridges like PCI-e, reads are rather
>> costly. Doing many reads or read-modify-writes is thus long and strenuous
>> on the CPU (active waiting).
>>
>> The transfer workflow of this driver allows some assumptions to be made 
>> and
>> exploited to minimize reads as much as possible.
>>
>> These two assumptions are made:
>> - since we are in control of the CR register, cache it so we don't have 
>> to
>>   read it all the time to modify it.
>
> Makes sense.

I have made an attempt at it can you check if you get any performance
improvemets
on your setup.

http://www.spinics.net/lists/linux-spi/msg05963.html


Thanks,
Shubhrajyoti

--
Go from Idea to Many App Stores Faster with Intel(R) XDK
Give your users amazing mobile app experiences with Intel(R) XDK.
Use one codebase in this all-in-one HTML5 development environment.
Design, debug & build mobile apps & 2D/3D high-impact games for multiple OSs.
http://pubads.g.doubleclick.net/gampad/clk?id=254741911=/4140
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

Re: [PATCH 1/3] spi: spi-xilinx: Remove ISR race condition

[Shubhrajyoti Datta]

On Thu, Oct 8, 2015 at 8:40 PM, Jean-Francois Dagenais
 wrote:
>
>> On Jun 4, 2013, at 1:32 PM, Mark Brown  wrote:
>>
>> Applied but this is a bit sad, having to defer the refill to process
>> context means that we're adding extra latency which takes us further
>> away from being able to saturate the bus.  There ought to be a way to
>> avoid the issue though I can't think of a non-racy one - I guess level
>> triggered interrupts aren't an option?
>
> Hi all,
>
> We've been using an improved version of this driver in production for years 
> here
> in the 3.4 tree. I had to intervene in order to improve performance. I managed
> to double it (not bad).
Thats cool.



>
> Like the other threads I've seen about this, my strategy involved limiting the
> reads to the registers, which, through a pci-e link were kind of long. Here's
> the yet un-submitted commit header I carry in my clone:

Why not send the patches.

>
> =
> spi: xilinx - minimize iomem reads
>
> If this IP core is accessed through bridges like PCI-e, reads are rather
> costly. Doing many reads or read-modify-writes is thus long and strenuous
> on the CPU (active waiting).
>
> The transfer workflow of this driver allows some assumptions to be made 
> and
> exploited to minimize reads as much as possible.
>
> These two assumptions are made:
> - since we are in control of the CR register, cache it so we don't have to
>   read it all the time to modify it.

Makes sense.

> - FIFO (either depth of 1 or 16) are always maxed out, unless the 
> remaining
>   bytes are less than the FIFO depth. For this reason, we can predict the
>   state of the FIFOs without checking with the status register to check if
>   they are empty or full.

Can you explain more details.
>
> Reading 32Mb flash at 32MHz on a core with 8bits/word and FIFO enabled 
> (16),
> has dropped from ~60s to ~30s. Still high, but better. Most of the delay 
> still
> comes from emptying the RX FIFO one "word" at a time.
> ===
>

--
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

Re: [PATCH v2] spi: Add Lattice ECP3 FPGA configuration via SPI

[Shubhrajyoti Datta]

On Mon, Nov 26, 2012 at 4:12 PM, Stefan Roese s...@denx.de wrote:
 +
 +static int __devinit lattice_ecp3_probe(struct spi_device *spi)
 +{
 +   int err;
 +
 +   err = request_firmware_nowait(THIS_MODULE, FW_ACTION_NOHOTPLUG,
 + FIRMWARE_NAME, spi-dev,
 + GFP_KERNEL, spi, firmware_load);
 +   if (err) {
 +   dev_err(spi-dev, Firmware loading failed with %d!\n, err);
 +   goto err;
nitpick:
the goto looks un-necessary, could we return err here and save an
un-necessary branch.

 +   }
 +
 +   dev_info(spi-dev, FPGA bitstream configuration driver registered 
 (ver %s)\n,
 +   DRIVER_VER);
 +
 +   return 0;
 +
 +err:
 +   return err;
 +}

--
Monitor your physical, virtual and cloud infrastructure from a single
web console. Get in-depth insight into apps, servers, databases, vmware,
SAP, cloud infrastructure, etc. Download 30-day Free Trial.
Pricing starts from $795 for 25 servers or applications!
http://p.sf.net/sfu/zoho_dev2dev_nov
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

Re: [PATCH] SPI: SSP SPI Controller driver

[Shubhrajyoti Datta]

On Wed, Nov 21, 2012 at 7:46 AM, chao bi chao...@intel.com wrote:


 This patch is to implement SSP SPI controller driver, which has been
 applied and
 validated on intel Moorestown  Medfield platform. The patch are
 originated by
 Ken Mills ken.k.mi...@intel.com and Sylvain Centelles 
 sylvain.centel...@intel.com,
 and to be further developed by Channing chao...@intel.com and Chen Jun
 jun.d.c...@intel.com according to their integration  validation on
 Medfield platform.

 Signed-off-by: Ken Mills ken.k.mi...@intel.com
 Signed-off-by: Sylvain Centelles sylvain.centel...@intel.com
 Signed-off-by: channing chao...@intel.com
 Signed-off-by: Chen Jun jun.d.c...@intel.com
 ---
  drivers/spi/Kconfig   |9 +
  drivers/spi/Makefile  |1 +
  drivers/spi/spi-intel-mid-ssp.c   | 1407
 +
  include/linux/spi/spi-intel-mid-ssp.h |  326 
  4 files changed, 1743 insertions(+), 0 deletions(-)
  create mode 100644 drivers/spi/spi-intel-mid-ssp.c
  create mode 100644 include/linux/spi/spi-intel-mid-ssp.h

 diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
 index 1acae35..8b4461b 100644
 --- a/drivers/spi/Kconfig
 +++ b/drivers/spi/Kconfig
 @@ -179,6 +179,15 @@ config SPI_IMX
   This enables using the Freescale i.MX SPI controllers in master
   mode.

 +config SPI_INTEL_MID_SSP
 +   tristate SSP SPI controller driver for Intel MID platforms
 +   depends on SPI_MASTER  INTEL_MID_DMAC
 +   help
 + This is the unified SSP SPI master controller driver for
 + the Intel MID platforms, handling Moorestown  Medfield,
 + master clock mode.
 + It supports Bulverde SSP core.
 +
  config SPI_LM70_LLP
 tristate Parallel port adapter for LM70 eval board (DEVELOPMENT)
 depends on PARPORT  EXPERIMENTAL
 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
 index c48df47..83f06d0 100644
 --- a/drivers/spi/Makefile
 +++ b/drivers/spi/Makefile
 @@ -32,6 +32,7 @@ obj-$(CONFIG_SPI_FSL_ESPI)+= spi-fsl-espi.o
  obj-$(CONFIG_SPI_FSL_SPI)  += spi-fsl-spi.o
  obj-$(CONFIG_SPI_GPIO) += spi-gpio.o
  obj-$(CONFIG_SPI_IMX)  += spi-imx.o
 +obj-$(CONFIG_SPI_INTEL_MID_SSP)+= spi-intel-mid-ssp.o
  obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o
  obj-$(CONFIG_SPI_MPC512x_PSC)  += spi-mpc512x-psc.o
  obj-$(CONFIG_SPI_MPC52xx_PSC)  += spi-mpc52xx-psc.o
 diff --git a/drivers/spi/spi-intel-mid-ssp.c
 b/drivers/spi/spi-intel-mid-ssp.c
 new file mode 100644
 index 000..8fca48f
 --- /dev/null
 +++ b/drivers/spi/spi-intel-mid-ssp.c
 @@ -0,0 +1,1407 @@
 +/*
 + * spi-intel-mid-ssp.c
 + * This driver supports Bulverde SSP core used on Intel MID platforms
 + * It supports SSP of Moorestown  Medfield platforms and handles clock
 + * slave  master modes.
 + *
 + * Copyright (c) 2010, Intel Corporation.
 + *  Ken Mills ken.k.mi...@intel.com
 + *  Sylvain Centelles sylvain.centel...@intel.com
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2, as published by the Free Software Foundation.
 + *
 + * This program is distributed in the hope it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 for
 + * more details.
 + *
 + * You should have received a copy of the GNU General Public License
 along with
 + * this program; if not, write to the Free Software Foundation, Inc.,
 + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 + *
 + */
 +
 +/*
 + * Note:
 + *
 + * Supports DMA and non-interrupt polled transfers.
 + *
 + */
 +
 +#include linux/delay.h
 +#include linux/interrupt.h
 +#include linux/highmem.h
 +#include linux/pci.h
 +#include linux/init.h
 +#include linux/interrupt.h
 +#include linux/dma-mapping.h
 +#include linux/intel_mid_dma.h
 +#include linux/pm_qos.h
 +#include linux/module.h
 +
 +#include linux/spi/spi.h
 +#include linux/spi/spi-intel-mid-ssp.h
 +
 +#define DRIVER_NAME intel_mid_ssp_spi_unified
 +
 +MODULE_AUTHOR(Ken Mills);
 +MODULE_DESCRIPTION(Bulverde SSP core SPI contoller);
 +MODULE_LICENSE(GPL);
 +
 +static const struct pci_device_id pci_ids[];
 +
 +#ifdef DUMP_RX
 +static void dump_trailer(const struct device *dev, char *buf, int len,
 int sz)
 +{
 +   int tlen1 = (len  sz ? len : sz);
 +   int tlen2 =  ((len - sz)  sz) ? sz : (len - sz);
 +   unsigned char *p;
 +   static char msg[MAX_SPI_TRANSFER_SIZE];
 +
 +   memset(msg, '\0', sizeof(msg));
 +   p = buf;
 +   while (p  buf + tlen1)
 +   sprintf(msg, %s%02x, msg, (unsigned int)*p++);
 +
 +   if (tlen2  0) {
 +   sprintf(msg, %s ., msg);
 +   p = (buf+len) - tlen2;
 +   while (p  buf + len)
 + 

Re: [PATCH] SPI: SSP SPI Controller driver

[Shubhrajyoti Datta]

On Wed, Nov 21, 2012 at 7:46 AM, chao bi chao...@intel.com wrote:

 +   /* Create the PM_QOS request */
 +   if (drv_context-quirks  QUIRKS_USE_PM_QOS)
 +   pm_qos_add_request(drv_context-pm_qos_req,
 +   PM_QOS_CPU_DMA_LATENCY,
 +   PM_QOS_DEFAULT_VALUE);


What happens if the flag is not set if it is absolutely necessary for the
driver it should not be a
configurable option?
--
Monitor your physical, virtual and cloud infrastructure from a single
web console. Get in-depth insight into apps, servers, databases, vmware,
SAP, cloud infrastructure, etc. Download 30-day Free Trial.
Pricing starts from $795 for 25 servers or applications!
http://p.sf.net/sfu/zoho_dev2dev_nov
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

Re: [PATCH] SPI: SSP SPI Controller driver

[Shubhrajyoti Datta]

On Wed, Nov 21, 2012 at 5:56 PM, Alan Cox a...@linux.intel.com wrote:

 On Wed, 21 Nov 2012 17:44:21 +0530
 Shubhrajyoti Datta omaplinuxker...@gmail.com wrote:

  On Wed, Nov 21, 2012 at 7:46 AM, chao bi chao...@intel.com wrote:
 
   +   /* Create the PM_QOS request */
   +   if (drv_context-quirks  QUIRKS_USE_PM_QOS)
   +   pm_qos_add_request(drv_context-pm_qos_req,
   +   PM_QOS_CPU_DMA_LATENCY,
   +   PM_QOS_DEFAULT_VALUE);
  
 
  What happens if the flag is not set if it is absolutely necessary for
  the driver it should not be a
  configurable option

 If you read through the code it's set only when the device is
 Moorestown/Oaktrail based and only in slave mode. It is not necessary
 in other configurations.


Thats what I was trying to understand.

If I am not wrong the latency is time related.
Why only some platforms / modes need it also the value is not speed
dependent.


My doubt is that the time taken for the dma will be more in lower speed so
the
latency constraint could be relaxed.

Also the spi core today doesnt have slave mode support thats a different
discussion altogether may be we can leave it for now.





 Alan

--
Monitor your physical, virtual and cloud infrastructure from a single
web console. Get in-depth insight into apps, servers, databases, vmware,
SAP, cloud infrastructure, etc. Download 30-day Free Trial.
Pricing starts from $795 for 25 servers or applications!
http://p.sf.net/sfu/zoho_dev2dev_nov
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

Re: [PATCH 06/17] spi/atmel_spi: add flag to controller data for lock operations

[Shubhrajyoti Datta]

On Mon, Nov 12, 2012 at 2:22 PM, Wenyou Yang wenyou.y...@atmel.com wrote:
 From: Nicolas Ferre nicolas.fe...@atmel.com

 Will allow to drop the lock during DMA operations.

 Signed-off-by: Nicolas Ferre nicolas.fe...@atmel.com
 Cc: grant.lik...@secretlab.ca
 Cc: spi-devel-general@lists.sourceforge.net
 ---
  drivers/spi/spi-atmel.c |   31 +++
  1 file changed, 19 insertions(+), 12 deletions(-)

 diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
 index 76a1baf..37f54c3 100644
 --- a/drivers/spi/spi-atmel.c
 +++ b/drivers/spi/spi-atmel.c
 @@ -187,6 +187,7 @@
   */
  struct atmel_spi {
 spinlock_t  lock;
 +   unsigned long   flags;

 resource_size_t phybase;
 void __iomem*regs;
 @@ -323,6 +324,16 @@ static void cs_deactivate(struct atmel_spi *as, struct 
 spi_device *spi)
 gpio_set_value(asd-npcs_pin, !active);
  }

 +static void atmel_spi_lock(struct atmel_spi *as)
 +{
 +   spin_lock_irqsave(as-lock, as-flags);
 +}
 +
 +static void atmel_spi_unlock(struct atmel_spi *as)
 +{
 +   spin_unlock_irqrestore(as-lock, as-flags);
 +}

May be this can be called directly.

 +
  static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
 struct spi_transfer *xfer)
  {
 @@ -559,9 +570,9 @@ atmel_spi_msg_done(struct spi_master *master, struct 
 atmel_spi *as,
 xfer complete: %u bytes transferred\n,
 msg-actual_length);

 -   spin_unlock(as-lock);
 +   atmel_spi_unlock(as);
 msg-complete(msg-context);
 -   spin_lock(as-lock);
 +   atmel_spi_lock(as);

 as-current_transfer = NULL;
 as-next_transfer = NULL;
 @@ -788,13 +799,11 @@ static int atmel_spi_setup(struct spi_device *spi)
 spi-controller_state = asd;
 gpio_direction_output(npcs_pin, !(spi-mode  SPI_CS_HIGH));
 } else {
 -   unsigned long   flags;
 -
 -   spin_lock_irqsave(as-lock, flags);
 +   atmel_spi_lock(as);
 if (as-stay == spi)
 as-stay = NULL;
 cs_deactivate(as, spi);
 -   spin_unlock_irqrestore(as-lock, flags);
 +   atmel_spi_unlock(as);
 }

 asd-csr = csr;
 @@ -813,7 +822,6 @@ static int atmel_spi_transfer(struct spi_device *spi, 
 struct spi_message *msg)
  {
 struct atmel_spi*as;
 struct spi_transfer *xfer;
 -   unsigned long   flags;
 struct device   *controller = spi-master-dev.parent;
 u8  bits;
 struct atmel_spi_device *asd;
 @@ -878,11 +886,11 @@ static int atmel_spi_transfer(struct spi_device *spi, 
 struct spi_message *msg)
 msg-status = -EINPROGRESS;
 msg-actual_length = 0;

 -   spin_lock_irqsave(as-lock, flags);
 +   atmel_spi_lock(as);
 list_add_tail(msg-queue, as-queue);
 if (!as-current_transfer)
 atmel_spi_next_message(spi-master);
 -   spin_unlock_irqrestore(as-lock, flags);
 +   atmel_spi_unlock(as);

 return 0;
  }
 @@ -892,17 +900,16 @@ static void atmel_spi_cleanup(struct spi_device *spi)
 struct atmel_spi*as = spi_master_get_devdata(spi-master);
 struct atmel_spi_device *asd = spi-controller_state;
 unsignedgpio = (unsigned) spi-controller_data;
 -   unsigned long   flags;

 if (!asd)
 return;

 -   spin_lock_irqsave(as-lock, flags);
 +   atmel_spi_lock(as);
 if (as-stay == spi) {
 as-stay = NULL;
 cs_deactivate(as, spi);
 }
 -   spin_unlock_irqrestore(as-lock, flags);
 +   atmel_spi_unlock(as);

 spi-controller_state = NULL;
 gpio_free(gpio);
 --
 1.7.9.5


 --
 Everyone hates slow websites. So do we.
 Make your web apps faster with AppDynamics
 Download AppDynamics Lite for free today:
 http://p.sf.net/sfu/appdyn_d2d_nov
 ___
 spi-devel-general mailing list
 spi-devel-general@lists.sourceforge.net
 https://lists.sourceforge.net/lists/listinfo/spi-devel-general

--
Monitor your physical, virtual and cloud infrastructure from a single
web console. Get in-depth insight into apps, servers, databases, vmware,
SAP, cloud infrastructure, etc. Download 30-day Free Trial.
Pricing starts from $795 for 25 servers or applications!
http://p.sf.net/sfu/zoho_dev2dev_nov
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

Re: [PATCH resend] SPI: McSPI: fix D0/D1 direction confusion

[Shubhrajyoti Datta]

On Wed, Nov 14, 2012 at 8:44 AM, Daniel Mack zon...@gmail.com wrote:
 0384e90b8 (spi/mcspi: allow configuration of pin directions) did what
 it claimed to do the wrong way around. D0/D1 is configured as output by
 *clearing* the bits in the conf registers, hence also breaking the
 former default behaviour.

 Fix this before that change is merged to mainline.

Indeed. Thanks.
Reviewed-by: Shubhrajyoti D shubhrajy...@ti.com

 Signed-off-by: Daniel Mack zon...@gmail.com
 ---
 Resent to apply directly on top of original commit.

  Documentation/devicetree/bindings/spi/omap-spi.txt | 6 +++---
  drivers/spi/spi-omap2-mcspi.c  | 6 +++---
  include/linux/platform_data/spi-omap2-mcspi.h  | 4 ++--
  3 files changed, 8 insertions(+), 8 deletions(-)

 diff --git a/Documentation/devicetree/bindings/spi/omap-spi.txt 
 b/Documentation/devicetree/bindings/spi/omap-spi.txt
 index 2ef0a6b..938809c 100644
 --- a/Documentation/devicetree/bindings/spi/omap-spi.txt
 +++ b/Documentation/devicetree/bindings/spi/omap-spi.txt
 @@ -6,9 +6,9 @@ Required properties:
- ti,omap4-spi for OMAP4+.
  - ti,spi-num-cs : Number of chipselect supported  by the instance.
  - ti,hwmods: Name of the hwmod associated to the McSPI
 -- ti,pindir-d0-in-d1-out: Select the D0 pin as input and D1 as
 - output. The default is D0 as output and
 - D1 as input.
 +- ti,pindir-d0-out-d1-in: Select the D0 pin as output and D1 as
 + input. The default is D0 as input and
 + D1 as output.

  Example:

 diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
 index 5104633..89f73c4 100644
 --- a/drivers/spi/spi-omap2-mcspi.c
 +++ b/drivers/spi/spi-omap2-mcspi.c
 @@ -766,7 +766,7 @@ static int omap2_mcspi_setup_transfer(struct spi_device 
 *spi,
 /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
  * REVISIT: this controller could support SPI_3WIRE mode.
  */
 -   if (mcspi-pin_dir == MCSPI_PINDIR_D0_OUT_D1_IN) {
 +   if (mcspi-pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
 l = ~OMAP2_MCSPI_CHCONF_IS;
 l = ~OMAP2_MCSPI_CHCONF_DPE1;
 l |= OMAP2_MCSPI_CHCONF_DPE0;
 @@ -1188,8 +1188,8 @@ static int __devinit omap2_mcspi_probe(struct 
 platform_device *pdev)
 of_property_read_u32(node, ti,spi-num-cs, num_cs);
 master-num_chipselect = num_cs;
 master-bus_num = bus_num++;
 -   if (of_get_property(node, ti,pindir-d0-in-d1-out, NULL))
 -   mcspi-pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
 +   if (of_get_property(node, ti,pindir-d0-out-d1-in, NULL))
 +   mcspi-pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
 } else {
 pdata = pdev-dev.platform_data;
 master-num_chipselect = pdata-num_cs;
 diff --git a/include/linux/platform_data/spi-omap2-mcspi.h 
 b/include/linux/platform_data/spi-omap2-mcspi.h
 index ce70f7b..a65572d 100644
 --- a/include/linux/platform_data/spi-omap2-mcspi.h
 +++ b/include/linux/platform_data/spi-omap2-mcspi.h
 @@ -7,8 +7,8 @@

  #define OMAP4_MCSPI_REG_OFFSET 0x100

 -#define MCSPI_PINDIR_D0_OUT_D1_IN  0
 -#define MCSPI_PINDIR_D0_IN_D1_OUT  1
 +#define MCSPI_PINDIR_D0_IN_D1_OUT  0
 +#define MCSPI_PINDIR_D0_OUT_D1_IN  1

  struct omap2_mcspi_platform_config {
 unsigned short  num_cs;
 --
 1.7.11.7


 --
 Monitor your physical, virtual and cloud infrastructure from a single
 web console. Get in-depth insight into apps, servers, databases, vmware,
 SAP, cloud infrastructure, etc. Download 30-day Free Trial.
 Pricing starts from $795 for 25 servers or applications!
 http://p.sf.net/sfu/zoho_dev2dev_nov
 ___
 spi-devel-general mailing list
 spi-devel-general@lists.sourceforge.net
 https://lists.sourceforge.net/lists/listinfo/spi-devel-general

--
Monitor your physical, virtual and cloud infrastructure from a single
web console. Get in-depth insight into apps, servers, databases, vmware,
SAP, cloud infrastructure, etc. Download 30-day Free Trial.
Pricing starts from $795 for 25 servers or applications!
http://p.sf.net/sfu/zoho_dev2dev_nov
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

Re: [PATCH] spi: omap2-mcspi: Reorder the wait_for_completion for tx

[Shubhrajyoti Datta]

On Tue, Nov 6, 2012 at 2:33 PM, Mark Brown
broo...@opensource.wolfsonmicro.com wrote:
 On Tue, Nov 06, 2012 at 02:30:19PM +0530, Shubhrajyoti D wrote:
 The commit  d7b4394e[Cleanup the omap2_mcspi_txrx_dma function]
 changed the wait_for_completion order. Move the wait so that the
 rx doesnot wait for the tx to complete.

 Applied, thanks.

Thanks Mark,

--
LogMeIn Central: Instant, anywhere, Remote PC access and management.
Stay in control, update software, and manage PCs from one command center
Diagnose problems and improve visibility into emerging IT issues
Automate, monitor and manage. Do more in less time with Central
http://p.sf.net/sfu/logmein12331_d2d
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

Re: [PATCH] spi: omap2-mcspi: Reorder the wait_for_completion for tx

[Shubhrajyoti Datta]

On Tue, Nov 6, 2012 at 2:52 PM, Mark Brown
broo...@opensource.wolfsonmicro.com wrote:
 On Tue, Nov 06, 2012 at 02:47:27PM +0530, Shubhrajyoti D wrote:
 The commit  d7b4394e[Cleanup the omap2_mcspi_txrx_dma function]
 changed the wait_for_completion order. Move the wait so that the
 rx doesnot wait for the tx to complete.

 Is this a resend of the patch I just applied, or is it something
 different?

No please ignore this one.

Something wrong at my end it got sent twice.
Please ignore.

--
LogMeIn Central: Instant, anywhere, Remote PC access and management.
Stay in control, update software, and manage PCs from one command center
Diagnose problems and improve visibility into emerging IT issues
Automate, monitor and manage. Do more in less time with Central
http://p.sf.net/sfu/logmein12331_d2d
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

Re: [REGRESSION] d7b4394e breaks bi-directional DMA transfers on omap2-mcspi

[Shubhrajyoti Datta]

On Wed, Oct 31, 2012 at 8:59 PM, Shubhrajyoti Datta
omaplinuxker...@gmail.com wrote:
[...]

Mark,

let me know if you want me to resubmit it as a patch.


 From 07a59cb82955c37eff6fe06ba25958dc1b5c5f56 Mon Sep 17 00:00:00 2001
 From: Shubhrajyoti D shubhrajy...@ti.com
 Date: Wed, 31 Oct 2012 19:15:25 +0530
 Subject: [PATCH] spi: omap2-mcspi: Reorder the wait_for_completion for tx

 The commit  d7b4394e[Cleanup the omap2_mcspi_txrx_dma function]
 changed the wait_for_completion order. Move the wait so that the
 rx doesnot wait for the tx to complete.

 Reported-by: Sørensen, Stefan soren...@polycom.com
 Signed-off-by: Shubhrajyoti D shubhrajy...@ti.com
 ---
  drivers/spi/spi-omap2-mcspi.c |   39 +++
  1 files changed, 19 insertions(+), 20 deletions(-)

 diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
 index bcfd062..251f6d0 100644
 --- a/drivers/spi/spi-omap2-mcspi.c
 +++ b/drivers/spi/spi-omap2-mcspi.c
 @@ -323,18 +323,13 @@ static void omap2_mcspi_tx_dma(struct spi_device *spi,
 struct omap2_mcspi  *mcspi;
 struct omap2_mcspi_dma  *mcspi_dma;
 unsigned intcount;
 -   u8  * rx;
 const u8* tx;
 -   void __iomem*chstat_reg;
 -   struct omap2_mcspi_cs   *cs = spi-controller_state;

 mcspi = spi_master_get_devdata(spi-master);
 mcspi_dma = mcspi-dma_channels[spi-chip_select];
 count = xfer-len;

 -   rx = xfer-rx_buf;
 tx = xfer-tx_buf;
 -   chstat_reg = cs-base + OMAP2_MCSPI_CHSTAT0;

 if (mcspi_dma-dma_tx) {
 struct dma_async_tx_descriptor *tx;
 @@ -359,19 +354,6 @@ static void omap2_mcspi_tx_dma(struct spi_device *spi,
 dma_async_issue_pending(mcspi_dma-dma_tx);
 omap2_mcspi_set_dma_req(spi, 0, 1);

 -   wait_for_completion(mcspi_dma-dma_tx_completion);
 -   dma_unmap_single(mcspi-dev, xfer-tx_dma, count,
 -DMA_TO_DEVICE);
 -
 -   /* for TX_ONLY mode, be sure all words have shifted out */
 -   if (rx == NULL) {
 -   if (mcspi_wait_for_reg_bit(chstat_reg,
 -   OMAP2_MCSPI_CHSTAT_TXS)  0)
 -   dev_err(spi-dev, TXS timed out\n);
 -   else if (mcspi_wait_for_reg_bit(chstat_reg,
 -   OMAP2_MCSPI_CHSTAT_EOT)  0)
 -   dev_err(spi-dev, EOT timed out\n);
 -   }
  }

  static unsigned
 @@ -492,6 +474,7 @@ omap2_mcspi_txrx_dma(struct spi_device *spi,
 struct spi_transfer *xfer)
 struct dma_slave_config cfg;
 enum dma_slave_buswidth width;
 unsigned es;
 +   void __iomem*chstat_reg;

 mcspi = spi_master_get_devdata(spi-master);
 mcspi_dma = mcspi-dma_channels[spi-chip_select];
 @@ -526,8 +509,24 @@ omap2_mcspi_txrx_dma(struct spi_device *spi,
 struct spi_transfer *xfer)
 omap2_mcspi_tx_dma(spi, xfer, cfg);

 if (rx != NULL)
 -   return omap2_mcspi_rx_dma(spi, xfer, cfg, es);
 -
 +   count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
 +
 +   if (tx != NULL) {
 +   chstat_reg = cs-base + OMAP2_MCSPI_CHSTAT0;
 +   wait_for_completion(mcspi_dma-dma_tx_completion);
 +   dma_unmap_single(mcspi-dev, xfer-tx_dma, xfer-len,
 +DMA_TO_DEVICE);
 +
 +   /* for TX_ONLY mode, be sure all words have shifted out */
 +   if (rx == NULL) {
 +   if (mcspi_wait_for_reg_bit(chstat_reg,
 +   OMAP2_MCSPI_CHSTAT_TXS)  0)
 +   dev_err(spi-dev, TXS timed out\n);
 +   else if (mcspi_wait_for_reg_bit(chstat_reg,
 +   OMAP2_MCSPI_CHSTAT_EOT)  0)
 +   dev_err(spi-dev, EOT timed out\n);
 +   }
 +   }
 return count;
  }

 --
 1.7.5.4

--
LogMeIn Central: Instant, anywhere, Remote PC access and management.
Stay in control, update software, and manage PCs from one command center
Diagnose problems and improve visibility into emerging IT issues
Automate, monitor and manage. Do more in less time with Central
http://p.sf.net/sfu/logmein12331_d2d
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

Re: [REGRESSION] d7b4394e breaks bi-directional DMA transfers on omap2-mcspi

[Shubhrajyoti Datta]

On Wed, Oct 31, 2012 at 5:46 PM, Sørensen, Stefan
stefan.soren...@polycom.com wrote:
 Bi-directional SPI transfers using DMA no longer works on omap2-mcspi after
 this commit:
My bad.


 commit d7b4394e780b02511c8a7a499380cdd56316c770
 Author: Shubhrajyoti D shubhrajy...@ti.com
 Date:   Tue Sep 11 12:13:20 2012 +0530

 spi: omap2-mcspi: Cleanup the omap2_mcspi_txrx_dma function

 Currently in omap2_mcspi_txrx_dma the tx and the rx support is
 interleaved. Make the rx related code in omap2_mcspi_rx_dma
 and the tx related code omap2_mcspi_tx_dma and call the functions.

 While at it remove the braces in the if statements which has only
 one line.
 Also fix [foo * bar to foo *bar] warn for the rx and tx variables.

 Only a cleanup no functional change.

 Signed-off-by: Shubhrajyoti D shubhrajy...@ti.com
 Tested-by: Felipe Balbi ba...@ti.com
 Signed-off-by: Mark Brown broo...@opensource.wolfsonmicro.com


 Basically the patch changes the pattern
 start_tx();
 start_rx();
 wait_for_completion(tx);
 wait_for_completion(tx);
 into
 start_tx();
 wait_for_completion(tx);
 start_rx();
 wait_for_completion(tx);
 which will stall the transfer since the rx channel is not serviced.

So moving the tx completion.

Apologies for breaking in the original commit.


Will test and get back with a proper patch.
---
 drivers/spi/spi-omap2-mcspi.c |   34 --
 1 files changed, 16 insertions(+), 18 deletions(-)

diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
index 3542fdc..e8e5bbc 100644
--- a/drivers/spi/spi-omap2-mcspi.c
+++ b/drivers/spi/spi-omap2-mcspi.c
@@ -323,18 +323,13 @@ static void omap2_mcspi_tx_dma(struct spi_device *spi,
struct omap2_mcspi  *mcspi;
struct omap2_mcspi_dma  *mcspi_dma;
unsigned intcount;
-   u8  * rx;
const u8* tx;
-   void __iomem*chstat_reg;
-   struct omap2_mcspi_cs   *cs = spi-controller_state;

mcspi = spi_master_get_devdata(spi-master);
mcspi_dma = mcspi-dma_channels[spi-chip_select];
count = xfer-len;

-   rx = xfer-rx_buf;
tx = xfer-tx_buf;
-   chstat_reg = cs-base + OMAP2_MCSPI_CHSTAT0;

if (mcspi_dma-dma_tx) {
struct dma_async_tx_descriptor *tx;
@@ -359,19 +354,6 @@ static void omap2_mcspi_tx_dma(struct spi_device *spi,
dma_async_issue_pending(mcspi_dma-dma_tx);
omap2_mcspi_set_dma_req(spi, 0, 1);

-   wait_for_completion(mcspi_dma-dma_tx_completion);
-   dma_unmap_single(mcspi-dev, xfer-tx_dma, count,
-DMA_TO_DEVICE);
-
-   /* for TX_ONLY mode, be sure all words have shifted out */
-   if (rx == NULL) {
-   if (mcspi_wait_for_reg_bit(chstat_reg,
-   OMAP2_MCSPI_CHSTAT_TXS)  0)
-   dev_err(spi-dev, TXS timed out\n);
-   else if (mcspi_wait_for_reg_bit(chstat_reg,
-   OMAP2_MCSPI_CHSTAT_EOT)  0)
-   dev_err(spi-dev, EOT timed out\n);
-   }
 }

 static unsigned
@@ -492,6 +474,7 @@ omap2_mcspi_txrx_dma(struct spi_device *spi,
struct spi_transfer *xfer)
struct dma_slave_config cfg;
enum dma_slave_buswidth width;
unsigned es;
+   void __iomem*chstat_reg;

mcspi = spi_master_get_devdata(spi-master);
mcspi_dma = mcspi-dma_channels[spi-chip_select];
@@ -528,6 +511,21 @@ omap2_mcspi_txrx_dma(struct spi_device *spi,
struct spi_transfer *xfer)
if (rx != NULL)
return omap2_mcspi_rx_dma(spi, xfer, cfg, es);

+   chstat_reg = cs-base + OMAP2_MCSPI_CHSTAT0;
+   wait_for_completion(mcspi_dma-dma_tx_completion);
+   dma_unmap_single(mcspi-dev, xfer-tx_dma, count,
+DMA_TO_DEVICE);
+
+   /* for TX_ONLY mode, be sure all words have shifted out */
+   if (rx == NULL) {
+   if (mcspi_wait_for_reg_bit(chstat_reg,
+   OMAP2_MCSPI_CHSTAT_TXS)  0)
+   dev_err(spi-dev, TXS timed out\n);
+   else if (mcspi_wait_for_reg_bit(chstat_reg,
+   OMAP2_MCSPI_CHSTAT_EOT)  0)
+   dev_err(spi-dev, EOT timed out\n);
+   }
+
return count;
 }

-- 
1.7.5.4

--
Everyone hates slow websites. So do we.
Make your web apps faster with AppDynamics
Download AppDynamics Lite for free today:
http://p.sf.net/sfu/appdyn_sfd2d_oct
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

Re: [REGRESSION] d7b4394e breaks bi-directional DMA transfers on omap2-mcspi

[Shubhrajyoti Datta]

On Wed, Oct 31, 2012 at 7:27 PM, Shubhrajyoti Datta
omaplinuxker...@gmail.com wrote:
 On Wed, Oct 31, 2012 at 5:46 PM, Sørensen, Stefan
[...]

 Will test and get back with a proper patch.

Let me know if this solves.

From 07a59cb82955c37eff6fe06ba25958dc1b5c5f56 Mon Sep 17 00:00:00 2001
From: Shubhrajyoti D shubhrajy...@ti.com
Date: Wed, 31 Oct 2012 19:15:25 +0530
Subject: [PATCH] spi: omap2-mcspi: Reorder the wait_for_completion for tx

The commit  d7b4394e[Cleanup the omap2_mcspi_txrx_dma function]
changed the wait_for_completion order. Move the wait so that the
rx doesnot wait for the tx to complete.

Reported-by: Sørensen, Stefan soren...@polycom.com
Signed-off-by: Shubhrajyoti D shubhrajy...@ti.com
---
 drivers/spi/spi-omap2-mcspi.c |   39 +++
 1 files changed, 19 insertions(+), 20 deletions(-)

diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
index bcfd062..251f6d0 100644
--- a/drivers/spi/spi-omap2-mcspi.c
+++ b/drivers/spi/spi-omap2-mcspi.c
@@ -323,18 +323,13 @@ static void omap2_mcspi_tx_dma(struct spi_device *spi,
struct omap2_mcspi  *mcspi;
struct omap2_mcspi_dma  *mcspi_dma;
unsigned intcount;
-   u8  * rx;
const u8* tx;
-   void __iomem*chstat_reg;
-   struct omap2_mcspi_cs   *cs = spi-controller_state;

mcspi = spi_master_get_devdata(spi-master);
mcspi_dma = mcspi-dma_channels[spi-chip_select];
count = xfer-len;

-   rx = xfer-rx_buf;
tx = xfer-tx_buf;
-   chstat_reg = cs-base + OMAP2_MCSPI_CHSTAT0;

if (mcspi_dma-dma_tx) {
struct dma_async_tx_descriptor *tx;
@@ -359,19 +354,6 @@ static void omap2_mcspi_tx_dma(struct spi_device *spi,
dma_async_issue_pending(mcspi_dma-dma_tx);
omap2_mcspi_set_dma_req(spi, 0, 1);

-   wait_for_completion(mcspi_dma-dma_tx_completion);
-   dma_unmap_single(mcspi-dev, xfer-tx_dma, count,
-DMA_TO_DEVICE);
-
-   /* for TX_ONLY mode, be sure all words have shifted out */
-   if (rx == NULL) {
-   if (mcspi_wait_for_reg_bit(chstat_reg,
-   OMAP2_MCSPI_CHSTAT_TXS)  0)
-   dev_err(spi-dev, TXS timed out\n);
-   else if (mcspi_wait_for_reg_bit(chstat_reg,
-   OMAP2_MCSPI_CHSTAT_EOT)  0)
-   dev_err(spi-dev, EOT timed out\n);
-   }
 }

 static unsigned
@@ -492,6 +474,7 @@ omap2_mcspi_txrx_dma(struct spi_device *spi,
struct spi_transfer *xfer)
struct dma_slave_config cfg;
enum dma_slave_buswidth width;
unsigned es;
+   void __iomem*chstat_reg;

mcspi = spi_master_get_devdata(spi-master);
mcspi_dma = mcspi-dma_channels[spi-chip_select];
@@ -526,8 +509,24 @@ omap2_mcspi_txrx_dma(struct spi_device *spi,
struct spi_transfer *xfer)
omap2_mcspi_tx_dma(spi, xfer, cfg);

if (rx != NULL)
-   return omap2_mcspi_rx_dma(spi, xfer, cfg, es);
-
+   count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
+
+   if (tx != NULL) {
+   chstat_reg = cs-base + OMAP2_MCSPI_CHSTAT0;
+   wait_for_completion(mcspi_dma-dma_tx_completion);
+   dma_unmap_single(mcspi-dev, xfer-tx_dma, xfer-len,
+DMA_TO_DEVICE);
+
+   /* for TX_ONLY mode, be sure all words have shifted out */
+   if (rx == NULL) {
+   if (mcspi_wait_for_reg_bit(chstat_reg,
+   OMAP2_MCSPI_CHSTAT_TXS)  0)
+   dev_err(spi-dev, TXS timed out\n);
+   else if (mcspi_wait_for_reg_bit(chstat_reg,
+   OMAP2_MCSPI_CHSTAT_EOT)  0)
+   dev_err(spi-dev, EOT timed out\n);
+   }
+   }
return count;
 }

-- 
1.7.5.4

--
Everyone hates slow websites. So do we.
Make your web apps faster with AppDynamics
Download AppDynamics Lite for free today:
http://p.sf.net/sfu/appdyn_sfd2d_oct
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

Re: [06/10,V2] spi: Add SPI driver for mx233/mx28

[Shubhrajyoti Datta]

On Wed, Aug 1, 2012 at 10:59 AM, Guenter Roeck li...@roeck-us.net wrote:
 On Wed, Aug 01, 2012 at 07:00:54AM +0200, Marek Vasut wrote:
 Dear Shawn Guo,

  On Tue, Jul 31, 2012 at 08:35:59PM -0700, Guenter Roeck wrote:
   I think the call to spi_master_put() triggers the call to
   spi_master_release(). If so, kfree() would not be needed at all, and the
   documentation is wrong.
 
  Also those drivers calling kfree in probe.

 Looks like that to me ...

 Doesn't seem to be far spread, fortunately. Only spi-davinci.c, spi-imx.c, and
 spi-omap2-mcspi.c

I have a  omapsdp I could patch spi-omap2-mcspi.c  file thanks for the catch.

as far as I can see, plus the misleading comment in spi.c.

 Anyone up for writing some patches ? If not, I'll do it.

 Thanks,
 Guenter

 --
 Live Security Virtual Conference
 Exclusive live event will cover all the ways today's security and
 threat landscape has changed and how IT managers can respond. Discussions
 will include endpoint security, mobile security and the latest in malware
 threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/
 ___
 spi-devel-general mailing list
 spi-devel-general@lists.sourceforge.net
 https://lists.sourceforge.net/lists/listinfo/spi-devel-general

--
Live Security Virtual Conference
Exclusive live event will cover all the ways today's security and 
threat landscape has changed and how IT managers can respond. Discussions 
will include endpoint security, mobile security and the latest in malware 
threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

Re: [PATCH] spi: omap2-mcspi: Fix the below warning

[Shubhrajyoti Datta]

On Fri, Jul 20, 2012 at 3:40 PM, Mark Brown
broo...@opensource.wolfsonmicro.com wrote:
 On Thu, Jul 19, 2012 at 11:16:52PM +0530, Shubhrajyoti D wrote:
 The dma_map and dma_unmap should have same parameter
 passed otherwise we get the below warn.

 Applied, thanks.
thanks,

--
Live Security Virtual Conference
Exclusive live event will cover all the ways today's security and 
threat landscape has changed and how IT managers can respond. Discussions 
will include endpoint security, mobile security and the latest in malware 
threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

Re: Linux SPI slave support

[Shubhrajyoti Datta]

On Mon, Jul 16, 2012 at 5:56 AM, Marek Vasut ma...@denx.de wrote:
 Dear Shubhrajyoti Datta,

 Hello,

 On Sat, Jun 30, 2012 at 8:45 AM, Marek Vasut ma...@denx.de wrote:
  Hello,
 
  is there currently any ongoing effort to support SPI slave mode in Linux?
 
  If there is none, could you please share any hints that might help me
  better choose and go in the direction of implementing the SPI slave
  support?

 May be you may want to check the archives.
 You may want to see below before designing.

 http://permalink.gmane.org/gmane.linux.kernel.spi.devel/7495
 [...]

 So, idea V2:

 1) Separate out common parts from struct spi_master
 2) Create struct spi_slave
 2a) Implement spi_slave_send_message for spi_slave
 2b) Implement ? netlink interface to push and pull messages to/from 
 userland ?

 The protocol won't be done in kernel, but completely in userland.

 Is this good approach to take? Or maybe 2b can be replaced by blocking read on
 character device? I think netlink interface might actually be suited quite 
 well
 for this task.


The other option is to have something like a gpio  for synchronization.




 Best regards,
 Marek Vasut

--
Live Security Virtual Conference
Exclusive live event will cover all the ways today's security and 
threat landscape has changed and how IT managers can respond. Discussions 
will include endpoint security, mobile security and the latest in malware 
threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

Re: Linux SPI slave support

[Shubhrajyoti Datta]

On Tue, Jul 17, 2012 at 2:22 PM, Marek Vasut ma...@denx.de wrote:
 Dear Shubhrajyoti Datta,

 On Mon, Jul 16, 2012 at 5:56 AM, Marek Vasut ma...@denx.de wrote:
  Dear Shubhrajyoti Datta,
[..]
 The other option is to have something like a gpio  for synchronization.

 Synchronisation of what exactly? With my hardware (that doesn't exist yet I
 guess), the idea is to simply cross-connect the MISO/MOSI pins and connect the
 CLK signal. Is that possible btw?

IIUC , the clock is to be driven by master. The slave gets the clock.
Master knows when to start and stop the transaction.

However for the slave the options are to
1) Keep listening always.
2) Use something to syncronize( I may have used the word loosely)
master and slave.
So that it doesnt have to listen always.

Btw it is just a suggestion. I am not opposed to any other implementation.

Thanks and Regards,


 Thanks!


--
Live Security Virtual Conference
Exclusive live event will cover all the ways today's security and 
threat landscape has changed and how IT managers can respond. Discussions 
will include endpoint security, mobile security and the latest in malware 
threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

Re: Linux SPI slave support

[Shubhrajyoti Datta]

Hello,

On Sat, Jun 30, 2012 at 8:45 AM, Marek Vasut ma...@denx.de wrote:
 Hello,

 is there currently any ongoing effort to support SPI slave mode in Linux?

 If there is none, could you please share any hints that might help me better
 choose and go in the direction of implementing the SPI slave support?


May be you may want to check the archives.
You may want to see below before designing.

http://permalink.gmane.org/gmane.linux.kernel.spi.devel/7495


 I had this quick idea of simply extending the flags field of struct spi_master
 {} by something like SPI_MASTER_CAN_BE_SWITCHED_TO_SLAVE_MODE (shortened of
 course). Then there'd have to be a function present that can switch the mode,
 also in struct spi_master it seems. And then, any driver willing to use the
 slave support will simply call this switch function. Something amongst those
 lines maybe? Basically, the idea would be to have SPI slave mode drivers and
 master mode drivers using the same API, just make the bus configured
 differently.

 Please advise. Thanks in advance!

 Best regards,
 Marek Vasut

 --
 Live Security Virtual Conference
 Exclusive live event will cover all the ways today's security and
 threat landscape has changed and how IT managers can respond. Discussions
 will include endpoint security, mobile security and the latest in malware
 threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/
 ___
 spi-devel-general mailing list
 spi-devel-general@lists.sourceforge.net
 https://lists.sourceforge.net/lists/listinfo/spi-devel-general

--
Live Security Virtual Conference
Exclusive live event will cover all the ways today's security and 
threat landscape has changed and how IT managers can respond. Discussions 
will include endpoint security, mobile security and the latest in malware 
threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

Re: [PATCH] spi: add spi controller master driver for Blackfin 6xx processor

[Shubhrajyoti Datta]

Hi Scott,
Some minor comments?

On Tue, Jun 5, 2012 at 12:51 AM, Scott Jiang
scott.jiang.li...@gmail.com wrote:
 New spi controller is integrated into Blackfin 6xx processor.
 Comparing to bf5xx spi controller, we support 32 bits word size
 and independent receive and transmit DMA channels now.
 Also mode 0 and 2 (CPHA = 0) can get fully supported
 becasue cs line may be controlled by the software.
Snip

how about using spi core queuing?
 +
 +       status = bfin_spi_start_queue(drv_data);
 +       if (status != 0) {
 +               dev_err(dev, problem starting queue\n);
 +               goto err_destroy_queue;
 +       }
 +
 +       bfin_write(drv_data-regs-control, SPI_CTL_MSTR | SPI_CTL_CPHA);
 +       bfin_write(drv_data-regs-ssel, 0xFE00);
 +       bfin_write(drv_data-regs-delay, 0x0);
 +
 +       /* Register with the SPI framework */
 +       platform_set_drvdata(pdev, drv_data);
 +       status = spi_register_master(master);
 +       if (status != 0) {
 +               dev_err(dev, problem registering spi master\n);
 +               goto err_free_peripheral;
 +       }
 +
 +       dev_info(dev, bfin-spi probe success\n);
 +       return status;
 +
 +err_destroy_queue:
 +       bfin_spi_destroy_queue(drv_data);
 +err_free_peripheral:
 +       peripheral_free_list(drv_data-pin_req);
 +err_free_rx_dma:
 +       free_dma(drv_data-rx_dma);
 +err_free_tx_dma:
 +       free_dma(drv_data-tx_dma);
 +err_iounmap:
 +       iounmap(drv_data-regs);
 +err_put_master:
 +       spi_master_put(master);
 +
 +       return status;
 +}
 +
 +/* stop hardware and remove the driver */
 +static int __devexit bfin_spi_remove(struct platform_device *pdev)
 +{
 +       struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
 +
 +       if (!drv_data)
 +               return 0;
 +
 +       /* Remove the queue */
 +       bfin_spi_destroy_queue(drv_data);
 +
 +       /* Disable the SSP at the peripheral and SOC level */
 +       bfin_spi_disable(drv_data);
 +
 +       peripheral_free_list(drv_data-pin_req);
 +       free_dma(drv_data-rx_dma);
 +       free_dma(drv_data-tx_dma);
 +       iounmap(drv_data-regs);
 +
 +       /* Disconnect from the SPI framework */
 +       spi_unregister_master(drv_data-master);
 +       spi_master_put(drv_data-master);
 +       /* Prevent double remove */
 +       platform_set_drvdata(pdev, NULL);
 +
 +       return 0;
 +}
 +
 +#ifdef CONFIG_PM
 +static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state)
 +{
 +       struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
 +       int status = 0;
 +
 +       status = bfin_spi_stop_queue(drv_data);
 +       if (status != 0)
 +               return status;
 +
 +       drv_data-control = bfin_read(drv_data-regs-control);
 +       drv_data-ssel = bfin_read(drv_data-regs-ssel);
 +
 +       bfin_write(drv_data-regs-control, SPI_CTL_MSTR | SPI_CTL_CPHA);
 +       bfin_write(drv_data-regs-ssel, 0xFE00);
 +
 +       return 0;
 +}
 +
 +static int bfin_spi_resume(struct platform_device *pdev)
 +{
 +       struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
 +       int status = 0;
 +
 +       bfin_write(drv_data-regs-control, drv_data-control);
 +       bfin_write(drv_data-regs-ssel, drv_data-ssel);
 +
 +       /* Start the queue running */
 +       status = bfin_spi_start_queue(drv_data);
 +       if (status != 0) {
 +               dev_err(pdev-dev, problem starting queue (%d)\n, status);
 +               return status;
 +       }
 +
 +       return 0;
 +}
 +#else
 +#define bfin_spi_suspend NULL
 +#define bfin_spi_resume NULL
 +#endif /* CONFIG_PM */
 +
 +MODULE_ALIAS(platform:bfin-spi);
 +static struct platform_driver bfin_spi_driver = {
 +       .driver = {
 +               .name   = bfin-spi,
 +               .owner  = THIS_MODULE,
 +       },
 +       .suspend        = bfin_spi_suspend,
 +       .resume         = bfin_spi_resume,

Can we move to dev pm ops instead?

--
Live Security Virtual Conference
Exclusive live event will cover all the ways today's security and 
threat landscape has changed and how IT managers can respond. Discussions 
will include endpoint security, mobile security and the latest in malware 
threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

Re: [PATCH] spi/omap2-mcspi: convert to the pump message infrastructure

[Shubhrajyoti Datta]

Hi Linus,

On Tue, May 15, 2012 at 1:42 AM, Linus Walleij linus.wall...@linaro.org wrote:
 On Thu, May 10, 2012 at 2:57 PM, Shubhrajyoti D shubhrajy...@ti.com wrote:

 This patch converts the OMAP SPI driver to use the SPI infrastructure
 pump message queue.Also fixes the below warning.
 master is unqueued, this is deprecated

 Signed-off-by: Shubhrajyoti D shubhrajy...@ti.com

 Final version of the patch?
Lest someone has comments.

 Acked-by: Linus Walleij linus.wall...@linaro.org
Thanks.


 Yours,
 Linus Walleij
 --
 To unsubscribe from this list: send the line unsubscribe linux-kernel in
 the body of a message to majord...@vger.kernel.org
 More majordomo info at  http://vger.kernel.org/majordomo-info.html
 Please read the FAQ at  http://www.tux.org/lkml/

--
Live Security Virtual Conference
Exclusive live event will cover all the ways today's security and 
threat landscape has changed and how IT managers can respond. Discussions 
will include endpoint security, mobile security and the latest in malware 
threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

Re: [PATCH] spi/pl022: Fix error print while setting bits/word on pl022

[Shubhrajyoti Datta]

Hi Vinit ,
A minor comment/ suggestion.

On Tue, Apr 17, 2012 at 11:28 AM, Vinit Shenoy vinit.she...@st.com wrote:
 pl022 ssp controller supports word lengths from 4 to 16 bits.
 The kernel error message says:
 a standard pl022 can only handle 1 = n = 16 bit words.

 Fixed above range to 4 = n = 16.

 Signed-off-by: Vinit Shenoy vinit.she...@st.com
 ---
  drivers/spi/spi-pl022.c |    2 +-
  1 files changed, 1 insertions(+), 1 deletions(-)

 diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c
 index 09c925a..905752f 100644
 --- a/drivers/spi/spi-pl022.c
 +++ b/drivers/spi/spi-pl022.c
 @@ -1848,7 +1848,7 @@ static int pl022_setup(struct spi_device *spi)
                                illegal data size for this controller!\n);
                        dev_err(spi-dev,
                                a standard pl022 can only handle 
 -                               1 = n = 16 bit words\n);
 +                               4 = n = 16 bit words\n);
However this print will not executed for sizes  4
Can we have something like. [1]


                        status = -ENOTSUPP;
                        goto err_config_params;
                }
 --
 1.7.3.4


 --
 Better than sec? Nothing is better than sec when it comes to
 monitoring Big Data applications. Try Boundary one-second
 resolution app monitoring today. Free.
 http://p.sf.net/sfu/Boundary-dev2dev
 ___
 spi-devel-general mailing list
 spi-devel-general@lists.sourceforge.net
 https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[1]

diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c
index 09c925a..6444a5e 100644
--- a/drivers/spi/spi-pl022.c
+++ b/drivers/spi/spi-pl022.c
@@ -1823,11 +1823,7 @@ static int pl022_setup(struct spi_device *spi)
} else
chip-cs_control = chip_info-cs_control;

-   if (bits = 3) {
-   /* PL022 doesn't support less than 4-bits */
-   status = -ENOTSUPP;
-   goto err_config_params;
-   } else if (bits = 8) {
+   if (bits = 8  bits  3) {
dev_dbg(spi-dev, 4 = n =8 bits per word\n);
chip-n_bytes = 1;
chip-read = READING_U8;
@@ -1848,7 +1844,7 @@ static int pl022_setup(struct spi_device *spi)
illegal data size for this controller!\n);
dev_err(spi-dev,
a standard pl022 can only handle 
-   1 = n = 16 bit words\n);
+   4 = n = 16 bit words\n);
status = -ENOTSUPP;
goto err_config_params;
}

--
Better than sec? Nothing is better than sec when it comes to
monitoring Big Data applications. Try Boundary one-second 
resolution app monitoring today. Free.
http://p.sf.net/sfu/Boundary-dev2dev
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

Re: [PATCH V2] spi/pl022: Fix range checking for bits per word

[Shubhrajyoti Datta]

Hi Vinit,

Looks OK to me ,

On Tue, Apr 17, 2012 at 12:40 PM, Vinit Shenoy vinit.she...@st.com wrote:
 pl022 ssp controller supports word lengths from 4 to 16 (or 32) bits.
 Currently implemented checks were incorrect. It has following check

 if (pl022-vendor-max_bpw = 32)

 which must be checking for =.

 Also error print message is incorrect, that prints range is from 1 to
 16.

 Fix both these issues.

Thanks ,


 Signed-off-by: Vinit Shenoy vinit.she...@st.com
 ---
 V1-V2:
 - Fixed the check:
        if (pl022-vendor-max_bpw = 32)
 - Re-written complete range check logic.
I think the patches could be split as one is a fix the other corrects the
error msg.

Nit:
Also the changlogs spell the issue and not the solution.
I think that could be improved.
Other than  that feel free to add
Reviewed-by: Shubhrajyoti D shubhrajy...@ti.com

If you like.

  drivers/spi/spi-pl022.c |   25 +
  1 files changed, 9 insertions(+), 16 deletions(-)

 diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c
 index 09c925a..1ead49d 100644
 --- a/drivers/spi/spi-pl022.c
 +++ b/drivers/spi/spi-pl022.c
 @@ -1823,9 +1823,12 @@ static int pl022_setup(struct spi_device *spi)
        } else
                chip-cs_control = chip_info-cs_control;

 -       if (bits = 3) {
 -               /* PL022 doesn't support less than 4-bits */
 +       /* Check bits per word with vendor specific range */
 +       if ((bits = 3) || (bits  pl022-vendor-max_bpw)) {
                status = -ENOTSUPP;
 +               dev_err(spi-dev, illegal data size for this 
 controller!\n);
 +               dev_err(spi-dev, This controller can only handle 4 = n = 
 %d bit words\n,
 +                               pl022-vendor-max_bpw);
                goto err_config_params;
        } else if (bits = 8) {
                dev_dbg(spi-dev, 4 = n =8 bits per word\n);
 @@ -1838,20 +1841,10 @@ static int pl022_setup(struct spi_device *spi)
                chip-read = READING_U16;
                chip-write = WRITING_U16;
        } else {
 -               if (pl022-vendor-max_bpw = 32) {
 -                       dev_dbg(spi-dev, 17 = n = 32 bits per word\n);
 -                       chip-n_bytes = 4;
 -                       chip-read = READING_U32;
 -                       chip-write = WRITING_U32;
 -               } else {
 -                       dev_err(spi-dev,
 -                               illegal data size for this controller!\n);
 -                       dev_err(spi-dev,
 -                               a standard pl022 can only handle 
 -                               1 = n = 16 bit words\n);
 -                       status = -ENOTSUPP;
 -                       goto err_config_params;
 -               }
 +               dev_dbg(spi-dev, 17 = n = 32 bits per word\n);
 +               chip-n_bytes = 4;
 +               chip-read = READING_U32;
 +               chip-write = WRITING_U32;
        }

        /* Now Initialize all register settings required for this chip */
 --
 1.7.3.4


--
Better than sec? Nothing is better than sec when it comes to
monitoring Big Data applications. Try Boundary one-second 
resolution app monitoring today. Free.
http://p.sf.net/sfu/Boundary-dev2dev
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

Re: [PATCHv3 0/3] spi: omap2-mcspi: driver updates

[Shubhrajyoti Datta]

Hi Grant

On Tue, Apr 3, 2012 at 1:10 AM, Grant Likely grant.lik...@secretlab.ca wrote:
 On Sat, 31 Mar 2012 17:06:55 +0530, Shubhrajyoti D shubhrajy...@ti.com 
 wrote:
 The patch series does the following cleanups
 - Makes the driver use autosuspend
 - Folds Benoit's bus_num removal patch in the series
 - The tmp variable is used to write this can be optimised
  as it is not needed if the value is directly written.
  Acknowledge  Tarun for the suggestion.

 This is also available through
 git     : git://gitorious.org/linus-tree/linus-tree.git
 branch  : spi_next

 Rebased to Grant's spi/next branch.

 Merged, thanks.
Thanks ,


 BTW, it's easier to pull if you put the branch after the git URL (I
 can cut and paste all at once):

        git://gitorious.org/linus-tree/linus-tree.git spi_next

 git request-pull can be your friend here.

OK good idea will do that.

--
Better than sec? Nothing is better than sec when it comes to
monitoring Big Data applications. Try Boundary one-second 
resolution app monitoring today. Free.
http://p.sf.net/sfu/Boundary-dev2dev
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

Re: [PATCH 0/5] spi: omap2-mcspi: driver updates

[Shubhrajyoti Datta]

Hi Grant,

On Wed, Mar 28, 2012 at 3:28 AM, Grant Likely grant.lik...@secretlab.ca wrote:
 On Mon, 26 Mar 2012 19:14:35 +0530, Shubhrajyoti D shubhrajy...@ti.com 
 wrote:
 The patch series does the following cleanups
 - Converts the spi to module_platform_driver
 - Use the devm functions so that the freeing need not
   be done in the driver.
 - Makes the driver use autosuspend
 - Folds Benoit's bus_num removal patch in the series

 Changes from the previous version
 - Makes the driver use autosuspend
 - Folds Benoit's bus_num removal patch in the series


 This is also available through
 git     : git://gitorious.org/linus-tree/linus-tree.git
 branch  : spi

 Hi Shubhrajyoti,

 I'll queue these ones up for v3.5 unless you make the argument that
 they are bug fixes that must go into v3.4.

No  thats fine if targeted for v3.5 .
Thanks,


 g.
 --
 To unsubscribe from this list: send the line unsubscribe linux-kernel in
 the body of a message to majord...@vger.kernel.org
 More majordomo info at  http://vger.kernel.org/majordomo-info.html
 Please read the FAQ at  http://www.tux.org/lkml/

--
This SF email is sponsosred by:
Try Windows Azure free for 90 days Click Here 
http://p.sf.net/sfu/sfd2d-msazure
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

Re: [PATCH] spi-imx: Remove duplicate spi_imx_data definition

[Shubhrajyoti Datta]

Hi Fabio,

On Mon, Mar 26, 2012 at 11:43 PM, Fabio Estevam
fabio.este...@freescale.com wrote:
 Structure struct spi_imx_data is defined twice.

 Remove one of its definition.

 Signed-off-by: Fabio Estevam fabio.este...@freescale.com
 ---
  drivers/spi/spi-imx.c |   20 +---
  1 files changed, 9 insertions(+), 11 deletions(-)

 diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
 index 31054e3..f1f6700 100644
 --- a/drivers/spi/spi-imx.c
 +++ b/drivers/spi/spi-imx.c
 @@ -68,17 +68,6 @@ enum spi_imx_devtype {
        IMX51_ECSPI,    /* ECSPI on i.mx51 and later */
  };

 -struct spi_imx_data;
 -
 -struct spi_imx_devtype_data {
 -       void (*intctrl)(struct spi_imx_data *, int);
 -       int (*config)(struct spi_imx_data *, struct spi_imx_config *);
 -       void (*trigger)(struct spi_imx_data *);
 -       int (*rx_available)(struct spi_imx_data *);
 -       void (*reset)(struct spi_imx_data *);
 -       enum spi_imx_devtype devtype;
 -};

Is this change intentional

 -
  struct spi_imx_data {
        struct spi_bitbang bitbang;

 @@ -99,6 +88,15 @@ struct spi_imx_data {
        int chipselect[0];
  };

 +struct spi_imx_devtype_data {
 +       void (*intctrl)(struct spi_imx_data *, int);
 +       int (*config)(struct spi_imx_data *, struct spi_imx_config *);
 +       void (*trigger)(struct spi_imx_data *);
 +       int (*rx_available)(struct spi_imx_data *);
 +       void (*reset)(struct spi_imx_data *);
 +       enum spi_imx_devtype devtype;
 +};
 +
  static inline int is_imx27_cspi(struct spi_imx_data *d)
  {
        return d-devtype_data-devtype == IMX27_CSPI;
 --
 1.7.1



 --
 This SF email is sponsosred by:
 Try Windows Azure free for 90 days Click Here
 http://p.sf.net/sfu/sfd2d-msazure
 ___
 spi-devel-general mailing list
 spi-devel-general@lists.sourceforge.net
 https://lists.sourceforge.net/lists/listinfo/spi-devel-general

--
This SF email is sponsosred by:
Try Windows Azure free for 90 days Click Here 
http://p.sf.net/sfu/sfd2d-msazure
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

Re: [PATCH v3 6/6] mfd: mc13xxx: Add i2c driver

[Shubhrajyoti Datta]

Hi Marc,

On Thu, Mar 15, 2012 at 2:13 AM, Marc Reilly m...@cpdesign.com.au wrote:
 Adds support for mc13xxx family ICs connected via i2c.

 Signed-off-by: Marc Reilly m...@cpdesign.com.au
 ---
snip

 +static int mc13xxx_i2c_probe(struct i2c_client *client,
 +               const struct i2c_device_id *id)
 +{
 +       const struct of_device_id *of_id;
 +       struct i2c_driver *idrv = to_i2c_driver(client-dev.driver);
 +       struct mc13xxx *mc13xxx;
 +       struct mc13xxx_platform_data *pdata = dev_get_platdata(client-dev);
 +       int ret;
 +
 +       of_id = of_match_device(mc13xxx_dt_ids, client-dev);
 +       if (of_id)
 +               idrv-id_table =
 +                       mc13xxx_i2c_device_id[(enum mc13xxx_id) of_id-data];
 +
 +       mc13xxx = kzalloc(sizeof(*mc13xxx), GFP_KERNEL);
 +       if (!mc13xxx)
 +               return -ENOMEM;
 +
 +       dev_set_drvdata(client-dev, mc13xxx);
 +
 +       mc13xxx-dev = client-dev;
 +       mutex_init(mc13xxx-lock);
 +
 +       mc13xxx-regmap = regmap_init_i2c(client, mc13xxx_regmap_i2c_config);
 +       if (IS_ERR(mc13xxx-regmap)) {
 +               ret = PTR_ERR(mc13xxx-regmap);
 +               dev_err(mc13xxx-dev, Failed to initialize register map: 
 %d\n,
 +                               ret);
 +               dev_set_drvdata(client-dev, NULL);
Are we  leaking mc13xxx here
May be you can consider using devm* functions ?

  +               return ret;
 +       }
 +

--
This SF email is sponsosred by:
Try Windows Azure free for 90 days Click Here 
http://p.sf.net/sfu/sfd2d-msazure
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

Re: [PATCH v2] spi: Add SuperH HSPI prototype driver

[Shubhrajyoti Datta]

Hi Kuninori,

On Fri, Jan 6, 2012 at 11:30 AM, Kuninori Morimoto
kuninori.morimoto...@renesas.com wrote:
 This patch adds SuperH HSPI driver.
 It is still prototype driver, but has enough function at this point.

 Signed-off-by: Kuninori Morimoto kuninori.morimoto...@renesas.com
 ---
 v1 - v2

 - mdelay() - msleep()
 - typo fix
 - sizeof(struct hspi_priv) - sizeof(*hspi)
 - remove devname
 - use dev_err() instead of printk(KERN_ERR, )
 - modiry spi_unregister_master() timing

  drivers/spi/Kconfig         |    6 +
  drivers/spi/Makefile        |    1 +
  drivers/spi/spi-sh-hspi.c   |  363 
 +++
  include/linux/spi/sh_hspi.h |   34 
  4 files changed, 404 insertions(+), 0 deletions(-)
  create mode 100644 drivers/spi/spi-sh-hspi.c
  create mode 100644 include/linux/spi/sh_hspi.h

 diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
 index a1fd73d..33bb33e 100644
 --- a/drivers/spi/Kconfig
 +++ b/drivers/spi/Kconfig
 @@ -325,6 +325,12 @@ config SPI_SH_SCI
        help
          SPI driver for SuperH SCI blocks.

 +config SPI_SH_HSPI
 +       tristate SuperH HSPI controller
 +       depends on ARCH_SHMOBILE
 +       help
 +         SPI driver for SuperH HSPI blocks.
 +
  config SPI_STMP3XXX
        tristate Freescale STMP37xx/378x SPI/SSP controller
        depends on ARCH_STMP3XXX  SPI_MASTER
 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
 index 61c3261..d65e059 100644
 --- a/drivers/spi/Makefile
 +++ b/drivers/spi/Makefile
 @@ -51,6 +51,7 @@ obj-$(CONFIG_SPI_S3C64XX)             += spi-s3c64xx.o
  obj-$(CONFIG_SPI_SH)                   += spi-sh.o
  obj-$(CONFIG_SPI_SH_MSIOF)             += spi-sh-msiof.o
  obj-$(CONFIG_SPI_SH_SCI)               += spi-sh-sci.o
 +obj-$(CONFIG_SPI_SH_HSPI)              += spi-sh-hspi.o
  obj-$(CONFIG_SPI_STMP3XXX)             += spi-stmp.o
  obj-$(CONFIG_SPI_TEGRA)                        += spi-tegra.o
  obj-$(CONFIG_SPI_TI_SSP)               += spi-ti-ssp.o
 diff --git a/drivers/spi/spi-sh-hspi.c b/drivers/spi/spi-sh-hspi.c
 new file mode 100644
 index 000..f527d24
 --- /dev/null
 +++ b/drivers/spi/spi-sh-hspi.c
 @@ -0,0 +1,363 @@
 +/*
 + * SuperH HSPI bus driver
 + *
 + * Copyright (C) 2011  Kuninori Morimoto
 + *
 + * Based on spi-sh.c:
 + * Based on pxa2xx_spi.c:
 + * Copyright (C) 2011 Renesas Solutions Corp.
 + * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
 + *
 + * This program is free software; you can redistribute it and/or modify
 + * it under the terms of the GNU General Public License as published by
 + * the Free Software Foundation; version 2 of the License.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License
 + * along with this program; if not, write to the Free Software
 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 + *
 + */
 +#include linux/module.h
 +#include linux/kernel.h
 +#include linux/timer.h
 +#include linux/delay.h
 +#include linux/list.h
 +#include linux/workqueue.h
 +#include linux/interrupt.h
 +#include linux/platform_device.h
 +#include linux/pm_runtime.h
 +#include linux/io.h
 +#include linux/spi/spi.h
 +#include linux/spi/sh_hspi.h
 +
 +#define SPCR   0x00
 +#define SPSR   0x04
 +#define SPSCR  0x08
 +#define SPTBR  0x0C
 +#define SPRBR  0x10
 +#define SPCR2  0x14
 +
 +/* SPSR */
 +#define RXFL   (1  2)
 +
 +#define hspi2info(h)   (h-dev-platform_data)
 +
 +struct hspi_priv {
 +       void __iomem *addr;
 +       struct spi_master *master;
 +       struct list_head queue;
 +       struct workqueue_struct *workqueue;
 +       struct work_struct ws;
 +       struct device *dev;
 +       spinlock_t lock;
 +};
 +
 +/*
 + *             basic function
 + */
 +static void hspi_write(struct hspi_priv *hspi, int reg, u32 val)
 +{
 +       iowrite32(val, hspi-addr + reg);
 +}
 +
 +static u8 hspi_read(struct hspi_priv *hspi, int reg)
 +{
 +       return (u8)ioread32(hspi-addr + reg);

You  do a ioread32 and then typecast to u8 Didnt undwerstand?

 +}
 +
 +/*
 + *             transfer function
 + */
 +static int hspi_status_check_timeout(struct hspi_priv *hspi, u32 mask, u32 
 val)
 +{
 +       int t = 256;
 +
 +       while (t--) {
 +               if ((mask  hspi_read(hspi, SPSR)) == val)
 +                       return 0;
 +
 +               msleep(10);
 +       }
 +
 +       dev_err(hspi-dev, timeout\n);
 +       return -ETIMEDOUT;
 +}
 +
 +static int hspi_push(struct hspi_priv *hspi, struct spi_message *msg,
 +                    struct spi_transfer *t)
 +{
 +       int i, ret;
 +       u8 *data = (u8 *)t-tx_buf;
 +
 +       /*
 +        * FIXME
 +        * very simple, but polling transfer
 +        */
 +       for (i = 0; i  t-len; i++) {
 +               /* 

Re: [PATCH 9/9 v3] spi: add Broadcom BCM63xx SPI controller driver

[Shubhrajyoti Datta]

Hi Florian,

On Tue, Jan 31, 2012 at 7:40 PM, Florian Fainelli flor...@openwrt.org wrote:
 This patch adds support for the SPI controller found on the Broadcom BCM63xx
 SoCs.

 Signed-off-by: Tanguy Bouzeloc tanguy.bouze...@efixo.com
 Signed-off-by: Florian Fainelli flor...@openwrt.org
 ---
 Changes since v2:
 - reworked bcm63xx_spi_setup_transfer to choose closest spi transfer
  frequency
 - removed invalid 25Mhz frequency
 - fixed some minor checkpatch issues

 Changes since v1:
 - switched to the devm_* API which frees resources automatically
 - switched to dev_pm_ops
 - use module_platform_driver
 - remove MODULE_VERSION()
 - fixed return value when clock is not present using PTR_ERR()
 - fixed probe() error path to disable clock in case of failure

  drivers/spi/Kconfig       |    6 +
  drivers/spi/Makefile      |    1 +
  drivers/spi/spi-bcm63xx.c |  486 
 +
  3 files changed, 493 insertions(+), 0 deletions(-)
  create mode 100644 drivers/spi/spi-bcm63xx.c

 diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
 index 3f9a47e..16818ac 100644
 --- a/drivers/spi/Kconfig
 +++ b/drivers/spi/Kconfig
 @@ -94,6 +94,12 @@ config SPI_AU1550
          If you say yes to this option, support will be included for the
          PSC SPI controller found on Au1550, Au1200 and Au1300 series.

 +config SPI_BCM63XX
 +       tristate Broadcom BCM63xx SPI controller
 +       depends on BCM63XX
 +       help
 +          Enable support for the SPI controller on the Broadcom BCM63xx SoCs.
 +
  config SPI_BITBANG
        tristate Utilities for Bitbanging SPI masters
        help
 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
 index 61c3261..be38f73 100644
 --- a/drivers/spi/Makefile
 +++ b/drivers/spi/Makefile
 @@ -14,6 +14,7 @@ obj-$(CONFIG_SPI_ALTERA)              += spi-altera.o
  obj-$(CONFIG_SPI_ATMEL)                        += spi-atmel.o
  obj-$(CONFIG_SPI_ATH79)                        += spi-ath79.o
  obj-$(CONFIG_SPI_AU1550)               += spi-au1550.o
 +obj-$(CONFIG_SPI_BCM63XX)              += spi-bcm63xx.o
  obj-$(CONFIG_SPI_BFIN)                 += spi-bfin5xx.o
  obj-$(CONFIG_SPI_BFIN_SPORT)           += spi-bfin-sport.o
  obj-$(CONFIG_SPI_BITBANG)              += spi-bitbang.o
 diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c
 new file mode 100644
 index 000..eba8505
 --- /dev/null
 +++ b/drivers/spi/spi-bcm63xx.c
 @@ -0,0 +1,486 @@
 +/*
 + * Broadcom BCM63xx SPI controller support
 + *
 + * Copyright (C) 2009-2011 Florian Fainelli flor...@openwrt.org
 + * Copyright (C) 2010 Tanguy Bouzeloc tanguy.bouze...@efixo.com
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License
 + * as published by the Free Software Foundation; either version 2
 + * of the License, or (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License
 + * along with this program; if not, write to the
 + * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
 + */
 +
 +#include linux/kernel.h
 +#include linux/init.h
 +#include linux/clk.h
 +#include linux/io.h
 +#include linux/module.h
 +#include linux/platform_device.h
 +#include linux/delay.h
 +#include linux/interrupt.h
 +#include linux/spi/spi.h
 +#include linux/completion.h
 +#include linux/err.h
 +
 +#include bcm63xx_dev_spi.h
 +
 +#define PFX            KBUILD_MODNAME
 +#define DRV_VER                0.1.2
 +
 +struct bcm63xx_spi {
 +       spinlock_t              lock;
 +       int                     stopping;
 +       struct completion       done;
 +
 +       void __iomem            *regs;
 +       int                     irq;
 +
 +       /* Platform data */
 +       u32                     speed_hz;
 +       unsigned                fifo_size;
 +
 +       /* Data buffers */
 +       const unsigned char     *tx_ptr;
 +       unsigned char           *rx_ptr;
 +
 +       /* data iomem */
 +       u8 __iomem              *tx_io;
 +       const u8 __iomem        *rx_io;
 +
 +       int                     remaining_bytes;
 +
 +       struct clk              *clk;
 +       struct platform_device  *pdev;
 +};
 +
 +static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
 +                               unsigned int offset)
 +{
 +       return bcm_readw(bs-regs + bcm63xx_spireg(offset));

are you sure it should be bcm_readw

 +}
 +
 +static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
 +                               unsigned int offset)
 +{
 +       return bcm_readw(bs-regs + bcm63xx_spireg(offset));
 +}
 +

--
Keep Your Developer 

Re: [PATCH 1/3] spi/s3c64xx: Log error interrupts

[Shubhrajyoti Datta]

Hi Mark,

On Mon, Jan 30, 2012 at 3:10 AM, Mark Brown
broo...@opensource.wolfsonmicro.com wrote:
 On Sat, Jan 28, 2012 at 10:30:36PM +0530, Shubhrajyoti Datta wrote:

 Please delete irrelevant context from your replies.

  +   ret = request_irq(irq, s3c64xx_spi_irq, 0, spi-s3c64xx, sdd);

 Could we have a threaded irq instead and there are prints and that may get
 executed in interrupt context.

 So, clearly we *could*.  However I think that's not going to be as
 helpful.  These errors are never supposed to happen (and if they do
 indicate a fairly serious problem) so the performance impact shouldn't
 be our primary concern and if they do happen then my suspicion is that
 the timing information will be very important.  I expect that knowing
 exactly when the error occurred is likely to help diagnose what caused
 it by virtue of knowing what other things were going on in the system at
 that time.
I agree .

My only concern was that incase someone wants to add prints in the irq
that may be handy.
However as you rightly pointed that timing is surely to be more of a concern.
Thanks for the explanation.

--
Keep Your Developer Skills Current with LearnDevNow!
The most comprehensive online learning library for Microsoft developers
is just $99.99! Visual Studio, SharePoint, SQL - plus HTML5, CSS3, MVC3,
Metro Style Apps, more. Free future releases when you subscribe now!
http://p.sf.net/sfu/learndevnow-d2d
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

Re: [PATCH 1/3] spi/s3c64xx: Log error interrupts

[Shubhrajyoti Datta]

Hi Mark,
Some minor doubts/ questions.

On 1/21/12, Mark Brown broo...@opensource.wolfsonmicro.com wrote:
 Although the hardware supports interrupts we're not currently using them
 at all since for small transfers the overhead is greater than that for
 busy waiting and for large transfers we have interrupts from the DMA.
 This means that if the hardware reports an error (especially one which
 might not stall transfer) we might miss it.

 Take a first pass at dealing with such errors by enabling the interrupt
 if we can and logging the errors if they happen. Ideally we'd report the
 error via the affected transfer but since we're in master mode it's very
 difficult to trigger errors at present and this code is much simpler.

 Signed-off-by: Mark Brown broo...@opensource.wolfsonmicro.com
 Acked-by: Linus Walleij linus.wall...@linaro.org
 ---
  drivers/spi/spi-s3c64xx.c |   57
 +++-
  1 files changed, 55 insertions(+), 2 deletions(-)

 diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
 index 019a716..d56066b 100644
 --- a/drivers/spi/spi-s3c64xx.c
 +++ b/drivers/spi/spi-s3c64xx.c
 @@ -20,6 +20,7 @@
  #include linux/init.h
  #include linux/module.h
  #include linux/workqueue.h
 +#include linux/interrupt.h
  #include linux/delay.h
  #include linux/clk.h
  #include linux/dma-mapping.h
 @@ -153,6 +154,7 @@ struct s3c64xx_spi_dma_data {
   * @tx_dmach: Controller's DMA channel for Tx.
   * @sfr_start: BUS address of SPI controller regs.
   * @regs: Pointer to ioremap'ed controller registers.
 + * @irq: interrupt
   * @xfer_completion: To indicate completion of xfer task.
   * @cur_mode: Stores the active configuration of the controller.
   * @cur_bpw: Stores the active bits per word settings.
 @@ -930,6 +932,33 @@ setup_exit:
   return err;
  }

 +static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
 +{
 + struct s3c64xx_spi_driver_data *sdd = data;
 + struct spi_master *spi = sdd-master;
 + unsigned int val;
 +
 + val = readl(sdd-regs + S3C64XX_SPI_PENDING_CLR);
 +
 + val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
 + S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
 + S3C64XX_SPI_PND_TX_OVERRUN_CLR |
 + S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
 +
 + writel(val, sdd-regs + S3C64XX_SPI_PENDING_CLR);
 +
 + if (val  S3C64XX_SPI_PND_RX_OVERRUN_CLR)
 + dev_err(spi-dev, RX overrun\n);
 + if (val  S3C64XX_SPI_PND_RX_UNDERRUN_CLR)
 + dev_err(spi-dev, RX underrun\n);
 + if (val  S3C64XX_SPI_PND_TX_OVERRUN_CLR)
 + dev_err(spi-dev, TX overrun\n);
 + if (val  S3C64XX_SPI_PND_TX_UNDERRUN_CLR)
 + dev_err(spi-dev, TX underrun\n);
 +
 + return IRQ_HANDLED;
 +}
 +
  static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int
 channel)
  {
   struct s3c64xx_spi_info *sci = sdd-cntrlr_info;
 @@ -970,7 +999,8 @@ static int __init s3c64xx_spi_probe(struct
 platform_device *pdev)
   struct s3c64xx_spi_driver_data *sdd;
   struct s3c64xx_spi_info *sci;
   struct spi_master *master;
 - int ret;
 + int ret, irq;
 + char clk_name[16];

   if (pdev-id  0) {
   dev_err(pdev-dev,
 @@ -1010,6 +1040,12 @@ static int __init s3c64xx_spi_probe(struct
 platform_device *pdev)
   return -ENXIO;
   }

 + irq = platform_get_irq(pdev, 0);
 + if (irq  0) {
 + dev_warn(pdev-dev, Failed to get IRQ: %d\n, irq);
 + return irq;
 + }
 +
   master = spi_alloc_master(pdev-dev,
   sizeof(struct s3c64xx_spi_driver_data));
   if (master == NULL) {
 @@ -1104,10 +1140,21 @@ static int __init s3c64xx_spi_probe(struct
 platform_device *pdev)
   INIT_WORK(sdd-work, s3c64xx_spi_work);
   INIT_LIST_HEAD(sdd-queue);

 + ret = request_irq(irq, s3c64xx_spi_irq, 0, spi-s3c64xx, sdd);

Could we have a threaded irq instead and there are prints and that may get
executed in interrupt context.

 + if (ret != 0) {
 + dev_err(pdev-dev, Failed to request IRQ %d: %d\n,
 + irq, ret);
 + goto err8;
 + }
 +
 + writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
 +S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
 +sdd-regs + S3C64XX_SPI_INT_EN);
 +
   if (spi_register_master(master)) {
   dev_err(pdev-dev, cannot register SPI master\n);
   ret = -EBUSY;
 - goto err8;
 + goto err9;
   }

   dev_dbg(pdev-dev, Samsung SoC SPI Driver loaded for Bus SPI-%d 
 @@ -1119,6 +1166,8 @@ static int __init s3c64xx_spi_probe(struct
 platform_device *pdev)

   return 0;

 +err9:
 + free_irq(irq, sdd);
  err8:
   destroy_workqueue(sdd-workqueue);
  err7:
 @@ -1157,6 +1206,10 @@ static int s3c64xx_spi_remove(struct platform_device
 *pdev)

   spi_unregister_master(master);

 + writel(0, sdd-regs + 

Re: [PATCH spi-next] spi: add Broadcom BCM63xx SPI controller driver

[Shubhrajyoti Datta]

Hi Florian,

On Tue, Nov 22, 2011 at 1:46 AM, Florian Fainelli flor...@openwrt.org wrote:
 This patch adds support for the SPI controller found on the Broadcom BCM63xx
 SoCs.

 Signed-off-by: Tanguy Bouzeloc tanguy.bouze...@efixo.com
 Signed-off-by: Florian Fainelli flor...@openwrt.org
 ---
 The platform related changes have been submitted on the linux-mips ml:
 http://www.linux-mips.org/archives/linux-mips/2011-11/msg00547.html

 Ralf, if Grant is okay with that patch, it probably makes sense to merge this
 controller via your tree since it depends on the arch/mips/bcm63xx knobs.

  drivers/spi/Kconfig       |    6 +
  drivers/spi/Makefile      |    1 +
  drivers/spi/spi-bcm63xx.c |  494 
 +
  3 files changed, 501 insertions(+), 0 deletions(-)
  create mode 100644 drivers/spi/spi-bcm63xx.c

 diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
 index 52e2900..8aecc4e 100644
 --- a/drivers/spi/Kconfig
 +++ b/drivers/spi/Kconfig
 @@ -94,6 +94,12 @@ config SPI_AU1550
          If you say yes to this option, support will be included for the
          Au1550 SPI controller (may also work with Au1200,Au1210,Au1250).

 +config SPI_BCM63XX
 +       tristate Broadcom BCM63xx SPI controller
 +       depends on BCM63XX
 +       help
 +          Enable support for the SPI controller on the Broadcom BCM63xx SoCs.
 +
  config SPI_BITBANG
        tristate Utilities for Bitbanging SPI masters
        help
 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
 index 61c3261..be38f73 100644
 --- a/drivers/spi/Makefile
 +++ b/drivers/spi/Makefile
 @@ -14,6 +14,7 @@ obj-$(CONFIG_SPI_ALTERA)              += spi-altera.o
  obj-$(CONFIG_SPI_ATMEL)                        += spi-atmel.o
  obj-$(CONFIG_SPI_ATH79)                        += spi-ath79.o
  obj-$(CONFIG_SPI_AU1550)               += spi-au1550.o
 +obj-$(CONFIG_SPI_BCM63XX)              += spi-bcm63xx.o
  obj-$(CONFIG_SPI_BFIN)                 += spi-bfin5xx.o
  obj-$(CONFIG_SPI_BFIN_SPORT)           += spi-bfin-sport.o
  obj-$(CONFIG_SPI_BITBANG)              += spi-bitbang.o
 diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c
 new file mode 100644
 index 000..9f01fc8
 --- /dev/null
 +++ b/drivers/spi/spi-bcm63xx.c
 @@ -0,0 +1,494 @@
 +/*
 + * Broadcom BCM63xx SPI controller support
 + *
 + * Copyright (C) 2009-2011 Florian Fainelli flor...@openwrt.org
 + * Copyright (C) 2010 Tanguy Bouzeloc tanguy.bouze...@efixo.com
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License
 + * as published by the Free Software Foundation; either version 2
 + * of the License, or (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License
 + * along with this program; if not, write to the
 + * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
 + */
 +
 +#include linux/kernel.h
 +#include linux/init.h
 +#include linux/clk.h
 +#include linux/module.h
 +#include linux/platform_device.h
 +#include linux/delay.h
 +#include linux/interrupt.h
 +#include linux/spi/spi.h
 +#include linux/completion.h
 +#include linux/err.h
 +
 +#include bcm63xx_dev_spi.h
 +
 +#define PFX            KBUILD_MODNAME
 +#define DRV_VER                0.1.2
 +
 +struct bcm63xx_spi {
 +       spinlock_t              lock;
 +       int                     stopping;
 +       struct completion       done;
 +
 +       void __iomem            *regs;
 +       int                     irq;
 +
 +       /* Platform data */
 +       u32                     speed_hz;
 +       unsigned                fifo_size;
 +
 +       /* Data buffers */
 +       const unsigned char     *tx_ptr;
 +       unsigned char           *rx_ptr;
 +
 +       /* data iomem */
 +       u8 __iomem              *tx_io;
 +       const u8 __iomem        *rx_io;
 +
 +       int                     remaining_bytes;
 +
 +       struct clk              *clk;
 +       struct platform_device  *pdev;
 +};
 +
 +static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
 +                               unsigned int offset)
 +{
 +       return bcm_readw(bs-regs + bcm63xx_spireg(offset));
 +}
 +
 +static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
 +                               unsigned int offset)
 +{
 +       return bcm_readw(bs-regs + bcm63xx_spireg(offset));
 +}
 +
 +static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
 +                                 u8 value, unsigned int offset)
 +{
 +       bcm_writeb(value, bs-regs + bcm63xx_spireg(offset));
 +}
 +
 +static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
 +                                 u16 value, unsigned int offset)
 +{
 +