Re: [PATCH 1/4] spi-topcliff-pch: Modify pci-bus number dynamically to get DMA device info
Hi Grant. More than a month has been passed since I posted the following patches. However still not reviewed yet. [PATCH 1/4] spi-topcliff-pch: Modify pci-bus number dynamically to get DMA device info [PATCH 2/4] spi-topcliff-pch: Fix issue for transmitting over 4KByte [PATCH 3/4][RESEND] spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control [PATCH 4/4] spi-topcliff-pch: add recovery processing in case wait-event timeout Could you review these ? thanks, tomoya 2011/12/9 Tomoya MORINAGA tomoya.r...@gmail.com: Signed-off-by: Tomoya MORINAGA tomoya.r...@gmail.com --- drivers/spi/spi-topcliff-pch.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c index 99ec279..fcd9462 100644 --- a/drivers/spi/spi-topcliff-pch.c +++ b/drivers/spi/spi-topcliff-pch.c @@ -920,7 +920,8 @@ static void pch_spi_request_dma(struct pch_spi_data *data, int bpw) dma_cap_set(DMA_SLAVE, mask); /* Get DMA's dev information */ - dma_dev = pci_get_bus_and_slot(2, PCI_DEVFN(12, 0)); + dma_dev = pci_get_bus_and_slot(data-board_dat-pdev-bus-number, + PCI_DEVFN(12, 0)); /* Set Tx DMA */ param = dma-param_tx; -- 1.7.4.4 -- Keep Your Developer Skills Current with LearnDevNow! The most comprehensive online learning library for Microsoft developers is just $99.99! Visual Studio, SharePoint, SQL - plus HTML5, CSS3, MVC3, Metro Style Apps, more. Free future releases when you subscribe now! http://p.sf.net/sfu/learndevnow-d2d ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH] spi-topcliff-pch: Fix count calculation issue
2011/12/8, Wolfram Sang w.s...@pengutronix.de: Signed-off-by: Tomoya MORINAGA tomoya.r...@gmail.com Which branch is this patch based on? This patch was created for linux-3.2. However, other patches which have dependency are not sent to upstream yet. So, I'll send the patch series again. Sorry, for inconvenience. thanks, tomoya -- Cloud Services Checklist: Pricing and Packaging Optimization This white paper is intended to serve as a reference, checklist and point of discussion for anyone considering optimizing the pricing and packaging model of a cloud services business. Read Now! http://www.accelacomm.com/jaw/sfnl/114/51491232/ ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH 1/4] spi-topcliff-pch: Modify pci-bus number dynamically to get DMA device info
Signed-off-by: Tomoya MORINAGA tomoya.r...@gmail.com --- drivers/spi/spi-topcliff-pch.c |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c index 99ec279..fcd9462 100644 --- a/drivers/spi/spi-topcliff-pch.c +++ b/drivers/spi/spi-topcliff-pch.c @@ -920,7 +920,8 @@ static void pch_spi_request_dma(struct pch_spi_data *data, int bpw) dma_cap_set(DMA_SLAVE, mask); /* Get DMA's dev information */ - dma_dev = pci_get_bus_and_slot(2, PCI_DEVFN(12, 0)); + dma_dev = pci_get_bus_and_slot(data-board_dat-pdev-bus-number, + PCI_DEVFN(12, 0)); /* Set Tx DMA */ param = dma-param_tx; -- 1.7.4.4 -- Cloud Services Checklist: Pricing and Packaging Optimization This white paper is intended to serve as a reference, checklist and point of discussion for anyone considering optimizing the pricing and packaging model of a cloud services business. Read Now! http://www.accelacomm.com/jaw/sfnl/114/51491232/ ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH 2/4] spi-topcliff-pch: Fix issue for transmitting over 4KByte
Currently, when spi-topcliff-pch receives transmit request over 4KByte,
this driver can't process correctly. This driver needs to divide the data
into 4Kbyte unit.
This patch fixes the issue.
Signed-off-by: Tomoya MORINAGA tomoya.r...@gmail.com
---
drivers/spi/spi-topcliff-pch.c | 66 +---
1 files changed, 55 insertions(+), 11 deletions(-)
diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c
index fcd9462..7339765 100644
--- a/drivers/spi/spi-topcliff-pch.c
+++ b/drivers/spi/spi-topcliff-pch.c
@@ -194,6 +194,7 @@ struct pch_spi_data {
struct pch_spi_dma_ctrl dma;
int use_dma;
u8 irq_reg_sts;
+ int save_total_len;
};
/**
@@ -819,11 +820,13 @@ static void pch_spi_copy_rx_data_for_dma(struct
pch_spi_data *data, int bpw)
rx_dma_buf = data-dma.rx_buf_virt;
for (j = 0; j data-bpw_len; j++)
*rx_buf++ = *rx_dma_buf++ 0xFF;
+ data-cur_trans-rx_buf = rx_buf;
} else {
rx_sbuf = data-cur_trans-rx_buf;
rx_dma_sbuf = data-dma.rx_buf_virt;
for (j = 0; j data-bpw_len; j++)
*rx_sbuf++ = *rx_dma_sbuf++;
+ data-cur_trans-rx_buf = rx_sbuf;
}
}
@@ -849,6 +852,9 @@ static int pch_spi_start_transfer(struct pch_spi_data *data)
rtn = wait_event_interruptible_timeout(data-wait,
data-transfer_complete,
msecs_to_jiffies(2 * HZ));
+ if (!rtn)
+ dev_err(data-master-dev,
+ %s wait-event timeout\n, __func__);
dma_sync_sg_for_cpu(data-master-dev, dma-sg_rx_p, dma-nent,
DMA_FROM_DEVICE);
@@ -985,6 +991,7 @@ static void pch_spi_handle_dma(struct pch_spi_data *data,
int *bpw)
int i;
int size;
int rem;
+ int head;
unsigned long flags;
struct pch_spi_dma_ctrl *dma;
@@ -1013,6 +1020,11 @@ static void pch_spi_handle_dma(struct pch_spi_data
*data, int *bpw)
}
data-bpw_len = data-cur_trans-len / (*bpw / 8);
+ if (data-bpw_len PCH_BUF_SIZE) {
+ data-bpw_len = PCH_BUF_SIZE;
+ data-cur_trans-len -= PCH_BUF_SIZE;
+ }
+
/* copy Tx Data */
if (data-cur_trans-tx_buf != NULL) {
if (*bpw == 8) {
@@ -1027,10 +1039,17 @@ static void pch_spi_handle_dma(struct pch_spi_data
*data, int *bpw)
*tx_dma_sbuf++ = *tx_sbuf++;
}
}
+
+ /* Calculate Rx parameter for DMA transmitting */
if (data-bpw_len PCH_DMA_TRANS_SIZE) {
- num = data-bpw_len / PCH_DMA_TRANS_SIZE + 1;
+ if (data-bpw_len % PCH_DMA_TRANS_SIZE) {
+ num = data-bpw_len / PCH_DMA_TRANS_SIZE + 1;
+ rem = data-bpw_len % PCH_DMA_TRANS_SIZE;
+ } else {
+ num = data-bpw_len / PCH_DMA_TRANS_SIZE;
+ rem = PCH_DMA_TRANS_SIZE;
+ }
size = PCH_DMA_TRANS_SIZE;
- rem = data-bpw_len % PCH_DMA_TRANS_SIZE;
} else {
num = 1;
size = data-bpw_len;
@@ -1090,15 +1109,23 @@ static void pch_spi_handle_dma(struct pch_spi_data
*data, int *bpw)
dma-nent = num;
dma-desc_rx = desc_rx;
- /* TX */
- if (data-bpw_len PCH_DMA_TRANS_SIZE) {
- num = data-bpw_len / PCH_DMA_TRANS_SIZE;
+ /* Calculate Tx parameter for DMA transmitting */
+ if (data-bpw_len PCH_MAX_FIFO_DEPTH) {
+ head = PCH_MAX_FIFO_DEPTH - PCH_DMA_TRANS_SIZE;
+ if (data-bpw_len % PCH_DMA_TRANS_SIZE 4) {
+ num = data-bpw_len / PCH_DMA_TRANS_SIZE + 1;
+ rem = data-bpw_len % PCH_DMA_TRANS_SIZE - head;
+ } else {
+ num = data-bpw_len / PCH_DMA_TRANS_SIZE;
+ rem = data-bpw_len % PCH_DMA_TRANS_SIZE +
+ PCH_DMA_TRANS_SIZE - head;
+ }
size = PCH_DMA_TRANS_SIZE;
- rem = 16;
} else {
num = 1;
size = data-bpw_len;
rem = data-bpw_len;
+ head = 0;
}
dma-sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
@@ -1108,11 +1135,17 @@ static void pch_spi_handle_dma(struct pch_spi_data
*data, int *bpw)
for (i = 0; i num; i++, sg++) {
if (i == 0) {
sg-offset = 0;
+ sg_set_page(sg, virt_to_page(dma-tx_buf_virt), size +
head,
+ sg-offset);
+ sg_dma_len(sg) = size + head;
+ } else if (i == (num - 1)) {
+ sg-offset
[PATCH 3/4][RESEND] spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
This patch supports a spi mode setup and bit order setup by IO control. spi mode: mode 0 to mode 3 bit order:LSB first, MSB first Signed-off-by: Tomoya MORINAGA tomoya.r...@gmail.com --- drivers/spi/spi-topcliff-pch.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c index 7339765..1864555 100644 --- a/drivers/spi/spi-topcliff-pch.c +++ b/drivers/spi/spi-topcliff-pch.c @@ -1430,6 +1430,7 @@ static int __devinit pch_spi_pd_probe(struct platform_device *plat_dev) master-num_chipselect = PCH_MAX_CS; master-setup = pch_spi_setup; master-transfer = pch_spi_transfer; + master-mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; data-board_dat = board_dat; data-plat_dev = plat_dev; -- 1.7.4.4 -- Cloud Services Checklist: Pricing and Packaging Optimization This white paper is intended to serve as a reference, checklist and point of discussion for anyone considering optimizing the pricing and packaging model of a cloud services business. Read Now! http://www.accelacomm.com/jaw/sfnl/114/51491232/ ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH 4/4] spi-topcliff-pch: add recovery processing in case wait-event timeout
Currently, pch_spi_start_transfer failure is not anticipated.
This patch adds the processing.
Signed-off-by: Tomoya MORINAGA tomoya.r...@gmail.com
---
drivers/spi/spi-topcliff-pch.c | 10 +-
1 files changed, 9 insertions(+), 1 deletions(-)
diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c
index 1864555..10b684c 100644
--- a/drivers/spi/spi-topcliff-pch.c
+++ b/drivers/spi/spi-topcliff-pch.c
@@ -1262,8 +1262,16 @@ static void pch_spi_process_messages(struct work_struct
*pwork)
char *save_rx_buf = data-cur_trans-rx_buf;
for (i = 0; i cnt; i ++) {
pch_spi_handle_dma(data, bpw);
- if (!pch_spi_start_transfer(data))
+ if (!pch_spi_start_transfer(data)) {
+ data-transfer_complete = true;
+ data-current_msg-status = -EIO;
+ data-current_msg-complete
+ (data-current_msg-context);
+ data-bcurrent_msg_processing = false;
+ data-current_msg = NULL;
+ data-cur_trans = NULL;
goto out;
+ }
pch_spi_copy_rx_data_for_dma(data, bpw);
}
data-cur_trans-rx_buf = save_rx_buf;
--
1.7.4.4
--
Cloud Services Checklist: Pricing and Packaging Optimization
This white paper is intended to serve as a reference, checklist and point of
discussion for anyone considering optimizing the pricing and packaging model
of a cloud services business. Read Now!
http://www.accelacomm.com/jaw/sfnl/114/51491232/
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH] spi-topcliff-pch: Fix count calculation issue
Currently, count value is not correct more than len=8193 like below.
len Current-cnt New-cnt Anticipated-cnt
40951 1 1
40961 1 1
40972 2 2
81912 2 2
81922 2 2
81932(NG) 3 3
12287 3 3 3
12288 3 3 3
12289 3(NG) 4 4
This patch fixes the issue.
Signed-off-by: Tomoya MORINAGA tomoya.r...@gmail.com
---
drivers/spi/spi-topcliff-pch.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c
index 9fb0541..08b5f31 100644
--- a/drivers/spi/spi-topcliff-pch.c
+++ b/drivers/spi/spi-topcliff-pch.c
@@ -1247,7 +1247,9 @@ static void pch_spi_process_messages(struct work_struct
*pwork)
}
spin_unlock(data-lock);
- cnt = data-cur_trans-len / (PCH_BUF_SIZE + 1) + 1;
+ if (!data-cur_trans-len)
+ goto out;
+ cnt = (data-cur_trans-len - 1) / PCH_BUF_SIZE + 1;
data-save_total_len = data-cur_trans-len;
if (data-use_dma) {
int i;
--
1.7.4.4
--
All the data continuously generated in your IT infrastructure
contains a definitive record of customers, application performance,
security threats, fraudulent activity, and more. Splunk takes this
data and makes sense of it. IT sense. And common sense.
http://p.sf.net/sfu/splunk-novd2d
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH 1/2] spi-topcliff-pch: Support new device LAPIS Semiconductor ML7831 IOH
ML7831 is companion chip for Intel Atom E6xx series.
Signed-off-by: Tomoya MORINAGA tomoya-li...@dsn.lapis-semi.com
---
drivers/spi/Kconfig|6 +++---
drivers/spi/spi-topcliff-pch.c |5 -
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index a1fd73d..6168516 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -346,14 +346,14 @@ config SPI_TI_SSP
serial port.
config SPI_TOPCLIFF_PCH
- tristate Intel EG20T PCH/OKI SEMICONDUCTOR ML7213 IOH SPI controller
+ tristate Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) SPI
depends on PCI
help
SPI driver for the Topcliff PCH (Platform Controller Hub) SPI bus
used in some x86 embedded processors.
- This driver also supports the ML7213, a companion chip for the
- Atom E6xx series and compatible with the Intel EG20T PCH.
+ This driver also supports the ML7213/ML7223/ML7831, a companion chip
+ for the Atom E6xx series and compatible with the Intel EG20T PCH.
config SPI_TXX9
tristate Toshiba TXx9 SPI controller
diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c
index 6a80749..2b1e966 100644
--- a/drivers/spi/spi-topcliff-pch.c
+++ b/drivers/spi/spi-topcliff-pch.c
@@ -95,16 +95,18 @@
#define PCH_CLOCK_HZ 5000
#define PCH_MAX_SPBR 1023
-/* Definition for ML7213 by OKI SEMICONDUCTOR */
+/* Definition for ML7213/ML7831 by OKI SEMICONDUCTOR */
#define PCI_VENDOR_ID_ROHM 0x10DB
#define PCI_DEVICE_ID_ML7213_SPI 0x802c
#define PCI_DEVICE_ID_ML7223_SPI 0x800F
+#define PCI_DEVICE_ID_ML7831_SPI 0x8816
/*
* Set the number of SPI instance max
* Intel EG20T PCH : 1ch
* OKI SEMICONDUCTOR ML7213 IOH : 2ch
* OKI SEMICONDUCTOR ML7223 IOH : 1ch
+ * OKI SEMICONDUCTOR ML7831 IOH : 1ch
*/
#define PCH_SPI_MAX_DEV2
@@ -218,6 +220,7 @@ static struct pci_device_id pch_spi_pcidev_id[] = {
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI),1, },
{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, },
+ { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_SPI), 1, },
{ }
};
--
1.7.4.4
--
The demand for IT networking professionals continues to grow, and the
demand for specialized networking skills is growing even more rapidly.
Take a complimentary Learning@Cisco Self-Assessment and learn
about Cisco certifications, training, and career opportunities.
http://p.sf.net/sfu/cisco-dev2dev
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH 2/2] spi-topcliff-pch: Change company name OKI SEMICONDUCTOR to LAPIS Semiconductor
On October 1 in 2011, OKI SEMICONDUCTOR Co., Ltd. changed the company name in to LAPIS Semiconductor Co., Ltd. Signed-off-by: Tomoya MORINAGA tomoya-li...@dsn.lapis-semi.com --- drivers/spi/spi-topcliff-pch.c | 12 ++-- 1 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c index 2b1e966..7086583 100644 --- a/drivers/spi/spi-topcliff-pch.c +++ b/drivers/spi/spi-topcliff-pch.c @@ -1,7 +1,7 @@ /* * SPI bus driver for the Topcliff PCH used by Intel SoCs * - * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD. + * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -95,7 +95,7 @@ #define PCH_CLOCK_HZ 5000 #define PCH_MAX_SPBR 1023 -/* Definition for ML7213/ML7831 by OKI SEMICONDUCTOR */ +/* Definition for ML7213/ML7223/ML7831 by LAPIS Semiconductor */ #define PCI_VENDOR_ID_ROHM 0x10DB #define PCI_DEVICE_ID_ML7213_SPI 0x802c #define PCI_DEVICE_ID_ML7223_SPI 0x800F @@ -104,9 +104,9 @@ /* * Set the number of SPI instance max * Intel EG20T PCH : 1ch - * OKI SEMICONDUCTOR ML7213 IOH : 2ch - * OKI SEMICONDUCTOR ML7223 IOH : 1ch - * OKI SEMICONDUCTOR ML7831 IOH : 1ch + * LAPIS Semiconductor ML7213 IOH :2ch + * LAPIS Semiconductor ML7223 IOH :1ch + * LAPIS Semiconductor ML7831 IOH :1ch */ #define PCH_SPI_MAX_DEV2 @@ -1756,4 +1756,4 @@ MODULE_PARM_DESC(use_dma, to use DMA for data transfers pass 1 else 0; default 1); MODULE_LICENSE(GPL); -MODULE_DESCRIPTION(Intel EG20T PCH/OKI SEMICONDUCTOR ML7xxx IOH SPI Driver); +MODULE_DESCRIPTION(Intel EG20T PCH/LAPIS Semiconductor ML7xxx IOH SPI Driver); -- 1.7.4.4 -- The demand for IT networking professionals continues to grow, and the demand for specialized networking skills is growing even more rapidly. Take a complimentary Learning@Cisco Self-Assessment and learn about Cisco certifications, training, and career opportunities. http://p.sf.net/sfu/cisco-dev2dev ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH] spi_topcliff_pch: supports a spi mode setup and bit order setup by IO control
Hi Grant, It seems this patch Toshiharu posted in 20-July remains not to be reviewed by you. Could you review this patch and merge to your tree ? Thanks in advance, -- tomoya ROHM Co., Ltd. (2011/07/20 14:56), Toshiharu Okada wrote: This patch supports a spi mode setup and bit order setup by IO control. spi mode: mode 0 to mode 3 bit order:LSB first, MSB first Signed-off-by: Toshiharu Okadatoshiharu-li...@dsn.okisemi.com --- drivers/spi/spi_topcliff_pch.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/drivers/spi/spi_topcliff_pch.c b/drivers/spi/spi_topcliff_pch.c index 79e48d4..dec83c9 100644 --- a/drivers/spi/spi_topcliff_pch.c +++ b/drivers/spi/spi_topcliff_pch.c @@ -1038,6 +1038,7 @@ static int pch_spi_probe(struct pci_dev *pdev, const struct pci_device_id *id) master-num_chipselect = PCH_MAX_CS; master-setup = pch_spi_setup; master-transfer = pch_spi_transfer; + master-mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; dev_dbg(pdev-dev, %s transfer member of SPI master initialized\n, __func__); -- All the data continuously generated in your IT infrastructure contains a definitive record of customers, application performance, security threats, fraudulent activity and more. Splunk takes this data and makes sense of it. Business sense. IT sense. Common sense. http://p.sf.net/sfu/splunk-d2dcopy1 ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH 1/5] spi-topcliff-pch: add tx-memory clear after complete transmitting
Hi Grant, 1 month has passed. You look very busy, right ? We've been long waiting for your accept. Could you review these patch series ? Thanks in advance. (2011/09/06 16:58), Tomoya MORINAGA wrote: Currently, in case of reading date from SPI flash, command is sent twice. The cause is that tx-memory clear processing is missing . This patch adds the tx-momory clear processing. Signed-off-by: Tomoya MORINAGAtomoya-li...@dsn.okisemi.com --- drivers/spi/spi-topcliff-pch.c |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c index 540c290..1b98b7e 100644 --- a/drivers/spi/spi-topcliff-pch.c +++ b/drivers/spi/spi-topcliff-pch.c @@ -839,6 +839,11 @@ static void pch_spi_start_transfer(struct pch_spi_data *data) dma_sync_sg_for_cpu(data-master-dev, dma-sg_rx_p, dma-nent, DMA_FROM_DEVICE); + + dma_sync_sg_for_cpu(data-master-dev, dma-sg_tx_p, dma-nent, + DMA_FROM_DEVICE); + memset(data-dma.tx_buf_virt, 0, PAGE_SIZE); + async_tx_ack(dma-desc_rx); async_tx_ack(dma-desc_tx); kfree(dma-sg_tx_p); -- tomoya ROHM Co., Ltd. -- All the data continuously generated in your IT infrastructure contains a definitive record of customers, application performance, security threats, fraudulent activity and more. Splunk takes this data and makes sense of it. Business sense. IT sense. Common sense. http://p.sf.net/sfu/splunk-d2dcopy1 ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH 4/5 v2] spi-topcliff-pch: Add recovery processing in case FIFO overrun error occurs
Add recovery processing in case FIFO overrun error occurs with DMA transfer
mode.
Signed-off-by: Tomoya MORINAGA tomoya-li...@dsn.okisemi.com
---
v2: v1 patch series are included invalid patch file
---
drivers/spi/spi-topcliff-pch.c | 31 ---
1 files changed, 24 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c
index 6cb2fdb..c8efa75 100644
--- a/drivers/spi/spi-topcliff-pch.c
+++ b/drivers/spi/spi-topcliff-pch.c
@@ -352,16 +352,26 @@ static irqreturn_t pch_spi_handler(int irq, void *dev_id)
%s returning due to suspend\n, __func__);
return IRQ_NONE;
}
- if (data-use_dma)
- return IRQ_NONE;
io_remap_addr = data-io_remap_addr;
spsr = io_remap_addr + PCH_SPSR;
reg_spsr_val = ioread32(spsr);
- if (reg_spsr_val SPSR_ORF_BIT)
- dev_err(board_dat-pdev-dev, %s Over run error, __func__);
+ if (reg_spsr_val SPSR_ORF_BIT) {
+ dev_err(board_dat-pdev-dev, %s Over run error\n, __func__);
+ if (data-current_msg-complete != 0) {
+ data-transfer_complete = true;
+ data-current_msg-status = -EIO;
+ data-current_msg-complete(data-current_msg-context);
+ data-bcurrent_msg_processing = false;
+ data-current_msg = NULL;
+ data-cur_trans = NULL;
+ }
+ }
+
+ if (data-use_dma)
+ return IRQ_NONE;
/* Check if the interrupt is for SPI device */
if (reg_spsr_val (SPSR_FI_BIT | SPSR_RFI_BIT)) {
@@ -815,10 +825,11 @@ static void pch_spi_copy_rx_data_for_dma(struct
pch_spi_data *data, int bpw)
}
}
-static void pch_spi_start_transfer(struct pch_spi_data *data)
+static int pch_spi_start_transfer(struct pch_spi_data *data)
{
struct pch_spi_dma_ctrl *dma;
unsigned long flags;
+ int rtn;
dma = data-dma;
@@ -833,7 +844,9 @@ static void pch_spi_start_transfer(struct pch_spi_data
*data)
initiating the transfer. */
dev_dbg(data-master-dev,
%s:waiting for transfer to get over\n, __func__);
- wait_event_interruptible(data-wait, data-transfer_complete);
+ rtn = wait_event_interruptible_timeout(data-wait,
+ data-transfer_complete,
+ msecs_to_jiffies(2 * HZ));
dma_sync_sg_for_cpu(data-master-dev, dma-sg_rx_p, dma-nent,
DMA_FROM_DEVICE);
@@ -860,6 +873,8 @@ static void pch_spi_start_transfer(struct pch_spi_data
*data)
pch_spi_clear_fifo(data-master);
spin_unlock_irqrestore(data-lock, flags);
+
+ return rtn;
}
static void pch_dma_rx_complete(void *arg)
@@ -1187,7 +1202,8 @@ static void pch_spi_process_messages(struct work_struct
*pwork)
if (data-use_dma) {
pch_spi_handle_dma(data, bpw);
- pch_spi_start_transfer(data);
+ if (!pch_spi_start_transfer(data))
+ goto out;
pch_spi_copy_rx_data_for_dma(data, bpw);
} else {
pch_spi_set_tx(data, bpw);
@@ -1225,6 +1241,7 @@ static void pch_spi_process_messages(struct work_struct
*pwork)
} while (data-cur_trans != NULL);
+out:
pch_spi_writereg(data-master, PCH_SSNXCR, SSN_HIGH);
if (data-use_dma)
pch_spi_release_dma(data);
--
1.7.4.4
--
Special Offer -- Download ArcSight Logger for FREE!
Finally, a world-class log management solution at an even better
price-free! And you'll get a free Love Thy Logs t-shirt when you
download Logger. Secure your free ArcSight Logger TODAY!
http://p.sf.net/sfu/arcsisghtdev2dev
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH] spi-topcliff-pch: Support new device ML7223 IOH
Support new device OKI SEMICONDUCTOR ML7223 IOH(Input/Output Hub).
The ML7223 IOH is for MP(Media Phone) use.
The ML7223 is companion chip for Intel Atom E6xx series.
The ML7223 is completely compatible for Intel EG20T PCH.
Signed-off-by: Tomoya MORINAGA tomoya-li...@dsn.okisemi.com
---
drivers/spi/spi-topcliff-pch.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c
index 1b8030b..5b574cf 100644
--- a/drivers/spi/spi-topcliff-pch.c
+++ b/drivers/spi/spi-topcliff-pch.c
@@ -95,11 +95,13 @@
/* Definition for ML7213 by OKI SEMICONDUCTOR */
#define PCI_VENDOR_ID_ROHM 0x10DB
#define PCI_DEVICE_ID_ML7213_SPI 0x802c
+#define PCI_DEVICE_ID_ML7223_SPI 0x800F
/*
* Set the number of SPI instance max
* Intel EG20T PCH : 1ch
* OKI SEMICONDUCTOR ML7213 IOH : 2ch
+ * OKI SEMICONDUCTOR ML7223 IOH : 1ch
*/
#define PCH_SPI_MAX_DEV2
@@ -212,6 +214,7 @@ struct pch_pd_dev_save {
static struct pci_device_id pch_spi_pcidev_id[] = {
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI),1, },
{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
+ { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, },
{ }
};
@@ -1711,4 +1714,4 @@ MODULE_PARM_DESC(use_dma,
to use DMA for data transfers pass 1 else 0; default 1);
MODULE_LICENSE(GPL);
-MODULE_DESCRIPTION(Intel EG20T PCH/OKI SEMICONDUCTOR ML7213 IOH SPI Driver);
+MODULE_DESCRIPTION(Intel EG20T PCH / OKI SEMICONDUCTOR ML7xxx IOH SPI
Driver);
--
1.7.4
--
EditLive Enterprise is the world's most technically advanced content
authoring tool. Experience the power of Track Changes, Inline Image
Editing and ensure content is compliant with Accessibility Checking.
http://p.sf.net/sfu/ephox-dev2dev
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH/RESEND v4 1/2] spi_topcliff_pch: support new device ML7213 IOH
Hi Grant, Why don't you give us your comment/opinion at all for our v4 patch ?? We have been long waiting since 27-April. (2011/06/07 14:50), Tomoya MORINAGA wrote: ***Modify Grant's comments. - Delete unrelated whitespace - Prevent device driver from accessing platform data - Add __devinit and __devexit - Save pdev-dev to pd_dev-dev.parent - Have own suspend/resume processing in platform_driver. - Care returned value in pch_spi_init - Change unregister order Support ML7213 device of OKI SEMICONDUCTOR. ML7213 is companion chip of Intel Atom E6xx series for IVI(In-Vehicle Infotainment). ML7213 is compatible for Intel EG20T PCH. Signed-off-by: Tomoya MORINAGAtomoya-li...@dsn.okisemi.com --- drivers/spi/Kconfig|5 +- drivers/spi/spi_topcliff_pch.c | 599 +--- 2 files changed, 317 insertions(+), 287 deletions(-) -- tomoya OKI SEMICONDUCTOR CO., LTD. -- EditLive Enterprise is the world's most technically advanced content authoring tool. Experience the power of Track Changes, Inline Image Editing and ensure content is compliant with Accessibility Checking. http://p.sf.net/sfu/ephox-dev2dev ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH/RESEND v4 1/2] spi_topcliff_pch: support new device ML7213 IOH
(2011/06/08 23:44), Grant Likely wrote: Sorry about that Tomoya. I got completely overloaded at the end of April and all of May. I ended up dropping a lot of patches on the floor because of it. I'm not purposefully ignoring you! I can understand you ware very busy last month. Though I thought you tried to avoid me, I was relieved to read this your mail. I wanted to know the information at last month. Thanks, tomoya -- EditLive Enterprise is the world's most technically advanced content authoring tool. Experience the power of Track Changes, Inline Image Editing and ensure content is compliant with Accessibility Checking. http://p.sf.net/sfu/ephox-dev2dev ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH v2] spi: reorganize drivers
Hi Grant, (2011/06/07 1:52), Grant Likely wrote: Hahaha. Oops, I can't remember the conversation I had 5 minutes after getting off the phone. It should actually be Tomoya who can comment on the name change. As far as I know, this change doesn't occur any issue. However, I don't have perfect confidence about it. Could you give me any information about concern ? -- tomoya OKI SEMICONDUCTOR CO., LTD. -- EditLive Enterprise is the world's most technically advanced content authoring tool. Experience the power of Track Changes, Inline Image Editing and ensure content is compliant with Accessibility Checking. http://p.sf.net/sfu/ephox-dev2dev ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH/RESEND 2/2] spi_topcliff_pch: DMA support
This patch enables this SPI driver works with DMA mode.
Signed-off-by: Tomoya MORINAGA tomoya-li...@dsn.okisemi.com
---
drivers/spi/spi_topcliff_pch.c | 612
1 files changed, 492 insertions(+), 120 deletions(-)
diff --git a/drivers/spi/spi_topcliff_pch.c b/drivers/spi/spi_topcliff_pch.c
index 88bd472..f543ff6 100644
--- a/drivers/spi/spi_topcliff_pch.c
+++ b/drivers/spi/spi_topcliff_pch.c
@@ -28,6 +28,9 @@
#include linux/device.h
#include linux/platform_device.h
+#include linux/dmaengine.h
+#include linux/pch_dma.h
+
/* Register offsets */
#define PCH_SPCR 0x00/* SPI control register */
#define PCH_SPBRR 0x04/* SPI baud rate register */
@@ -36,7 +39,7 @@
#define PCH_SPDRR 0x10/* SPI read data register */
#define PCH_SSNXCR 0x18/* SSN Expand Control Register */
#define PCH_SRST 0x1C/* SPI reset register */
-#define PCH_SPI_ADDRESS_SIZE 0x20
+#define PCH_ADDRESS_SIZE 0x20
#define PCH_SPSR_TFD 0x07C0
#define PCH_SPSR_RFD 0xF800
@@ -54,8 +57,6 @@
#define STATUS_EXITING 2
#define PCH_SLEEP_TIME 10
-#define PCH_ADDRESS_SIZE 0x20
-
#define SSN_LOW0x02U
#define SSN_NO_CONTROL 0x00U
#define PCH_MAX_CS 0xFF
@@ -75,6 +76,7 @@
#define SPSR_TFI_BIT (1 0)
#define SPSR_RFI_BIT (1 1)
#define SPSR_FI_BIT(1 2)
+#define SPSR_ORF_BIT (1 3)
#define SPBRR_SIZE_BIT (1 10)
#define PCH_ALL
(SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\
@@ -83,10 +85,9 @@
#define SPCR_RFIC_FIELD20
#define SPCR_TFIC_FIELD16
-#define SPSR_INT_BITS 0x1F
-#define MASK_SPBRR_SPBR_BITS (~((1 10) - 1))
-#define MASK_RFIC_SPCR_BITS(~(0xf 20))
-#define MASK_TFIC_SPCR_BITS(~(0xf000f 12))
+#define MASK_SPBRR_SPBR_BITS ((1 10) - 1)
+#define MASK_RFIC_SPCR_BITS(0xf SPCR_RFIC_FIELD)
+#define MASK_TFIC_SPCR_BITS(0xf SPCR_TFIC_FIELD)
#define PCH_CLOCK_HZ 5000
#define PCH_MAX_SPBR 1023
@@ -102,6 +103,28 @@
*/
#define PCH_SPI_MAX_DEV2
+#define PCH_BUF_SIZE 4096
+#define PCH_DMA_TRANS_SIZE 12
+
+static int use_dma = 1;
+
+struct pch_spi_dma_ctrl {
+ struct dma_async_tx_descriptor *desc_tx;
+ struct dma_async_tx_descriptor *desc_rx;
+ struct pch_dma_slaveparam_tx;
+ struct pch_dma_slaveparam_rx;
+ struct dma_chan *chan_tx;
+ struct dma_chan *chan_rx;
+ struct scatterlist *sg_tx_p;
+ struct scatterlist *sg_rx_p;
+ struct scatterlist sg_tx;
+ struct scatterlist sg_rx;
+ int nent;
+ void*tx_buf_virt;
+ void*rx_buf_virt;
+ dma_addr_t tx_buf_dma;
+ dma_addr_t rx_buf_dma;
+};
/**
* struct pch_spi_data - Holds the SPI channel specific details
* @io_remap_addr: The remapped PCI base address
@@ -140,6 +163,7 @@
*/
struct pch_spi_data {
void __iomem *io_remap_addr;
+ unsigned long io_base_addr;
struct spi_master *master;
struct work_struct work;
struct workqueue_struct *wk;
@@ -162,6 +186,8 @@ struct pch_spi_data {
struct pch_spi_board_data *board_dat;
struct platform_device *plat_dev;
int ch;
+ struct pch_spi_dma_ctrl dma;
+ int use_dma;
u8 irq_reg_sts;
};
@@ -273,10 +299,10 @@ static void pch_spi_handler_sub(struct pch_spi_data
*data, u32 reg_spsr_val,
reg_spcr_val = ~SPCR_RFIE_BIT; /* disable RFI */
/* reset rx threshold */
- reg_spcr_val = MASK_RFIC_SPCR_BITS;
+ reg_spcr_val = ~MASK_RFIC_SPCR_BITS;
reg_spcr_val |= (PCH_RX_THOLD_MAX SPCR_RFIC_FIELD);
- iowrite32(((reg_spcr_val) = (~(SPCR_RFIE_BIT))),
-(io_remap_addr + PCH_SPCR));
+
+ iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR));
}
/* update counts */
@@ -287,12 +313,15 @@ static void pch_spi_handler_sub(struct pch_spi_data
*data, u32 reg_spsr_val,
/* if transfer complete interrupt */
if (reg_spsr_val SPSR_FI_BIT) {
- /* disable FI RFI interrupts */
- pch_spi_setclr_reg(data-master, PCH_SPCR, 0,
- SPCR_FIE_BIT | SPCR_RFIE_BIT);
+ if (tx_index bpw_len)
+ dev_err(data-master-dev,
+ %s : Transfer is not completed, __func__);
+ /* disable interrupts
Re: [PATCH/RESEND v4 1/2] spi_topcliff_pch: support new device ML7213 IOH
Sorry for invalid patch From y
It seems My PC's clock is reset.
(2009/01/02 8:29), y wrote:
From: Tomoya MORINAGAtomoya-li...@dsn.okisemi.com
***Modify Grant's comments.
- Delete unrelated whitespace
- Prevent device driver from accessing platform data
- Add __devinit and __devexit
- Save pdev-dev to pd_dev-dev.parent
- Have own suspend/resume processing in platform_driver.
- Care returned value in pch_spi_init
- Change unregister order
Support ML7213 device of OKI SEMICONDUCTOR.
ML7213 is companion chip of Intel Atom E6xx series for IVI(In-Vehicle
Infotainment).
ML7213 is compatible for Intel EG20T PCH.
Signed-off-by: Tomoya MORINAGAtomoya-li...@dsn.okisemi.com
---
drivers/spi/Kconfig|5 +-
drivers/spi/spi_topcliff_pch.c | 599
+---
2 files changed, 317 insertions(+), 287 deletions(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index fc14b8d..ed6134b 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -380,12 +380,15 @@ config SPI_TI_SSP
module will be called ti-ssp-spi.
config SPI_TOPCLIFF_PCH
- tristate Topcliff PCH SPI Controller
+ tristate Intel EG20T PCH/OKI SEMICONDUCTOR ML7213 IOH SPI controller
depends on PCI
help
SPI driver for the Topcliff PCH (Platform Controller Hub) SPI bus
used in some x86 embedded processors.
+ This driver also supports the ML7213, a companion chip for the
+ Atom E6xx series and compatible with the Intel EG20T PCH.
+
config SPI_TXX9
tristate Toshiba TXx9 SPI controller
depends on GENERIC_GPIO CPU_TX49XX
diff --git a/drivers/spi/spi_topcliff_pch.c b/drivers/spi/spi_topcliff_pch.c
index 79e48d4..88bd472 100644
--- a/drivers/spi/spi_topcliff_pch.c
+++ b/drivers/spi/spi_topcliff_pch.c
@@ -26,6 +26,7 @@
#includelinux/spi/spidev.h
#includelinux/module.h
#includelinux/device.h
+#includelinux/platform_device.h
/* Register offsets */
#define PCH_SPCR0x00/* SPI control register */
@@ -35,6 +36,7 @@
#define PCH_SPDRR 0x10/* SPI read data register */
#define PCH_SSNXCR 0x18/* SSN Expand Control Register */
#define PCH_SRST0x1C/* SPI reset register */
+#define PCH_SPI_ADDRESS_SIZE 0x20
#define PCH_SPSR_TFD0x07C0
#define PCH_SPSR_RFD0xF800
@@ -75,7 +77,8 @@
#define SPSR_FI_BIT (1 2)
#define SPBRR_SIZE_BIT (1 10)
-#define PCH_ALL
(SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|SPCR_ORIE_BIT|SPCR_MDFIE_BIT)
+#define PCH_ALL
(SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\
+ SPCR_ORIE_BIT|SPCR_MDFIE_BIT)
#define SPCR_RFIC_FIELD 20
#define SPCR_TFIC_FIELD 16
@@ -88,6 +91,16 @@
#define PCH_CLOCK_HZ5000
#define PCH_MAX_SPBR1023
+/* Definition for ML7213 by OKI SEMICONDUCTOR */
+#define PCI_VENDOR_ID_ROHM 0x10DB
+#define PCI_DEVICE_ID_ML7213_SPI 0x802c
+
+/*
+ * Set the number of SPI instance max
+ * Intel EG20T PCH : 1ch
+ * OKI SEMICONDUCTOR ML7213 IOH :2ch
+*/
+#define PCH_SPI_MAX_DEV 2
/**
* struct pch_spi_data - Holds the SPI channel specific details
@@ -121,6 +134,9 @@
* @cur_trans: The current transfer that this SPI
driver is
* handling
* @board_dat: Reference to the SPI device data
structure
+ * @plat_dev:platform_device structure
+ * @ch: SPI channel number
+ * @irq_reg_sts: Status of IRQ registration
*/
struct pch_spi_data {
void __iomem *io_remap_addr;
@@ -144,27 +160,33 @@ struct pch_spi_data {
struct spi_message *current_msg;
struct spi_transfer *cur_trans;
struct pch_spi_board_data *board_dat;
+ struct platform_device *plat_dev;
+ int ch;
+ u8 irq_reg_sts;
};
/**
* struct pch_spi_board_data - Holds the SPI device specific details
* @pdev: Pointer to the PCI device
- * @irq_reg_sts: Status of IRQ registration
- * @pci_req_sts: Status of pci_request_regions
* @suspend_sts:Status of suspend
- * @data:Pointer to SPI channel data structure
+ * @num: The number of SPI device instance
*/
struct pch_spi_board_data {
struct pci_dev *pdev;
- u8 irq_reg_sts;
- u8 pci_req_sts;
u8 suspend_sts;
- struct pch_spi_data *data;
+ int num;
+};
+
+struct pch_pd_dev_save {
+ int num;
+ struct platform_device *pd_save[PCH_SPI_MAX_DEV];
+ struct pch_spi_board_data *board_dat;
};
static struct pci_device_id pch_spi_pcidev_id[] = {
-
RE: [PATCH v4 1/2] spi_topcliff_pch: support new device ML7213 IOH
Grant, Could you review this patch ASAP? I worry this spi patch can not be integrated to the latest kernel again. With Best Regards, - Tomoya MORINAGA OKI SEMICONDUCTOR CO., LTD. -Original Message- From: linux-kernel-ow...@vger.kernel.org [mailto:linux-kernel-ow...@vger.kernel.org] On Behalf Of Tomoya MORINAGA Sent: Friday, May 20, 2011 9:07 AM To: 'David Brownell'; 'Grant Likely'; spi-devel-general@lists.sourceforge.net; linux-ker...@vger.kernel.org Cc: qi.w...@intel.com; yong.y.w...@intel.com; joel.cl...@intel.com; kok.howg@intel.com; 'Toshiharu Okada' Subject: RE: [PATCH v4 1/2] spi_topcliff_pch: support new device ML7213 IOH Hi Grant Could you review this patch ASAP? There is little time to be integrated to 2.6.40. Thanks, - Tomoya MORINAGA OKI SEMICONDUCTOR CO., LTD. -Original Message- From: linux-kernel-ow...@vger.kernel.org [mailto:linux-kernel-ow...@vger.kernel.org] On Behalf Of Tomoya MORINAGA Sent: Tuesday, May 10, 2011 2:59 PM To: 'David Brownell'; 'Grant Likely'; spi-devel-general@lists.sourceforge.net; linux-ker...@vger.kernel.org Cc: qi.w...@intel.com; yong.y.w...@intel.com; joel.cl...@intel.com; kok.howg@intel.com Subject: RE: [PATCH v4 1/2] spi_topcliff_pch: support new device ML7213 IOH Hi Grant, Sent: Wednesday, April 27, 2011 11:23 AM To: David Brownell; Grant Likely; spi-devel-general@lists.sourceforge.net; linux-ker...@vger.kernel.org Cc: qi.w...@intel.com; yong.y.w...@intel.com; joel.cl...@intel.com; kok.howg@intel.com; Tomoya MORINAGA Subject: [PATCH v4 1/2] spi_topcliff_pch: support new device ML7213 IOH Could you review this patch ? With Best Regards, - Tomoya MORINAGA OKI SEMICONDUCTOR CO., LTD. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ -- What Every C/C++ and Fortran developer Should Know! Read this article and learn how Intel has extended the reach of its next-generation tools to help Windows* and Linux* C/C++ and Fortran developers boost performance applications - including clusters. http://p.sf.net/sfu/intel-dev2devmay ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
RE: [PATCH v4 1/2] spi_topcliff_pch: support new device ML7213 IOH
Hi Grant Could you review this patch ASAP? There is little time to be integrated to 2.6.40. Thanks, - Tomoya MORINAGA OKI SEMICONDUCTOR CO., LTD. -Original Message- From: linux-kernel-ow...@vger.kernel.org [mailto:linux-kernel-ow...@vger.kernel.org] On Behalf Of Tomoya MORINAGA Sent: Tuesday, May 10, 2011 2:59 PM To: 'David Brownell'; 'Grant Likely'; spi-devel-general@lists.sourceforge.net; linux-ker...@vger.kernel.org Cc: qi.w...@intel.com; yong.y.w...@intel.com; joel.cl...@intel.com; kok.howg@intel.com Subject: RE: [PATCH v4 1/2] spi_topcliff_pch: support new device ML7213 IOH Hi Grant, Sent: Wednesday, April 27, 2011 11:23 AM To: David Brownell; Grant Likely; spi-devel-general@lists.sourceforge.net; linux-ker...@vger.kernel.org Cc: qi.w...@intel.com; yong.y.w...@intel.com; joel.cl...@intel.com; kok.howg@intel.com; Tomoya MORINAGA Subject: [PATCH v4 1/2] spi_topcliff_pch: support new device ML7213 IOH Could you review this patch ? With Best Regards, - Tomoya MORINAGA OKI SEMICONDUCTOR CO., LTD. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ -- What Every C/C++ and Fortran developer Should Know! Read this article and learn how Intel has extended the reach of its next-generation tools to help Windows* and Linux* C/C++ and Fortran developers boost performance applications - including clusters. http://p.sf.net/sfu/intel-dev2devmay ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
RE: [PATCH v4 1/2] spi_topcliff_pch: support new device ML7213 IOH
Hi Grant, Sent: Wednesday, April 27, 2011 11:23 AM To: David Brownell; Grant Likely; spi-devel-general@lists.sourceforge.net; linux-ker...@vger.kernel.org Cc: qi.w...@intel.com; yong.y.w...@intel.com; joel.cl...@intel.com; kok.howg@intel.com; Tomoya MORINAGA Subject: [PATCH v4 1/2] spi_topcliff_pch: support new device ML7213 IOH Could you review this patch ? With Best Regards, - Tomoya MORINAGA OKI SEMICONDUCTOR CO., LTD. -- Achieve unprecedented app performance and reliability What every C/C++ and Fortran developer should know. Learn how Intel has extended the reach of its next-generation tools to help boost performance applications - inlcuding clusters. http://p.sf.net/sfu/intel-dev2devmay ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH 2/2] spi_topcliff_pch: DMA support
This patch enables this SPI driver works with DMA mode.
Signed-off-by: Tomoya MORINAGA tomoya-li...@dsn.okisemi.com
---
drivers/spi/spi_topcliff_pch.c | 612
1 files changed, 492 insertions(+), 120 deletions(-)
diff --git a/drivers/spi/spi_topcliff_pch.c b/drivers/spi/spi_topcliff_pch.c
index 88bd472..f543ff6 100644
--- a/drivers/spi/spi_topcliff_pch.c
+++ b/drivers/spi/spi_topcliff_pch.c
@@ -28,6 +28,9 @@
#include linux/device.h
#include linux/platform_device.h
+#include linux/dmaengine.h
+#include linux/pch_dma.h
+
/* Register offsets */
#define PCH_SPCR 0x00/* SPI control register */
#define PCH_SPBRR 0x04/* SPI baud rate register */
@@ -36,7 +39,7 @@
#define PCH_SPDRR 0x10/* SPI read data register */
#define PCH_SSNXCR 0x18/* SSN Expand Control Register */
#define PCH_SRST 0x1C/* SPI reset register */
-#define PCH_SPI_ADDRESS_SIZE 0x20
+#define PCH_ADDRESS_SIZE 0x20
#define PCH_SPSR_TFD 0x07C0
#define PCH_SPSR_RFD 0xF800
@@ -54,8 +57,6 @@
#define STATUS_EXITING 2
#define PCH_SLEEP_TIME 10
-#define PCH_ADDRESS_SIZE 0x20
-
#define SSN_LOW0x02U
#define SSN_NO_CONTROL 0x00U
#define PCH_MAX_CS 0xFF
@@ -75,6 +76,7 @@
#define SPSR_TFI_BIT (1 0)
#define SPSR_RFI_BIT (1 1)
#define SPSR_FI_BIT(1 2)
+#define SPSR_ORF_BIT (1 3)
#define SPBRR_SIZE_BIT (1 10)
#define PCH_ALL
(SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\
@@ -83,10 +85,9 @@
#define SPCR_RFIC_FIELD20
#define SPCR_TFIC_FIELD16
-#define SPSR_INT_BITS 0x1F
-#define MASK_SPBRR_SPBR_BITS (~((1 10) - 1))
-#define MASK_RFIC_SPCR_BITS(~(0xf 20))
-#define MASK_TFIC_SPCR_BITS(~(0xf000f 12))
+#define MASK_SPBRR_SPBR_BITS ((1 10) - 1)
+#define MASK_RFIC_SPCR_BITS(0xf SPCR_RFIC_FIELD)
+#define MASK_TFIC_SPCR_BITS(0xf SPCR_TFIC_FIELD)
#define PCH_CLOCK_HZ 5000
#define PCH_MAX_SPBR 1023
@@ -102,6 +103,28 @@
*/
#define PCH_SPI_MAX_DEV2
+#define PCH_BUF_SIZE 4096
+#define PCH_DMA_TRANS_SIZE 12
+
+static int use_dma = 1;
+
+struct pch_spi_dma_ctrl {
+ struct dma_async_tx_descriptor *desc_tx;
+ struct dma_async_tx_descriptor *desc_rx;
+ struct pch_dma_slaveparam_tx;
+ struct pch_dma_slaveparam_rx;
+ struct dma_chan *chan_tx;
+ struct dma_chan *chan_rx;
+ struct scatterlist *sg_tx_p;
+ struct scatterlist *sg_rx_p;
+ struct scatterlist sg_tx;
+ struct scatterlist sg_rx;
+ int nent;
+ void*tx_buf_virt;
+ void*rx_buf_virt;
+ dma_addr_t tx_buf_dma;
+ dma_addr_t rx_buf_dma;
+};
/**
* struct pch_spi_data - Holds the SPI channel specific details
* @io_remap_addr: The remapped PCI base address
@@ -140,6 +163,7 @@
*/
struct pch_spi_data {
void __iomem *io_remap_addr;
+ unsigned long io_base_addr;
struct spi_master *master;
struct work_struct work;
struct workqueue_struct *wk;
@@ -162,6 +186,8 @@ struct pch_spi_data {
struct pch_spi_board_data *board_dat;
struct platform_device *plat_dev;
int ch;
+ struct pch_spi_dma_ctrl dma;
+ int use_dma;
u8 irq_reg_sts;
};
@@ -273,10 +299,10 @@ static void pch_spi_handler_sub(struct pch_spi_data
*data, u32 reg_spsr_val,
reg_spcr_val = ~SPCR_RFIE_BIT; /* disable RFI */
/* reset rx threshold */
- reg_spcr_val = MASK_RFIC_SPCR_BITS;
+ reg_spcr_val = ~MASK_RFIC_SPCR_BITS;
reg_spcr_val |= (PCH_RX_THOLD_MAX SPCR_RFIC_FIELD);
- iowrite32(((reg_spcr_val) = (~(SPCR_RFIE_BIT))),
-(io_remap_addr + PCH_SPCR));
+
+ iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR));
}
/* update counts */
@@ -287,12 +313,15 @@ static void pch_spi_handler_sub(struct pch_spi_data
*data, u32 reg_spsr_val,
/* if transfer complete interrupt */
if (reg_spsr_val SPSR_FI_BIT) {
- /* disable FI RFI interrupts */
- pch_spi_setclr_reg(data-master, PCH_SPCR, 0,
- SPCR_FIE_BIT | SPCR_RFIE_BIT);
+ if (tx_index bpw_len)
+ dev_err(data-master-dev,
+ %s : Transfer is not completed, __func__);
+ /* disable interrupts
[PATCH v4 1/2] spi_topcliff_pch: support new device ML7213 IOH
***Modify Grant's comments.
- Delete unrelated whitespace
- Prevent device driver from accessing platform data
- Add __devinit and __devexit
- Save pdev-dev to pd_dev-dev.parent
- Have own suspend/resume processing in platform_driver.
- Care returned value in pch_spi_init
- Change unregister order
Support ML7213 device of OKI SEMICONDUCTOR.
ML7213 is companion chip of Intel Atom E6xx series for IVI(In-Vehicle
Infotainment).
ML7213 is compatible for Intel EG20T PCH.
Signed-off-by: Tomoya MORINAGA tomoya-li...@dsn.okisemi.com
---
drivers/spi/Kconfig|5 +-
drivers/spi/spi_topcliff_pch.c | 599 +---
2 files changed, 317 insertions(+), 287 deletions(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index fc14b8d..ed6134b 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -380,12 +380,15 @@ config SPI_TI_SSP
module will be called ti-ssp-spi.
config SPI_TOPCLIFF_PCH
- tristate Topcliff PCH SPI Controller
+ tristate Intel EG20T PCH/OKI SEMICONDUCTOR ML7213 IOH SPI controller
depends on PCI
help
SPI driver for the Topcliff PCH (Platform Controller Hub) SPI bus
used in some x86 embedded processors.
+ This driver also supports the ML7213, a companion chip for the
+ Atom E6xx series and compatible with the Intel EG20T PCH.
+
config SPI_TXX9
tristate Toshiba TXx9 SPI controller
depends on GENERIC_GPIO CPU_TX49XX
diff --git a/drivers/spi/spi_topcliff_pch.c b/drivers/spi/spi_topcliff_pch.c
index 79e48d4..88bd472 100644
--- a/drivers/spi/spi_topcliff_pch.c
+++ b/drivers/spi/spi_topcliff_pch.c
@@ -26,6 +26,7 @@
#include linux/spi/spidev.h
#include linux/module.h
#include linux/device.h
+#include linux/platform_device.h
/* Register offsets */
#define PCH_SPCR 0x00/* SPI control register */
@@ -35,6 +36,7 @@
#define PCH_SPDRR 0x10/* SPI read data register */
#define PCH_SSNXCR 0x18/* SSN Expand Control Register */
#define PCH_SRST 0x1C/* SPI reset register */
+#define PCH_SPI_ADDRESS_SIZE 0x20
#define PCH_SPSR_TFD 0x07C0
#define PCH_SPSR_RFD 0xF800
@@ -75,7 +77,8 @@
#define SPSR_FI_BIT(1 2)
#define SPBRR_SIZE_BIT (1 10)
-#define PCH_ALL
(SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|SPCR_ORIE_BIT|SPCR_MDFIE_BIT)
+#define PCH_ALL
(SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\
+ SPCR_ORIE_BIT|SPCR_MDFIE_BIT)
#define SPCR_RFIC_FIELD20
#define SPCR_TFIC_FIELD16
@@ -88,6 +91,16 @@
#define PCH_CLOCK_HZ 5000
#define PCH_MAX_SPBR 1023
+/* Definition for ML7213 by OKI SEMICONDUCTOR */
+#define PCI_VENDOR_ID_ROHM 0x10DB
+#define PCI_DEVICE_ID_ML7213_SPI 0x802c
+
+/*
+ * Set the number of SPI instance max
+ * Intel EG20T PCH : 1ch
+ * OKI SEMICONDUCTOR ML7213 IOH : 2ch
+*/
+#define PCH_SPI_MAX_DEV2
/**
* struct pch_spi_data - Holds the SPI channel specific details
@@ -121,6 +134,9 @@
* @cur_trans: The current transfer that this SPI driver is
* handling
* @board_dat: Reference to the SPI device data structure
+ * @plat_dev: platform_device structure
+ * @ch:SPI channel number
+ * @irq_reg_sts: Status of IRQ registration
*/
struct pch_spi_data {
void __iomem *io_remap_addr;
@@ -144,27 +160,33 @@ struct pch_spi_data {
struct spi_message *current_msg;
struct spi_transfer *cur_trans;
struct pch_spi_board_data *board_dat;
+ struct platform_device *plat_dev;
+ int ch;
+ u8 irq_reg_sts;
};
/**
* struct pch_spi_board_data - Holds the SPI device specific details
* @pdev: Pointer to the PCI device
- * @irq_reg_sts: Status of IRQ registration
- * @pci_req_sts: Status of pci_request_regions
* @suspend_sts: Status of suspend
- * @data: Pointer to SPI channel data structure
+ * @num: The number of SPI device instance
*/
struct pch_spi_board_data {
struct pci_dev *pdev;
- u8 irq_reg_sts;
- u8 pci_req_sts;
u8 suspend_sts;
- struct pch_spi_data *data;
+ int num;
+};
+
+struct pch_pd_dev_save {
+ int num;
+ struct platform_device *pd_save[PCH_SPI_MAX_DEV];
+ struct pch_spi_board_data *board_dat;
};
static struct pci_device_id pch_spi_pcidev_id[] = {
- {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_GE_SPI)},
- {0,}
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI),1, },
+ { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
+ { }
};
/**
@@ -283,11 +305,11 @@ static void pch_spi_handler_sub
RE: [PATCH v3] spi_topcliff_pch: support new device ML7213 IOH
Hi Grant, Could you review this patch ? We do hope this patch will be merged for 2.6.39. Thanks in advance, - Tomoya MORINAGA OKI SEMICONDUCTOR CO., LTD. -Original Message- From: Tomoya MORINAGA [mailto:tomoya-li...@dsn.okisemi.com] Sent: Thursday, March 17, 2011 9:08 AM To: 'David Brownell'; 'Grant Likely'; 'spi-devel-general@lists.sourceforge.net'; 'linux-ker...@vger.kernel.org' Cc: 'qi.w...@intel.com'; 'yong.y.w...@intel.com'; 'joel.cl...@intel.com'; 'kok.howg@intel.com' Subject: RE: [PATCH v3] spi_topcliff_pch: support new device ML7213 IOH Hi Grant, Could you review this patch ? We hope this patch will be merged for 2.6.39. With Best Regards, - Tomoya MORINAGA OKI SEMICONDUCTOR CO., LTD. -Original Message- From: Tomoya MORINAGA [mailto:tomoya-li...@dsn.okisemi.com] Sent: Monday, February 28, 2011 8:48 PM To: David Brownell; Grant Likely; spi-devel-general@lists.sourceforge.net; linux-ker...@vger.kernel.org Cc: qi.w...@intel.com; yong.y.w...@intel.com; joel.cl...@intel.com; kok.howg@intel.com; Tomoya MORINAGA Subject: [PATCH v3] spi_topcliff_pch: support new device ML7213 IOH Support ML7213 device of OKI SEMICONDUCTOR. ML7213 is companion chip of Intel Atom E6xx series for IVI(In-Vehicle Infotainment). ML7213 is compatible for Intel EG20T PCH. Signed-off-by: Tomoya MORINAGA tomoya-li...@dsn.okisemi.com --- drivers/spi/Kconfig|5 +- drivers/spi/spi_topcliff_pch.c | 481 2 files changed, 250 insertions(+), 236 deletions(-) -- Enable your software for Intel(R) Active Management Technology to meet the growing manageability and security demands of your customers. Businesses are taking advantage of Intel(R) vPro (TM) technology - will your software be a part of the solution? Download the Intel(R) Manageability Checker today! http://p.sf.net/sfu/intel-dev2devmar ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
RE: spi_topcliff_pch: reload issue
Hi, Previous my question included mistake. I show modified below. insmod spi_topcliff_pch.ko(Then, both /dev/spidev0.0/1.0 are created with success) rmmod spi_topcliff_pch.ko (Then, both /dev/spidev0.0/1.0 are NOT deleted.) insmod spi_topcliff_pch.ko(Then, kernel error occurred. Attached err_log) I attached source code(power management is not updated) and kernel error log. Do you have any information about the above ? With Best Regards, - Tomoya MORINAGA OKI SEMICONDUCTOR CO., LTD. -Original Message- From: Tomoya MORINAGA [mailto:morinaga...@dsn.okisemi.com] Sent: Tuesday, February 22, 2011 10:22 AM To: 'David Brownell'; 'Grant Likely'; 'spi-devel-general@lists.sourceforge.net'; 'linux-ker...@vger.kernel.org' Cc: 'qi.w...@intel.com'; 'yong.y.w...@intel.com'; 'joel.cl...@intel.com'; 'kok.howg@intel.com'; Toshiharu Okada Subject: spi_topcliff_pch: reload issue Hi, issue: after reload the spi module, it can't do SPI communication. We have faced issue when execute the following command. insmod xxx.ko(Then, /dev/spidev0.0 is created with success) rmmod xxx.ko (Then, /dev/spidev0.0 is deleted with success) insmod xxx.ko(Then, /dev/spidev0.0 is created, however, below error message is showed) :02:0c.1: registered master spi0 :02:0c.1: chipselect 0 already in use :02:0c.1: can't create new device for spidev Do you have any information about the above ? kernel=2.6.37 on FC14 With Best Regards, - Tomoya MORINAGA OKI SEMICONDUCTOR CO., LTD. /* * SPI bus driver for the Topcliff PCH used by Intel SoCs * * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. */ #include linux/delay.h #include linux/pci.h #include linux/wait.h #include linux/spi/spi.h #include linux/interrupt.h #include linux/sched.h #include linux/spi/spidev.h #include linux/module.h #include linux/device.h #include linux/platform_device.h /* Register offsets */ #define PCH_SPCR0x00/* SPI control register */ #define PCH_SPBRR 0x04/* SPI baud rate register */ #define PCH_SPSR0x08/* SPI status register */ #define PCH_SPDWR 0x0C/* SPI write data register */ #define PCH_SPDRR 0x10/* SPI read data register */ #define PCH_SSNXCR 0x18/* SSN Expand Control Register */ #define PCH_SRST0x1C/* SPI reset register */ #define PCH_SPI_ADDRESS_SIZE0x20 #define PCH_SPSR_TFD0x07C0 #define PCH_SPSR_RFD0xF800 #define PCH_READABLE(x) (((x) PCH_SPSR_RFD)11) #define PCH_WRITABLE(x) (((x) PCH_SPSR_TFD)6) #define PCH_RX_THOLD7 #define PCH_RX_THOLD_MAX15 #define PCH_MAX_BAUDRATE500 #define PCH_MAX_FIFO_DEPTH 16 #define STATUS_RUNNING 1 #define STATUS_EXITING 2 #define PCH_SLEEP_TIME 10 #define PCH_ADDRESS_SIZE0x20 #define SSN_LOW 0x02U #define SSN_NO_CONTROL 0x00U #define PCH_MAX_CS 0xFF #define PCI_DEVICE_ID_GE_SPI0x8816 #define SPCR_SPE_BIT(1 0) #define SPCR_MSTR_BIT (1 1) #define SPCR_LSBF_BIT (1 4) #define SPCR_CPHA_BIT (1 5) #define SPCR_CPOL_BIT (1 6) #define SPCR_TFIE_BIT (1 8) #define SPCR_RFIE_BIT (1 9) #define SPCR_FIE_BIT(1 10) #define SPCR_ORIE_BIT (1 11) #define SPCR_MDFIE_BIT (1 12) #define SPCR_FICLR_BIT (1 24) #define SPSR_TFI_BIT(1 0) #define SPSR_RFI_BIT(1 1) #define SPSR_FI_BIT (1 2) #define SPBRR_SIZE_BIT (1 10) #define PCH_ALL (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|SPCR_ORIE_BIT|SPCR_MDFIE_BIT) #define SPCR_RFIC_FIELD 20 #define SPCR_TFIC_FIELD 16 #define SPSR_INT_BITS 0x1F #define MASK_SPBRR_SPBR_BITS(~((1 10) - 1)) #define MASK_RFIC_SPCR_BITS (~(0xf 20)) #define MASK_TFIC_SPCR_BITS (~(0xf000f 12)) #define PCH_CLOCK_HZ5000 #define PCH_MAX_SPBR1023 /* Definition for ML7213 by OKI SEMICONDUCTOR */ #define PCI_VENDOR_ID_ROHM 0x10DB #define PCI_DEVICE_ID_ML7213_SPI
RE: [PATCH v2] spi_topcliff_pch: support new device ML7213 IOH
Hi Grant,
Could you review my patch ?
With Best Regards,
-
Tomoya MORINAGA
OKI SEMICONDUCTOR CO., LTD.
-Original Message-
From: Tomoya MORINAGA [mailto:tomoya-li...@dsn.okisemi.com]
Sent: Wednesday, January 26, 2011 5:07 PM
To: David Brownell; Grant Likely;
spi-devel-general@lists.sourceforge.net; linux-ker...@vger.kernel.org
Cc: qi.w...@intel.com; yong.y.w...@intel.com;
joel.cl...@intel.com; kok.howg@intel.com; Tomoya MORINAGA
Subject: [PATCH v2] spi_topcliff_pch: support new device ML7213 IOH
Support ML7213 device of OKI SEMICONDUCTOR.
ML7213 is companion chip of Intel Atom E6xx series for
IVI(In-Vehicle Infotainment).
ML7213 is completely compatible for Intel EG20T PCH.
Signed-off-by: Tomoya MORINAGA tomoya-li...@dsn.okisemi.com
---
drivers/spi/Kconfig|7 +-
drivers/spi/spi_topcliff_pch.c | 450
++--
2 files changed, 250 insertions(+), 207 deletions(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index
bb233a9..f36631c 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -351,12 +351,17 @@ config SPI_TEGRA
SPI driver for NVidia Tegra SoCs
config SPI_TOPCLIFF_PCH
- tristate Topcliff PCH SPI Controller
+ tristate Intel EG20T PCH/OKI SEMICONDUCTOR ML7213 IOH
SPI controller
depends on PCI
help
SPI driver for the Topcliff PCH (Platform Controller
Hub) SPI bus
used in some x86 embedded processors.
+ This driver also can be used for OKI SEMICONDUCTOR's
ML7213 IOH which
+ is for IVI(In-Vehicle Infotainment) use.
+ ML7213 IOH is companion chip for Intel Atom E6xx series.
+ ML7213 IOH is completely compatible for Intel EG20T PCH.
+
config SPI_TXX9
tristate Toshiba TXx9 SPI controller
depends on GENERIC_GPIO CPU_TX49XX
diff --git a/drivers/spi/spi_topcliff_pch.c
b/drivers/spi/spi_topcliff_pch.c index 79e48d4..81feb11 100644
--- a/drivers/spi/spi_topcliff_pch.c
+++ b/drivers/spi/spi_topcliff_pch.c
@@ -26,6 +26,7 @@
#include linux/spi/spidev.h
#include linux/module.h
#include linux/device.h
+#include linux/platform_device.h
/* Register offsets */
#define PCH_SPCR 0x00/* SPI control register */
@@ -35,6 +36,7 @@
#define PCH_SPDRR0x10/* SPI read data register */
#define PCH_SSNXCR 0x18/* SSN Expand Control
Register */
#define PCH_SRST 0x1C/* SPI reset register */
+#define PCH_SPI_ADDRESS_SIZE 0x20
#define PCH_SPSR_TFD 0x07C0
#define PCH_SPSR_RFD 0xF800
@@ -88,6 +90,16 @@
#define PCH_CLOCK_HZ 5000
#define PCH_MAX_SPBR 1023
+/* Definition for ML7213 by OKI SEMICONDUCTOR */
+#define PCI_VENDOR_ID_ROHM 0x10DB
+#define PCI_DEVICE_ID_ML7213_SPI 0x802c
+
+/*
+Set the number of SPI instance max
+Intel EG20T PCH :1ch
+OKI SEMICONDUCTOR ML7213 IOH : 2ch
+*/
+#define PCH_SPI_MAX_DEV 2
/**
* struct pch_spi_data - Holds the SPI channel specific
details @@ -121,6 +133,8 @@
* @cur_trans: The current transfer
that this SPI driver is
* handling
* @board_dat: Reference to the SPI
device data structure
+ * @plat_dev:platform_device structure
+ * @ch: SPI channel number
*/
struct pch_spi_data {
void __iomem *io_remap_addr;
@@ -144,6 +158,8 @@ struct pch_spi_data {
struct spi_message *current_msg;
struct spi_transfer *cur_trans;
struct pch_spi_board_data *board_dat;
+ struct platform_device plat_dev;
+ int ch;
};
/**
@@ -153,18 +169,21 @@ struct pch_spi_data {
* @pci_req_sts: Status of pci_request_regions
* @suspend_sts: Status of suspend
* @data:Pointer to SPI channel data structure
+ * @num: The number of SPI device instance
*/
struct pch_spi_board_data {
struct pci_dev *pdev;
u8 irq_reg_sts;
u8 pci_req_sts;
u8 suspend_sts;
- struct pch_spi_data *data;
+ struct pch_spi_data *data[PCH_SPI_MAX_DEV];
+ int num;
};
static struct pci_device_id pch_spi_pcidev_id[] = {
- {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_GE_SPI)},
- {0,}
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI),1, },
+ { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
+ { }
};
/**
@@ -288,6 +307,7 @@ static irqreturn_t pch_spi_handler(int
irq, void *dev_id)
void __iomem *io_remap_addr;
irqreturn_t ret = IRQ_NONE;
struct pch_spi_board_data *board_dat = dev_id;
+ int i;
if (board_dat-suspend_sts) {
dev_dbg(board_dat-pdev-dev,
@@ -295,21 +315,21 @@ static irqreturn_t pch_spi_handler(int
irq, void *dev_id
[PATCH v2] spi_topcliff_pch: support new device ML7213 IOH
Support ML7213 device of OKI SEMICONDUCTOR.
ML7213 is companion chip of Intel Atom E6xx series for IVI(In-Vehicle
Infotainment).
ML7213 is completely compatible for Intel EG20T PCH.
Signed-off-by: Tomoya MORINAGA tomoya-li...@dsn.okisemi.com
---
drivers/spi/Kconfig|7 +-
drivers/spi/spi_topcliff_pch.c | 450 ++--
2 files changed, 250 insertions(+), 207 deletions(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index bb233a9..f36631c 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -351,12 +351,17 @@ config SPI_TEGRA
SPI driver for NVidia Tegra SoCs
config SPI_TOPCLIFF_PCH
- tristate Topcliff PCH SPI Controller
+ tristate Intel EG20T PCH/OKI SEMICONDUCTOR ML7213 IOH SPI controller
depends on PCI
help
SPI driver for the Topcliff PCH (Platform Controller Hub) SPI bus
used in some x86 embedded processors.
+ This driver also can be used for OKI SEMICONDUCTOR's ML7213 IOH which
+ is for IVI(In-Vehicle Infotainment) use.
+ ML7213 IOH is companion chip for Intel Atom E6xx series.
+ ML7213 IOH is completely compatible for Intel EG20T PCH.
+
config SPI_TXX9
tristate Toshiba TXx9 SPI controller
depends on GENERIC_GPIO CPU_TX49XX
diff --git a/drivers/spi/spi_topcliff_pch.c b/drivers/spi/spi_topcliff_pch.c
index 79e48d4..81feb11 100644
--- a/drivers/spi/spi_topcliff_pch.c
+++ b/drivers/spi/spi_topcliff_pch.c
@@ -26,6 +26,7 @@
#include linux/spi/spidev.h
#include linux/module.h
#include linux/device.h
+#include linux/platform_device.h
/* Register offsets */
#define PCH_SPCR 0x00/* SPI control register */
@@ -35,6 +36,7 @@
#define PCH_SPDRR 0x10/* SPI read data register */
#define PCH_SSNXCR 0x18/* SSN Expand Control Register */
#define PCH_SRST 0x1C/* SPI reset register */
+#define PCH_SPI_ADDRESS_SIZE 0x20
#define PCH_SPSR_TFD 0x07C0
#define PCH_SPSR_RFD 0xF800
@@ -88,6 +90,16 @@
#define PCH_CLOCK_HZ 5000
#define PCH_MAX_SPBR 1023
+/* Definition for ML7213 by OKI SEMICONDUCTOR */
+#define PCI_VENDOR_ID_ROHM 0x10DB
+#define PCI_DEVICE_ID_ML7213_SPI 0x802c
+
+/*
+Set the number of SPI instance max
+Intel EG20T PCH : 1ch
+OKI SEMICONDUCTOR ML7213 IOH : 2ch
+*/
+#define PCH_SPI_MAX_DEV2
/**
* struct pch_spi_data - Holds the SPI channel specific details
@@ -121,6 +133,8 @@
* @cur_trans: The current transfer that this SPI driver is
* handling
* @board_dat: Reference to the SPI device data structure
+ * @plat_dev: platform_device structure
+ * @ch:SPI channel number
*/
struct pch_spi_data {
void __iomem *io_remap_addr;
@@ -144,6 +158,8 @@ struct pch_spi_data {
struct spi_message *current_msg;
struct spi_transfer *cur_trans;
struct pch_spi_board_data *board_dat;
+ struct platform_device plat_dev;
+ int ch;
};
/**
@@ -153,18 +169,21 @@ struct pch_spi_data {
* @pci_req_sts: Status of pci_request_regions
* @suspend_sts: Status of suspend
* @data: Pointer to SPI channel data structure
+ * @num: The number of SPI device instance
*/
struct pch_spi_board_data {
struct pci_dev *pdev;
u8 irq_reg_sts;
u8 pci_req_sts;
u8 suspend_sts;
- struct pch_spi_data *data;
+ struct pch_spi_data *data[PCH_SPI_MAX_DEV];
+ int num;
};
static struct pci_device_id pch_spi_pcidev_id[] = {
- {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_GE_SPI)},
- {0,}
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI),1, },
+ { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
+ { }
};
/**
@@ -288,6 +307,7 @@ static irqreturn_t pch_spi_handler(int irq, void *dev_id)
void __iomem *io_remap_addr;
irqreturn_t ret = IRQ_NONE;
struct pch_spi_board_data *board_dat = dev_id;
+ int i;
if (board_dat-suspend_sts) {
dev_dbg(board_dat-pdev-dev,
@@ -295,21 +315,21 @@ static irqreturn_t pch_spi_handler(int irq, void *dev_id)
return IRQ_NONE;
}
- data = board_dat-data;
- io_remap_addr = data-io_remap_addr;
- spsr = io_remap_addr + PCH_SPSR;
+ for (i = 0; i board_dat-num; i++) {
+ data = board_dat-data[i];
+ io_remap_addr = data-io_remap_addr;
+ spsr = io_remap_addr + PCH_SPSR;
+ reg_spsr_val = ioread32(spsr);
- reg_spsr_val = ioread32(spsr);
+ /* Check if the interrupt is for SPI device */
+ if (reg_spsr_val (SPSR_FI_BIT | SPSR_RFI_BIT)) {
+ pch_spi_handler_sub(data, reg_spsr_val
RE: [PATCH 1/3] spi_topcliff_pch: support new device ML7213
Hi Grant, Thank you for your explanation. On Saturday, January 22, 2011 3:49 AM, Grant Likely wrote: Am I correct so far? No, not true. Both Topcliff(Intel EG20 PCH) and OKISEMI ML7213 IOH SPI devices can't use multi-ChipSelect but 1 ChipSelect only. I show the my modified diagram below. - Currently upstreamed version, /sys/devices/.../:00:1a.0 (pci_dev bound to driver 'pch_spi_pcidev') | \--spi0.0 (spi_device 0 on spi_master 0) - I posted before version. /sys/devices/.../:00:1a.0 (pci_dev bound to driver 'pch_spi_pcidev') | +--spi0.0 (spi_device 0 on spi_master 0) | \--spi1.0 (spi_device 0 on spi_master 1) - Your anticipated becomes like below /sys/devices/.../:00:1a.0 (pci_dev bound to driver 'pch_spi_pcidev') | +--pch_spi.0 | | | +--spi0.0 (spi_device 0 on spi_master 0) | \--pch_spi.1 | \--spi1.0 (spi_device 0 on spi_master 1) Still above, don't you change your opinion? Make sense? I probably understand your saying. You mean insert platform_device as wrapper between pci_driver and spi_topcliff_pch. Thanks, - Tomoya MORINAGA OKI SEMICONDUCTOR CO., LTD. -- Special Offer-- Download ArcSight Logger for FREE (a $49 USD value)! Finally, a world-class log management solution at an even better price-free! Download using promo code Free_Logger_4_Dev2Dev. Offer expires February 28th, so secure your free ArcSight Logger TODAY! http://p.sf.net/sfu/arcsight-sfd2d ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
RE: [PATCH 1/3] spi_topcliff_pch: support new device ML7213
Hi Grant,
Need your help!
Could you give us your answer ?
Thanks,
-
Tomoya MORINAGA
OKI SEMICONDUCTOR CO., LTD.
-Original Message-
From: linux-kernel-ow...@vger.kernel.org
[mailto:linux-kernel-ow...@vger.kernel.org] On Behalf Of
Tomoya MORINAGA
Sent: Wednesday, January 12, 2011 2:27 PM
To: 'Milton Miller'; 'Grant Likely'
Cc: 'David Brownell';
spi-devel-general@lists.sourceforge.net;
linux-ker...@vger.kernel.org; yong.y.w...@intel.com;
joel.cl...@intel.com; kok.howg@intel.com; 'Toshiharu
Okada'; 'Wang, Qi'
Subject: RE: [PATCH 1/3] spi_topcliff_pch: support new device ML7213
On Tuesday, January 11, 2011 6:42 PM, Tomoya MORINAGA wrote:
However, I couldn't clear my question.
I show the current our coding image.
Is the following agreeable with your saying ?
struct spi_platform_data {
u16 num_chipselect;
bool little_endian;
u8 bits_per_word;
struct spi_board_info *devices;
u8 num_devices;
};
static struct resource pch_spi_resources[] = {
{
.start = 0,
.end= 0,
.flags = IORESOURCE_MEM,
},
{
.start = 0,
.end= 0,
.flags = IORESOURCE_IRQ,
},
};
static struct spi_platform_data pch_spi_platform_data = {
.num_chipselect = 2,
.little_endian = true,
};
static struct pch_spi_cell pch_spi_cfg0 = {
.name = pch_spi,
.num_resources = ARRAY_SIZE(pch_spi_resources),
.resources = pch_spi_resources,
.platform_data = pch_spi_platform_data,
.data_size = sizeof(pch_spi_platform_data), };
static int pch_spi_get_resources(struct pch_spi_board_data
*board_dat, int num) {
int retval;
int i;
/* create workqueue */
board_dat-data[num]-wk =
create_singlethread_workqueue(KBUILD_MODNAME);
pci_request_regions(board_dat-pdev, KBUILD_MODNAME); }
static int pch_spi_add_device(struct device *parent, int id,
struct pch_spi_cell *cell,
struct resource *mem_base, int irq_base,
struct pch_spi_board_data *board_dat) {
platform_device_alloc(cell-name, id + cell-id);
res = kzalloc(sizeof(*res) * cell-num_resources, GFP_KERNEL);
if (!res)
goto fail_device;
platform_set_drvdata(pdev, cell-driver_data);
if (cell-data_size) {
platform_device_add_data(pdev,
cell-platform_data,
cell-data_size);
}
for (i = 0; i cell-num_resources; i++) {
if ((cell-resources[i].flags IORESOURCE_MEM)
mem_base) {
res[i].parent =
res[i].start =
res[i].end =
} else if (cell-resources[i].flags IORESOURCE_IRQ) {
res[i].start =
res[i].end =
} else {
}
ret = platform_device_add_resources(pdev, res,
cell-num_resources);
if (ret)
goto fail_res;
ret = platform_device_add(pdev);
if (ret)
goto fail_res;
kfree(res);
spi_alloc_master( );
board_dat-data[num] = spi_master_get_devdata( );
pch_spi_get_resources( );
/* set master mode */
pch_spi_set_master_mode( );
/* Register the controller with the SPI core. */
spi_register_master( );
return 0;
}
int pch_spi_add_devices(struct device *parent,
struct pch_spi_cell *cells, int n_devs,
struct resource *mem_base,
struct pch_spi_board_data *board_dat) {
pci_iomap()
for (i n_devs)
pch_spi_add_device()
}
static int pch_spi_probe(struct pci_dev *pdev, const struct
pci_device_id *id) {
board_dat = kzalloc(sizeof(struct pch_spi_board_data),
GFP_KERNEL);
pci_enable_device()
request_irq()
pch_spi_add_devices(pdev-dev,
pch_spi_cfg0,
2,
pdev-resource[0], board_dat);
}
static irqreturn_t pch_spi_handler(int irq, void *dev_id) {
for (i = 0; i board_dat-num; i++) {
data = board_dat-data[i];
io_remap_addr = data-io_remap_addr;
spsr = io_remap_addr + PCH_SPSR;
reg_spsr_val = ioread32(spsr);
/* Check if the interrupt is for SPI device */
if (reg_spsr_val (SPSR_FI_BIT | SPSR_RFI_BIT)) {
pch_spi_handler_sub(data, reg_spsr_val,
io_remap_addr);
ret = IRQ_HANDLED;
}
dev_dbg(board_dat-pdev-dev, %s EXIT return
value=%d\n,
__func__, ret);
}
return ret;
}
Thanks
RE: [PATCH 1/3] spi_topcliff_pch: support new device ML7213
Hi Grant, On Friday, January 07, 2011 6:22 PM, Milton Miller wrote: follow mfd_add_devices into drivers/mfd/mfd-core.c I have also seen mfd-core.c. However, I couldn't clear my question. Q1. It seems platform_device is not used in your example. Does need platform_device ? Q2. How detect pch_spi channel dynamically ? I want to catch your saying correctly. Could you give me more information ? Thanks, - Tomoya MORINAGA OKI SEMICONDUCTOR CO., LTD. -- Gaining the trust of online customers is vital for the success of any company that requires sensitive data to be transmitted over the Web. Learn how to best implement a security strategy that keeps consumers' information secure and instills the confidence they need to proceed with transactions. http://p.sf.net/sfu/oracle-sfdevnl ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
RE: [PATCH 1/3] spi_topcliff_pch: support new device ML7213
Resend (Previous destination address is broken partly.) Hi Grant, On Friday, January 07, 2011 6:22 PM, Milton Miller wrote: follow mfd_add_devices into drivers/mfd/mfd-core.c I have also seen mfd-core.c. However, I couldn't clear my question. Q1. It seems platform_device is not used in your example. Does need platform_device ? Q2. How detect pch_spi channel dynamically ? I want to catch your saying correctly. Could you give me more information ? Thanks, - Tomoya MORINAGA OKI SEMICONDUCTOR CO., LTD. -- Gaining the trust of online customers is vital for the success of any company that requires sensitive data to be transmitted over the Web. Learn how to best implement a security strategy that keeps consumers' information secure and instills the confidence they need to proceed with transactions. http://p.sf.net/sfu/oracle-sfdevnl ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
RE: [PATCH 1/3] spi_topcliff_pch: support new device ML7213
On Tuesday, January 11, 2011 6:42 PM, Tomoya MORINAGA wrote:
However, I couldn't clear my question.
I show the current our coding image.
Is the following agreeable with your saying ?
struct spi_platform_data {
u16 num_chipselect;
bool little_endian;
u8 bits_per_word;
struct spi_board_info *devices;
u8 num_devices;
};
static struct resource pch_spi_resources[] = {
{
.start = 0,
.end= 0,
.flags = IORESOURCE_MEM,
},
{
.start = 0,
.end= 0,
.flags = IORESOURCE_IRQ,
},
};
static struct spi_platform_data pch_spi_platform_data = {
.num_chipselect = 2,
.little_endian = true,
};
static struct pch_spi_cell pch_spi_cfg0 = {
.name = pch_spi,
.num_resources = ARRAY_SIZE(pch_spi_resources),
.resources = pch_spi_resources,
.platform_data = pch_spi_platform_data,
.data_size = sizeof(pch_spi_platform_data),
};
static int pch_spi_get_resources(struct pch_spi_board_data *board_dat, int num)
{
int retval;
int i;
/* create workqueue */
board_dat-data[num]-wk =
create_singlethread_workqueue(KBUILD_MODNAME);
pci_request_regions(board_dat-pdev, KBUILD_MODNAME);
}
static int pch_spi_add_device(struct device *parent, int id,
struct pch_spi_cell *cell,
struct resource *mem_base, int irq_base,
struct pch_spi_board_data *board_dat)
{
platform_device_alloc(cell-name, id + cell-id);
res = kzalloc(sizeof(*res) * cell-num_resources, GFP_KERNEL);
if (!res)
goto fail_device;
platform_set_drvdata(pdev, cell-driver_data);
if (cell-data_size) {
platform_device_add_data(pdev,
cell-platform_data, cell-data_size);
}
for (i = 0; i cell-num_resources; i++) {
if ((cell-resources[i].flags IORESOURCE_MEM) mem_base) {
res[i].parent =
res[i].start =
res[i].end =
} else if (cell-resources[i].flags IORESOURCE_IRQ) {
res[i].start =
res[i].end =
} else {
}
ret = platform_device_add_resources(pdev, res, cell-num_resources);
if (ret)
goto fail_res;
ret = platform_device_add(pdev);
if (ret)
goto fail_res;
kfree(res);
spi_alloc_master( );
board_dat-data[num] = spi_master_get_devdata( );
pch_spi_get_resources( );
/* set master mode */
pch_spi_set_master_mode( );
/* Register the controller with the SPI core. */
spi_register_master( );
return 0;
}
int pch_spi_add_devices(struct device *parent,
struct pch_spi_cell *cells, int n_devs,
struct resource *mem_base,
struct pch_spi_board_data *board_dat)
{
pci_iomap()
for (i n_devs)
pch_spi_add_device()
}
static int pch_spi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
board_dat = kzalloc(sizeof(struct pch_spi_board_data), GFP_KERNEL);
pci_enable_device()
request_irq()
pch_spi_add_devices(pdev-dev,
pch_spi_cfg0,
2,
pdev-resource[0], board_dat);
}
static irqreturn_t pch_spi_handler(int irq, void *dev_id)
{
for (i = 0; i board_dat-num; i++) {
data = board_dat-data[i];
io_remap_addr = data-io_remap_addr;
spsr = io_remap_addr + PCH_SPSR;
reg_spsr_val = ioread32(spsr);
/* Check if the interrupt is for SPI device */
if (reg_spsr_val (SPSR_FI_BIT | SPSR_RFI_BIT)) {
pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr);
ret = IRQ_HANDLED;
}
dev_dbg(board_dat-pdev-dev, %s EXIT return value=%d\n,
__func__, ret);
}
return ret;
}
Thanks,
-
Tomoya MORINAGA
OKI SEMICONDUCTOR CO., LTD.
--
Protect Your Site and Customers from Malware Attacks
Learn about various malware tactics and how to avoid them. Understand
malware threats, the impact they can have on your business, and how you
can protect your company and customers by using code signing.
http://p.sf.net/sfu/oracle-sfdevnl
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
RE: [PATCH 1/3] spi_topcliff_pch: support new device ML7213
Hi Milton, On Friday, January 07, 2011 6:22 PM, Milton Miller wrote: follow mfd_add_devices into drivers/mfd/mfd-core.c It seems mfd_add_devices/mfd_add_device are valuable for us. I'll study this. Thanks, - Tomoya MORINAGA OKI SEMICONDUCTOR CO., LTD. -- Gaining the trust of online customers is vital for the success of any company that requires sensitive data to be transmitted over the Web. Learn how to best implement a security strategy that keeps consumers' information secure and instills the confidence they need to proceed with transactions. http://p.sf.net/sfu/oracle-sfdevnl ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
RE: [PATCH 1/3] spi_topcliff_pch: support new device ML7213
Hi Grant, On Thursday, January 06, 2011 1:39 AM, Grant Likely wrote: As far as examples go, drivers/mfd/timberdale.c seems reasonable, if a bit larger than what you need. Thank you for your suggestion. However, though seeing this driver, I didn't understand your intention. It seems platform_device/platform_driver are not used in this. Which part of this driver do you want to show me as reference ? Thanks, - Tomoya MORINAGA OKI SEMICONDUCTOR CO., LTD. -Original Message- From: Grant Likely [mailto:glik...@secretlab.ca] On Behalf Of Grant Likely Sent: Thursday, January 06, 2011 1:39 AM To: Tomoya MORINAGA Cc: David Brownell; spi-devel-general@lists.sourceforge.net; linux-ker...@vger.kernel.org; qi.w...@intel.com; yong.y.w...@intel.com; joel.cl...@intel.com; kok.howg@intel.com; Toshiharu Okada Subject: Re: [PATCH 1/3] spi_topcliff_pch: support new device ML7213 On Wed, Jan 05, 2011 at 11:34:20AM +0900, Tomoya MORINAGA wrote: Hi Grant, On Wednesday, December 29, 2010 3:49 PM, Grant Likely wrote: As previously discussed on this list, I would like to see support for multiple bus instances implemented differently. Rather than storing the spi_master instances in an array in the pci device private data, the pci device should register a separate platform_device for each spi bus instance, and each of those bus instances should get bound to a topcliff_spi_bus driver which doesn't need to have any special knowledge about how many spi_master instances actually exist. Basically, the way it is implemented in this patch isn't taking advantage of the infrastructure and instance management provided by the driver model. I see. I will modify like your suggestion. Could you show the reference SPI driver using multi-instance ? In an multi-instance scenario, the spi driver is just a plain-jane platform_driver. There isn't anything special about it. Instead, the pci_driver becomes responsible to register one or more platform devices for the child busses. Much like one of the multifunction devices in drivers/mfd. As far as examples go, drivers/mfd/timberdale.c seems reasonable, if a bit larger than what you need. g. Thanks, --- Tomoya MORINAGA OKI SEMICONDUCTOR CO., LTD. -- Gaining the trust of online customers is vital for the success of any company that requires sensitive data to be transmitted over the Web. Learn how to best implement a security strategy that keeps consumers' information secure and instills the confidence they need to proceed with transactions. http://p.sf.net/sfu/oracle-sfdevnl ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
RE: [PATCH 1/3] spi_topcliff_pch: support new device ML7213
Hi Grant, Sorry, I made mistake in my-mail address. I sent again. On Thursday, January 06, 2011 1:39 AM, Grant Likely wrote: As far as examples go, drivers/mfd/timberdale.c seems reasonable, if a bit larger than what you need. Thank you for your suggestion. However, though seeing this driver, I didn't understand your intention. It seems platform_device/platform_driver are not used in this. Which part of this driver do you want to show me as reference ? Thanks, - Tomoya MORINAGA OKI SEMICONDUCTOR CO., LTD. -- Gaining the trust of online customers is vital for the success of any company that requires sensitive data to be transmitted over the Web. Learn how to best implement a security strategy that keeps consumers' information secure and instills the confidence they need to proceed with transactions. http://p.sf.net/sfu/oracle-sfdevnl ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH 2/3] spi_topcliff_pch: change calling function order correctly in remove
Signed-off-by: Tomoya MORINAGA tomoya-li...@dsn.okisemi.com --- drivers/spi/spi_topcliff_pch.c | 10 +- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi_topcliff_pch.c b/drivers/spi/spi_topcliff_pch.c index 18e077b..a796eaf 100644 --- a/drivers/spi/spi_topcliff_pch.c +++ b/drivers/spi/spi_topcliff_pch.c @@ -1166,21 +1166,21 @@ static void pch_spi_remove(struct pci_dev *pdev) spin_unlock(board_dat-data[i]-lock); } - /* Free resources allocated for PCH SPI */ - pch_spi_free_resources(board_dat); - /* Unregister SPI master */ for (i = 0; i board_dat-num; i++) spi_unregister_master(board_dat-data[i]-master); - /* free memory for private data */ - kfree(board_dat); + /* Free resources allocated for PCH SPI */ + pch_spi_free_resources(board_dat); pci_set_drvdata(pdev, NULL); /* disable PCI device */ pci_disable_device(pdev); + /* free memory for private data */ + kfree(board_dat); + dev_dbg(pdev-dev, %s invoked pci_disable_device\n, __func__); } -- 1.6.0.6 -- Learn how Oracle Real Application Clusters (RAC) One Node allows customers to consolidate database storage, standardize their database environment, and, should the need arise, upgrade to a full multi-node Oracle RAC database without downtime or disruption http://p.sf.net/sfu/oracle-sfdevnl ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH 3/3] spi_topcliff_pch: fix resource leak issue
In case spi_register_master fails in probe function, pch_spi_free_resources is not called. Signed-off-by: Tomoya MORINAGA tomoya-li...@dsn.okisemi.com --- drivers/spi/spi_topcliff_pch.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/drivers/spi/spi_topcliff_pch.c b/drivers/spi/spi_topcliff_pch.c index a796eaf..e806e31 100644 --- a/drivers/spi/spi_topcliff_pch.c +++ b/drivers/spi/spi_topcliff_pch.c @@ -1125,6 +1125,7 @@ static int pch_spi_probe(struct pci_dev *pdev, const struct pci_device_id *id) err_spi_reg_master: for (j = 0; j i; j++) spi_unregister_master(master[j]); + pch_spi_free_resources(board_dat); err_spi_get_resources: err_spi_alloc_master: for (j = 0; j i; j++) -- 1.6.0.6 -- Learn how Oracle Real Application Clusters (RAC) One Node allows customers to consolidate database storage, standardize their database environment, and, should the need arise, upgrade to a full multi-node Oracle RAC database without downtime or disruption http://p.sf.net/sfu/oracle-sfdevnl ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH 1/3] spi_topcliff_pch: support new device ML7213
Support ML7213 device of OKI SEMICONDUCTOR.
ML7213 is companion chip of Intel Atom E6xx series for IVI(In-Vehicle
Infotainment).
ML7213 is completely compatible for Intel EG20T PCH.
Signed-off-by: Tomoya MORINAGA tomoya-li...@dsn.okisemi.com
---
drivers/spi/spi_topcliff_pch.c | 293 +++-
1 files changed, 172 insertions(+), 121 deletions(-)
diff --git a/drivers/spi/spi_topcliff_pch.c b/drivers/spi/spi_topcliff_pch.c
index 58e187f..18e077b 100644
--- a/drivers/spi/spi_topcliff_pch.c
+++ b/drivers/spi/spi_topcliff_pch.c
@@ -35,6 +35,7 @@
#define PCH_SPDRR 0x10/* SPI read data register */
#define PCH_SSNXCR 0x18/* SSN Expand Control Register */
#define PCH_SRST 0x1C/* SPI reset register */
+#define PCH_SPI_ADDRESS_SIZE 0x20
#define PCH_SPSR_TFD 0x07C0
#define PCH_SPSR_RFD 0xF800
@@ -88,6 +89,16 @@
#define PCH_CLOCK_HZ 5000
#define PCH_MAX_SPBR 1023
+/* Definition for ML7213 by OKI SEMICONDUCTOR */
+#define PCI_VENDOR_ID_ROHM 0x10DB
+#define PCI_DEVICE_ID_ML7213_SPI 0x802c
+
+/*
+Set the number of SPI instance max
+Intel EG20T PCH : 1ch
+OKI SEMICONDUCTOR ML7213 IOH : 2ch
+*/
+#define PCH_SPI_MAX_DEV2
/**
* struct pch_spi_data - Holds the SPI channel specific details
@@ -153,18 +164,21 @@ struct pch_spi_data {
* @pci_req_sts: Status of pci_request_regions
* @suspend_sts: Status of suspend
* @data: Pointer to SPI channel data structure
+ * @num: The number of SPI device instance
*/
struct pch_spi_board_data {
struct pci_dev *pdev;
u8 irq_reg_sts;
u8 pci_req_sts;
u8 suspend_sts;
- struct pch_spi_data *data;
+ struct pch_spi_data *data[PCH_SPI_MAX_DEV];
+ int num;
};
static struct pci_device_id pch_spi_pcidev_id[] = {
- {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_GE_SPI)},
- {0,}
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI),1, },
+ { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
+ { }
};
/**
@@ -267,7 +281,7 @@ static void pch_spi_handler_sub(struct pch_spi_data *data,
u32 reg_spsr_val,
if (reg_spsr_val SPSR_FI_BIT) {
/* disable FI RFI interrupts */
pch_spi_setclr_reg(data-master, PCH_SPCR, 0,
- SPCR_FIE_BIT | SPCR_TFIE_BIT);
+ SPCR_FIE_BIT | SPCR_RFIE_BIT);
/* transfer is completed;inform pch_spi_process_messages */
data-transfer_complete = true;
@@ -288,6 +302,7 @@ static irqreturn_t pch_spi_handler(int irq, void *dev_id)
void __iomem *io_remap_addr;
irqreturn_t ret = IRQ_NONE;
struct pch_spi_board_data *board_dat = dev_id;
+ int i;
if (board_dat-suspend_sts) {
dev_dbg(board_dat-pdev-dev,
@@ -295,21 +310,22 @@ static irqreturn_t pch_spi_handler(int irq, void *dev_id)
return IRQ_NONE;
}
- data = board_dat-data;
- io_remap_addr = data-io_remap_addr;
- spsr = io_remap_addr + PCH_SPSR;
+ for (i = 0; i board_dat-num; i++) {
+ data = board_dat-data[i];
+ io_remap_addr = data-io_remap_addr;
+ spsr = io_remap_addr + PCH_SPSR;
- reg_spsr_val = ioread32(spsr);
+ reg_spsr_val = ioread32(spsr);
- /* Check if the interrupt is for SPI device */
- if (reg_spsr_val (SPSR_FI_BIT | SPSR_RFI_BIT)) {
- pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr);
- ret = IRQ_HANDLED;
- }
-
- dev_dbg(board_dat-pdev-dev, %s EXIT return value=%d\n,
- __func__, ret);
+ /* Check if the interrupt is for SPI device */
+ if (reg_spsr_val (SPSR_FI_BIT | SPSR_RFI_BIT)) {
+ pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr);
+ ret = IRQ_HANDLED;
+ }
+ dev_dbg(board_dat-pdev-dev, %s EXIT return value=%d\n,
+ __func__, ret);
+ }
return ret;
}
@@ -679,11 +695,11 @@ static void pch_spi_set_ir(struct pch_spi_data *data)
if ((data-bpw_len) PCH_MAX_FIFO_DEPTH) {
/* set receive threhold to PCH_RX_THOLD */
pch_spi_setclr_reg(data-master, PCH_SPCR,
- PCH_RX_THOLD SPCR_TFIC_FIELD,
- ~MASK_TFIC_SPCR_BITS);
+ PCH_RX_THOLD SPCR_RFIC_FIELD,
+ ~MASK_RFIC_SPCR_BITS);
/* enable FI and RFI interrupts */
pch_spi_setclr_reg(data-master, PCH_SPCR,
- SPCR_RFIE_BIT | SPCR_TFIE_BIT, 0);
+ SPCR_RFIE_BIT | SPCR_FIE_BIT, 0
[PATCH] spi_topcliff_pch: Fix data transfer issue
It seems spi_topcliff_pch of linux-2.6.37-rc6 degraded by previous patch.
In fact, data transfer fails on evaluation board testing.
I found like the following register miss-setting line.
Using this patch, I have confirmed data transfer can work well.
Signed-off-by: Tomoya MORINAGA tomoya-li...@dsn.okisemi.com
---
drivers/spi/spi_topcliff_pch.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi_topcliff_pch.c b/drivers/spi/spi_topcliff_pch.c
index 58e187f..56b7588 100644
--- a/drivers/spi/spi_topcliff_pch.c
+++ b/drivers/spi/spi_topcliff_pch.c
@@ -267,7 +267,7 @@ static void pch_spi_handler_sub(struct pch_spi_data *data,
u32 reg_spsr_val,
if (reg_spsr_val SPSR_FI_BIT) {
/* disable FI RFI interrupts */
pch_spi_setclr_reg(data-master, PCH_SPCR, 0,
- SPCR_FIE_BIT | SPCR_TFIE_BIT);
+ SPCR_FIE_BIT | SPCR_RFIE_BIT);
/* transfer is completed;inform pch_spi_process_messages */
data-transfer_complete = true;
@@ -679,11 +679,11 @@ static void pch_spi_set_ir(struct pch_spi_data *data)
if ((data-bpw_len) PCH_MAX_FIFO_DEPTH) {
/* set receive threhold to PCH_RX_THOLD */
pch_spi_setclr_reg(data-master, PCH_SPCR,
- PCH_RX_THOLD SPCR_TFIC_FIELD,
- ~MASK_TFIC_SPCR_BITS);
+ PCH_RX_THOLD SPCR_RFIC_FIELD,
+ ~MASK_RFIC_SPCR_BITS);
/* enable FI and RFI interrupts */
pch_spi_setclr_reg(data-master, PCH_SPCR,
- SPCR_RFIE_BIT | SPCR_TFIE_BIT, 0);
+ SPCR_RFIE_BIT | SPCR_FIE_BIT, 0);
} else {
/* set receive threhold to maximum */
pch_spi_setclr_reg(data-master, PCH_SPCR,
--
1.6.0.6
--
Learn how Oracle Real Application Clusters (RAC) One Node allows customers
to consolidate database storage, standardize their database environment, and,
should the need arise, upgrade to a full multi-node Oracle RAC database
without downtime or disruption
http://p.sf.net/sfu/oracle-sfdevnl
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH] spi_topcliff_pch: Fix data transfer issue
Sorry, I forget to add --CCs
It seems spi_topcliff_pch of linux-2.6.37-rc6 degraded by previous patch.
In fact, data transfer fails on evaluation board testing.
I found like the following register miss-setting line.
Using this patch, I have confirmed data transfer can work well.
Signed-off-by: Tomoya MORINAGA tomoya-li...@dsn.okisemi.com
---
drivers/spi/spi_topcliff_pch.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi_topcliff_pch.c b/drivers/spi/spi_topcliff_pch.c
index 58e187f..56b7588 100644
--- a/drivers/spi/spi_topcliff_pch.c
+++ b/drivers/spi/spi_topcliff_pch.c
@@ -267,7 +267,7 @@ static void pch_spi_handler_sub(struct pch_spi_data *data,
u32 reg_spsr_val,
if (reg_spsr_val SPSR_FI_BIT) {
/* disable FI RFI interrupts */
pch_spi_setclr_reg(data-master, PCH_SPCR, 0,
- SPCR_FIE_BIT | SPCR_TFIE_BIT);
+ SPCR_FIE_BIT | SPCR_RFIE_BIT);
/* transfer is completed;inform pch_spi_process_messages */
data-transfer_complete = true;
@@ -679,11 +679,11 @@ static void pch_spi_set_ir(struct pch_spi_data *data)
if ((data-bpw_len) PCH_MAX_FIFO_DEPTH) {
/* set receive threhold to PCH_RX_THOLD */
pch_spi_setclr_reg(data-master, PCH_SPCR,
- PCH_RX_THOLD SPCR_TFIC_FIELD,
- ~MASK_TFIC_SPCR_BITS);
+ PCH_RX_THOLD SPCR_RFIC_FIELD,
+ ~MASK_RFIC_SPCR_BITS);
/* enable FI and RFI interrupts */
pch_spi_setclr_reg(data-master, PCH_SPCR,
- SPCR_RFIE_BIT | SPCR_TFIE_BIT, 0);
+ SPCR_RFIE_BIT | SPCR_FIE_BIT, 0);
} else {
/* set receive threhold to maximum */
pch_spi_setclr_reg(data-master, PCH_SPCR,
--
1.6.0.6
--
Learn how Oracle Real Application Clusters (RAC) One Node allows customers
to consolidate database storage, standardize their database environment, and,
should the need arise, upgrade to a full multi-node Oracle RAC database
without downtime or disruption
http://p.sf.net/sfu/oracle-sfdevnl
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
